Arithmetic Circuit for Obtaining the Vector Product of Two Vectors

1. Field of the Invention

This invention relates to an arithmetic circuit applied to an encoder and a decoder of an error correction code.

2. Background of the Invention

When a digital video signal, a digital audio signal and the like are recorded and reproduced, an adjacent code or Reed-Solomon code is practically normally used as an error correction code. Parity data (redundant data) is generated in an encoder of such error correction signal, and a syndrome is generated in a decoder from a received word including the parity data. Error correction is performed using the syndrome. An arithmetic circuit for processing the elements of a finite field is used as the hardware of the parity generating circuit, the syndrome generating circuit and the error correction circuit. The finite field is a field of pm elements derived from an irreducible polynomial of m-th order, and the case where p=2 is important for the error correction code. Consequently, this invention is applied to the finite field where p=2.

In a conventional arithmetic circuit used in an encoder and a decoder, when multiplication of elements of the finite field is executed, for example, in the case of (.alpha.i, .alpha.j), .alpha.i is stored in a ROM (read-only memory) so as to obtain the exponent i and .alpha.j is similarly stored in a ROM so as to obtain the exponent j. An adder produces the exponent (i+j) which is stored in a ROM, whereby conversion to .alpha.i+j is achieved. In the finite field GF (2m), addition (also subtraction) can be simply implemented using an exclusive-OR gate, but as clearly seen from above-mentioned example, a number of ROMs and registers are required to execute multiplication or division and thereby the scale of the circuit is inevitably enlarged. Moreover, the conventional arithmetic circuit is constituted by dedicated hardware of each kind of polynomial or operation and therefore cannot be used for general purposes.

Accordingly, an object of the invention is to provide an improved arithmetic circuit wherein the necessary amount of memories such as ROMs and registers is decreased and the scale of the circuit is reduced.

Another object of the invention is to provide an arithmetic circuit that can execute an operation such as multiplication, division or raising to a power, using arbitarary elements of a finite field.

Still another object of the invention is to provide an arithmetic circuit that is suitable for use as an encoder and a decoder of an error correction code.

According to this invention, a first input of m bits, being a vector expression of the elements of a finite field GF (2m), is converted into components of a matrix expression of the same components. Each component of the matrix is multiplied with a second input of m bits which are a vector expression of the elements of the finite field GF (2m). This multiplication of the first and second inputs is obtained as a vector expression of the finite field GF (2m).

FIG. 1 is a schematic diagram illustrating the relation between the elements of a finite field and the matrix expression thereof;

FIG. 2 is a connection diagram of a converter to convert data of a vector expression into components of a matrix expression;

FIG. 3 is a connection diagram of an embodiment of the invention;

FIG. 4 is a block diagram of another embodiment of the invention;

FIG. 5 is a time chart illustrating operation of embodiment in FIG. 4;

and FIG. 6 is a connection diagram of still another embodiment of the invention.

An embodiment of the invention will now be described regarding the finite field GF (2m) for easy understanding.

First, the relation between a generator polynomial g(x) and an element .alpha.i of GF (2m) will be described. For example, assume that g(x)=x.sup.4 +x+1. The coefficients of the generator polynomial g(x) in power descending order are respectively (1, 0, 0, 1, 1). Corresponding to the coefficients, a shift register circuit having a feedback loop can be constituted as shown in FIG. 1(A). In FIG. 1(A), an adder inserted between a register of the first stage and a register of the next stage adds (mod. 2).

If an initial value (1000) is set in the shift register circuit as shown in FIG. 1(B) and then the shift operation is executed in sequence, the content of each register varies as shown in FIG. 1(B). If the root of g(x)=0 is made .alpha.(=.alpha..sup.1), .alpha..sup.4 +.alpha.+1=0 hence .alpha..sup.4 =.alpha.+1. Consequently, variation in the content of the registers shown in FIG. 1(B) is expressed as a power of .alpha. as follows: ##EQU1##

Elements having a value of .alpha..sup.4 or more are expressed as linear combinations of .alpha..sup.o, .alpha..sup.1, .alpha..sup.2, .alpha..sup.3 using the equation (.alpha..sup.4 =.alpha.+1). That is, ##EQU2## Thus the expression of .alpha..sup.4 or more using a vector expression of .alpha..sup.0 -.alpha..sup.3 is shown in FIG. 1(B).

Next, a relation between .alpha. and the matrix T will be described. If g(x)=x.sup.4 +x+1, the adjoint matrix T becomes ##EQU3## If .alpha..sup.i is FIG. 1(B) in a column vector, it follows that

Then T.sup.2 becomes ##EQU4## Expressing T.sup.2 using .alpha..sup.i, it follows that T.sup.2 =[.alpha..sup.2, .alpha..sup.3, .alpha..sup.4, .alpha..sup.5 ]. That is,

wherein i=0, 1, 2, . . . , 14, and i+1, i+2, i+3 may be estimated in (mod. 15). In other words, the first row of T.sup.i is coincident with .alpha..sup.i, the vector expression of .alpha..

Next, the expression .alpha..sup.i .times..alpha..sup.j =.alpha..sup.i+j will be described. Although vectors cannot be mutually multiplied, a matrix can be multiplied with a vector. Consequently, if the .alpha..sup.i is converted into the matrix expression T.sup.i, the multiplication of .alpha..sup.i .times..alpha..sup.j becomes possible. The multiplication of T with .alpha. is ##EQU5## If i=2 or more, it follows that

It is understood generally that T.alpha..sup.i =.alpha..sup.i+1. From this relation, it follows that

In general, the expression .alpha..sup.i+j =T.sup.i .multidot..alpha..sup.j holds. As a result of the above relation, the .alpha..sup.i and the T.sup.i may be deemed identical in multiplication, and therefore in order to calculate the expression .alpha..sup.i .times..alpha..sup.j, the expression T.sup.i .times..alpha..sup.j may be calculated.

Since T.sup.i may be expressed as T.sup.i =[.alpha..sup.i, .alpha..sup.i+1, .alpha..sup.i+2, .alpha..sup.i+3 ] as above described, if another vector can be produced from .alpha..sup.i, it follows that all components of the matrix T.sup.i can be known. Consequently, by multiplying these components with .alpha..sup.j, the multiplication of (.alpha..sup.i .times..alpha..sup.j) can be executed.

FIG. 2 shows a circuit for converting .alpha..sup.1 expressed as a vector into a matrix expression T.sup.1 wherein g(x)=x.sup.4 +x+1. Using the shift register circuit having the feedback loop shown in FIG. 1(A), each register .alpha..sup.i is set and the shift operation is executed three times so as to generate .alpha..sup.i+1, .alpha..sup.i+2, .alpha..sup.i+3 in sequence. Consequently, four registers 1, 2, 3, 4 in FIG. 2 are supplied with .alpha..sup.i, say .alpha..sup.1, from outside, and, by means of a connection equivalent to thence shift operations, the components of the matrix T.sup.1 can be generated simultaneously at the outputs of the four input registers at positions shown by broken lines in FIG. 2. That is, the output side of the registers 1 through 4 is shifted downwards by one bit, and the most significant bit and the least significant bit are added by adders 22, 23, 24 (mod. 2) at every shifting operation.

FIG. 3 shows a circuit construction showing an embodiment of the invention, wherein the inputs .alpha..sup.i (a.sub.o, a.sub.1, a.sub.2, a.sub.3 from the LSB (least significant bit)) are supplied. Coefficients g.sub.i of the generator polynomial g(x) are supplied to cascade connected registers 5, 6, 7, and the coefficients g.sub.3, g.sub.2, g.sub.1 are taken from the registers 5, 6, 7. If g(x)=x.sup.4 +x+1, it follows that g.sub.1 -1, g.sub.2 =g.sub.3 =0. The coefficient g.sub.1 is supplied to AND gates 8, 11, 14, the coefficient g.sub.2 is supplied to AND gates 9, 12, 15, and the coefficient g.sub.3 is supplied to AND gates 10, 13, 16.

Outputs of the AND gates 8, 9, 10 are supplied to exclusive-OR gates (hereinafter referred to as EXOR gates) 22, 32, 42 respectively at respective first inputs of the EXOR gates. Outputs of the AND gates 11, 12, 13 are supplied to EXOR gates 23, 33, 43 respectively at respective first inputs thereof. Outputs of the AND gates 14, 15, 16 are supplied to EXOR gates 24, 34, 44 respectively at respective first inputs thereof. The respective sets of the three AND gates in each line are commonly supplied with the MSB (most significant bit) from the previous line. The respective sets of the three AND gates in each line always become 0 when the coefficient g.sub.i of the generator polynomial is 0, and the former supplies the feedback data to the EXOR gate when the coefficient g.sub.i is 1. For example, when g.sub.1 =1 and g.sub.2 =g.sub.3 =0, the EXOR gates 22, 23, 24 act as an adder mod. 2 and other EXOR gates only make the state of the preceding AND gates pass as it is.

Consequently, the MSB in the previous line and outputs of the EXOR gates 22, 23, 24, . . . , 44 constitute all the components of a matrix corresponding to the inputs a.sub.0 through a.sub.3. Elements (b.sub.o, b.sub.1, b.sub.2, b.sub.3) of another field GF(2m) multiplied with the inputs converted into a matrix expression are written in registers 51, 52, 53, 54. The multiplication of the elements (b.sub.o, b.sub.1, b.sub.2, b.sub.3,) by the matrix components is represented by ##EQU6## and the outputs c.sub.o, c.sub.1, c.sub.2, c.sub.3 of the multiplication are as follows: ##EQU7##

The multiplication to generate the output c.sub.o is executed by AND gates 61, 62, 63, 64, and the addition is executed by EXOR gates 65, 66, 67. The output of the EXOR gate 67 is stored as c.sub.o in a register 101.

The multiplication to generate the output c.sub.1 is executed by AND gates 71, 72, 73, 74, and the addition is executed by EXOR gates 75, 76, 77. The output of the EXOR gate 77 is stored as c.sub.1 in a register 102. Similarly, the output c.sub.2 formed by AND gates 81, 82, 83, 84 and EXOR gates 85, 86, 87 is stored in a register 103, and the output c.sub.3 formed by AND gates 91, 92, 93, 94 and EXOR gates 95, 96, 97 is stored in a register 104.

Thus the circuit shown in FIG. 3 can be used for multiplying the two vectors of the finite field GF(2m) so as to generate a vector product output and change the generator polynomial g(x).

In above-mentioned embodiment of the invention, assume that (a.sub.o, a.sub.1, a.sub.2, a.sub.3) is input A, (b.sub.o, b.sub.1, b.sub.2, b.sub.3) is input B, and (c.sub.o, c.sub.1, c.sub.2, c.sub.3) is output C. Then if .alpha..sup.N is supplied as input A, output C of .alpha..sup.N. B is obtained, wherein N is a value arbitrarily determined among (0, 1, 2, . . . , 2m-2), and .alpha..sup.N can be formed by supplying N as the address of a ROM. Similarly, .alpha..sup.N can be generated by another ROM so as to form the output C of .alpha..sup.-N. B, and further .alpha..sup.-i can be generated by another ROM so as to form output C of .alpha..sup.-i .multidot.B.

Another embodiment of the invention, shown in FIG. 4, is an arithmetic circuit where a multiplier shown in FIG. 3 is used, and various operations as are described above can be executed without using a ROM.

In FIG. 4, reference numerals 111 and 121 designate converters to convert input data expressed as vectors into components of matrix T, and numerals 112 and 122 designate registers of m bits to store inputs to the converters 111 and 121. The converters 111 and 121 are supplied with coefficients of the generation polynominal from a shift register 117. The shift register 117 executes a shift operation in response to a clock CKG. Numerals 113 and 123 designate multiplication gates to execute matrix multiplication of components of the matrix T from the converters 111 and 121 with data of m bits representing a vector. The multiplication gates 113 and 123 are supplied with data of m bits from registers 114 and 124.

Input data to the register 112 is selected by a multiplexer 115 which is controlled by select signal S.sub.1. Input data to the register 114 is selected by a multiplexer 116 which is controlled by select signal S.sub.2. Similarly, the registers 122 and 124 are supplied with data selected by multiplexers 125 and 126, respectively. The multiplexers 125 and 126 are controlled by select signals S.sub.3 and S.sub.4, respectively. The multiplication output of the multiplication gate 113 is supplied to EXOR gate 118; the multiplication output of the multiplication gate 123 is supplied through AND gate 119 to the EXOR gate 118. The AND gate 119 is supplied with a control signal SA, and, if the control signal SA is 1, the addition output (mod. 2) from outputs of both multiplication gates 113 and 123 is taken as output signal C. If the control signal SA is 0, the output of the multiplication gate 113 becomes output signal C.

The multiplexers 115, 116, 125, 126 are supplied with input data of m bits E, A, F, B respectively at data inputs of the multiplexers. The output data C is fed back as additional input data to the multiplexers 115, 116, 125. Further, the multiplication output of the multiplication gate 123 is fed back as additional input data to the multiplexer 126. The output data of the multiplication gate 123 is taken as output data P.

In the arithmetic circuit shown in FIG. 4, the operation mode set by the select signals S.sub.1 -S.sub.4 and the control signal SA will be described.

First, the operation mode will be described when all select signals S.sub.1, S.sub.2, S.sub.3, S.sub.4 are 0 and the control signal SA is 1. Then the input data E, A, F, B are selected by the multiplexers 115, 116, 125, 126 respectively, and the multiplication output of the multiplication gate 123 is supplied through the AND gate 119 to the EXOR gate 118. Consequently, if matrices of the converters 111 and 121 are designated by T.sub.1 and T.sub.2 respectively, the output data C of (C=T.sub.1 A+T.sub.2 B) is obtained. If the input data E and F are .alpha..sup.i and .alpha..sup.j respectively, it follows that T.sub.1 =T.sup.i, T.sub.2 =T.sup.j. Consequently, the operation

can be executed. This operation is required in order to implement an error correction circuit.

The operation .beta..sup.N will be described as a second example. Since the number of the power is usually given in binary notation, GF(2.sup.4) where m=4 will be studied. Then the number of the power N is expressed as follows:

Consequently, the operation .beta..sup.N is executed as follows:

wherein n.sub.o, n.sub.1, n.sub.2, n.sub.3 are 0 or 1. Consequently, .beta..sup.2, .beta..sup.4, .beta..sup.8 may be formed from a given .beta., and the power operation be executed according to the number of the power.

The procedure during the arithmetic operation of .beta..sup.N will be described referring to FIG. 5. FIG. 5(A) shows clocks of the arithmetic circuit, and the select signals S.sub.1 and S.sub.2 are 0 during the time t.sub.1, t.sub.2 as shown in FIG. 5(B) and FIG. 5(C). Data .beta. of four bits is entered as input data E, and .alpha..sup.o (=1000) is entered as input data A, F, B. The select signals S.sub.1 and S.sub.2 become 1 at time t.sub.3 and calculation is started.

Input data .beta. and .alpha..sup.o are outputted from the multiplexer 115 and 116 as shown in FIG. 5(D) and FIG. 5(E), and these data are outputted from the registers 112 and 114 with a delay of one clock as shown in FIG. 5(F) and FIG. 5(G). At time t.sub.3, the output of the register 112 becomes .beta. and the output of the register 114 becomes .alpha..sup.o. Since the control signal SA is 0 and output .beta. of the multiplication gate 113 is fed back through the multiplexer 115 and 116 to the registers 112 and 114, the outputs of the registers 112 and 114 become .beta. at time t.sub.4. The outputs of the registers 112 and 114 become .beta..sup.2 at time t.sub.5, and then vary to .beta..sup.4, .beta..sup.6, .beta..sup.8. FIG. 5(H) shows the output of the multiplication gate 113.

The output of the multiplication gate 113 is supplied through the EXOR gate 118 to the multiplexer 125. Select signal S.sub.3 of the multiplexer 125 is changed at every clock corresponding to binary expression of the exponent N (n.sub.o, n.sub.1, n.sub.2, n.sub.3) as shown in FIG. 5(I). If the select signal S.sub.3 is 0, the input data F (=.alpha..sup.o) is selected; if the select signal S.sub.3 is 1, the output data of the multiplication gate 113 is selected. Consequently, the output of the multiplexer 125 becomes .beta..sup.n.sbsp.o, .beta..sup.2n.sbsp.1, .beta..sup.4n.sbsp.2, .beta..sup.8n.sbsp.3 in sequence as shown in FIG. 5(K), and the output of the register 122 becomes the output of the multiplexer 125 with a delay of one clock as shown in FIG. 5(M).

Select signal S.sub.4 becomes 1 at time t.sub.4 as shown in FIG. 5(J), and the output of the multiplication gate 123 is selected from input data B (=.alpha..sup.o) after time t.sub.4. FIG. 5(L) shows the output of the multiplexer 126, and the output of the multiplexer 126 is taken in the register 124 which produces the output shown in FIG. 5(N). At time t.sub.4, .beta..sup.n.sbsp.o from the register 122 and .alpha..sup.o from the register 124 are supplied to the multiplication gate 123. The output data P of (.alpha..sup.o x.beta..sup.n.sbsp.o =.beta..sup.n.sbsp.o) shown in FIG. 5(O) is generated. At time t.sub.5, since the input to the multiplication gate 123 becomes .beta..sup.2n.sbsp.1 and .beta..sup..sbsp.o, the output P of the multiplication gate 123 becomes .beta..sup.n.sbsp.o.sup.+2n.sbsp.1. Similarly, corresponding to the input supplied to the multiplication gate 123 at time t.sub.6, t.sub.7, the output P of .beta..sup.n.sbsp.o.sup.+2n.sbsp.1.sup. +4n.sbsp.2.sup.+8n.sbsp.3 is obtained from the multiplication gate 123. Although not shown, the output data P is passed through a register and thereby synchronized with the clock and value .beta..sup.8 is outputted at time t.sub.8.

The operation mode of .beta..sup.-1 will be described as a third example. In a finite field of GF(2.sup.4), since an arbitrary element .beta. other than 0 is

it follows that

That is, N may be made (N=14) and if N=(0111) is inputted as a select signal S.sub.3, .beta..sup.-1 is outputted as output data P. In calculating mod. (2m-1), values of N in binary notation may be all converted in order to change N into -N.

In a fourth operation mode of .beta..sup.-N, binary notation of the number of power N may be only converted. Consequently, if .beta. is supplied as input data E and .alpha..sup.o is supplied as input data A, F, B, and the converted number of the power N as the select signal S.sub.3 is supplied from the LSB in sequence, .beta..sup.-N can be obtained as the output data P.

A fifth operation mode (.beta..sup.N .times..gamma., .beta..sup.-N .times..gamma.) will be described. This is nearly identical to the second and third operation modes, and .gamma. may be entered as input data B in place of .alpha..sup.o.

A sixth operation mode (.alpha..sup.i x, .alpha..sup.-i x) will be described. In this case, .alpha. may be supplied as input data E, .alpha..sup.o be supplied as input data A, F and .gamma. be supplied as input data B, and further binary notation data of exponent i or -i be supplied from the LSB in sequence.

As shown in FIG. 6, in order to mutually multiply elements of a finite field GF(2.sup.4) representing vectors, all components of one element in the matrix expression (16 bits) may be entered from input terminal 131 in series to the shift register circuit, and components of 16 bits be multiplied by the vector (b0, b1, b2, b3). In FIG. 6, each register of the shift register circuit is designated by a suffix of each component of the matrix, and AND gates and EXOR gates to constitute the multiplication gate are designated by reference numerals identical to those in FIG. 3.