Integrated High Gain Voltage Controlled Oscillator

The present invention relates generally to the field of oscillators and more particularly to voltage controlled oscillators of the type used, for example, in phase locked loop (PLL) circuits.

Voltage controlled oscillator (VCO) circuits produce output signals whose frequency varies as a function of an input control voltage. These circuits are widely used in systems employing PLL circuits as well as in any system where a variable frequency output signal is required as a function in an input signal.

In data communication systems PLL circuits have been employed for extracting clock information from a received signal which permits data processing systems at remote locations to operate synchronously. Examples of such applications are described in U.S. Pat. No. 4,131,861 to Malaviya entitled "Variable Frequency Oscillator System Including Two Matched Oscillators Controlled by a Phase Locked Loop," and U.S. Pat. No. 4,513,427 to Boriello et al. entitled "Data and Clock Recovery System for Data Communication Controller." VCOs in these applications preferably have a highly stable center frequency at or near the desired system clock frequency, and a high gain or change in output frequency for a given change in input voltage. Finally, it is particularly advantageous if the VCO can be integrated on the same chip with the PLL and other circuits in order to reduce the size, power requirements, delay and cost of the system.

Highly stable VCOs have been fabricated using inherently stable frequency-determining components such as varactor diodes, bulk crystal devices, and bulk and surface acoustic wave devices. A relatively high VCO gain (MHz/volt) can be achieved by means of operational amplifiers such as in U.S. Pat. No. 4,118,674, which employs a crystal oscillator. However, these components are not integratable on a chip with the other required components in a VCO or PLL.

Another VCO configuration used in prior systems employs cascaded inverters connected in a ring configuration to form a ring oscillator as described, for example, in U.S. Pat. No. 4,072,910 to Dingwall et al. entitled "Voltage Controlled Oscillator Having Equally Controlled Current Source and Current Sink." Other ring oscillator VCOs are described in U.S. Pat. Nos. 4,052,673 and 4,513,427. Such oscillators have the advantages of small size, low cost, a large tuning range and they are integratable. The maximum frequency of a ring oscillator is limited by the logic speed, i.e., the switching delay of the devices used to form the inverter circuits. U.S. Pat. No. 4,513,427, cited above, describes a ring oscillator VCO employing a tapped delay line. While the components are contained on a single integrated circuit chip, the oscillator frequency in the disclosed embodiment is on the order of 40 MHz. and the data transfer rate is 10 Mbits/sec. For much higher data rates, which necessitate even higher clock frequencies, the tapped delay line technique will not suffice.

In the case of data processing systems including communication links wherein the data transfer rates are on the order of several hundred Mbits/sec., a VCO having a center frequency of several hundred MHz. and a gain of at least 1 GHz./volt is required in order to achieve acceptable noise performance. Known VCO arrangements cannot achieve this performance with a circuit formed on a single integrated circuit chip.

It is therefore an object of the present invention to provide a voltage controlled oscillator capable of high frequency and high gain operation, with all of the components thereof integratable on a single integrated circuit chip.

Another object of the invention is to provide a VCO formed of a plurality of cascaded inverter circuits in a ring configuration wherein the center frequency and the gain of the VCO are selectable.

Still another object of the invention is to provide an integratable VCO useful in phased locked loop and other applications.

In accordance with one embodiment of the present invention a voltage controlled oscillator is formed of a plurality of cascaded inverter circuits in a ring configuration. Each inverter is a grounded emitter circuit having an active pull-up stage in order to achieve a short gate delay. The frequency of the ring oscillator is determined by the number of inverter stages, and the gain is selectable by coupling an external control voltage to only certain of the inverters. The VCO may be fabricated on a single integrated circuit along with the other circuits necessary to form a PLL, frequency synthesizer, or other such frequency generation system.

Other objects and many of the attendant advantages of the present invention will be better understood by reference to the following detailed description in conjunction with the accompanying drawings, wherein:

FIG. 1 is a block diagram of a voltage controlled oscillator according to the present invention;

FIG. 2 is a schematic diagram of an inverter stage employed in the VCO of FIG. 1;

FIG. 3 is a graph showing the frequency of the VCO of FIG. 1 as a function of the control voltage;

FIG. 4 is a simplified block diagram of an alternative VCO control voltage generator; and

FIG. 5 is a block diagram of a phase locked loop system including the VCO of the present invention.

Referring now to the drawings, there is shown in FIG. 1 a VCO 10 according to one embodiment of the present invention. VCO 10 is formed of plurality of cascaded inverter stages 12 connected in a ring oscillator configuration, with each inverter 12 having an input 14 connected to the output 16 of the previous inverter stage 12. A VCO control voltage generator 18 has an output connected to a control input 20 of each inverter stage 12. The VCO generator 18 provides a control voltage signal which varies the frequency of VCO 10. The control voltage signal is comprised of a fixed bias to set the nominal operating frequency of VCO 10, and an external voltage signal V.sub.ext to vary the VCO frequency about the nominal frequency. The output f.sub.out a terminal 22 of VCO 10 may be taken across the input 14 and output 16 of any of the inverter stages 12. A differential current switch logic gate may be placed across terminal 22 to amplify the signal swing to achieve a greater noise margin. An eleven stage VCO is shown in FIG. 1 for illustrative purposes only. A greater or lesser number of stages can be used depending upon the desired center frequency of the VCO, as long as there is an odd number of stages. The VCO frequency f is determined by the expression

where N is the number of stages and D is the average delay of each stage. Thus, as the delay is reduced the VCO frequency increases.

FIG. 2 shows a schematic diagram of one of the VCO inverter stages 12. Each stage 12 is a grounded emitter inverter with an active pull-up circuit. The input signal V.sub.in to the base of transistor T1 is the output from the previous inverter stage. The emitter of T1 is grounded and the collector of T1 is the output of inverter 12. The emitter of a pull-up transistor T2 is also connected to the collector of T1. The input signal V.sub.gen to the emitter of T2 at terminal 20 is the control voltage from VCO generator 18. The collector of T2 is connected to the system power supply V.sub.CC, and a pull-up resistor R.sub.pu is connected between the base and emitter of T2.

In operation, the "up" level at the base of T1, i.e., the voltage when T1 is on, is the base-emitter voltage V.sub.be of T1 at its "on" current. This current is determined by V.sub.gen and R.sub.pu. The "down" level at the base of T1 is V.sub.gen -V.sub.be (T2) at a current that is the total of the current from the previous stage minus the current flowing in R.sub.pu. Pull-up transistor T2 and resistor R.sub.pu contribute to the short delay of inverter 12 as follows. When inverter 12 is on current is flowing through both T1 and T2. When the input V.sub.in to T1 drops, turning off the current, the current in T2 will continue for some additional delay time determined by its base-emitter time constant. The emitter current of T2 flows directly into the base of T1 of the following stage, turning it on very quickly. The net effect of this delay between T1 and T2 is to provide an overshoot on the turn-on transient, causing a reduction in the rise time and delay of the following stage. A similar effect occurs during the turn-off of the following stage. The signal swing is on the order of about 100 mV. The delay is on the order of about about 100 ps., which is approximately five times faster than the delay of a differential current switch logic gate fabricated with the same devices. The up and down levels are both clamped, as shown by the input signal at the base of T1. Therefore, by adjusting the control voltage V.sub.gen very large changes in the oscillator current can be achieved. In this manner the power in the VCO 10 can be varied without adversely affecting the operation of the oscillator.

Referring to FIG. 3, there is shown a graphical representation 24 of the output frequency of an eleven stage VCO according to the present invention as a function of the control voltage V.sub.gen. At a frequency of about 400 MHz. the VCO gain was about 4 GHz./volt. The gain of the VCO is expressed as

where .DELTA.f is the change in output frequency for a change in control voltage V.sub.gen of .DELTA.V, D is the average delay per stage, .DELTA.D is the change in delay, and N is the number of stages in the VCO. Variation of the gain is due primarily to variation in the stage delay. The main source of delay variation is variation in the control voltage V.sub.gen relative to the base-emitter voltage V.sub.be of T2. The nominal value of V.sub.gen is V.sub.be1 (off)-V.sub.be2 (on).

FIG. 4 shows an alternative arrangement of the control voltage generator 18 of FIG. 1, wherein the VCO gain can be adjusted. Rather than applying the same control voltage V.sub.gen to all of the inverter stages 12 as in FIG. 1, the control signal is divided into two components by means of generators GEN1 and GEN2. Generator GEN1 supplies a fixed bias voltage V.sub.gen1 to selected inverter stages, for example, stages 1-9, while generator GEN2 supplies a control voltage signal V.sub.gen2 to the remaining stages 10 and 11. Signal V.sub.gen2 is a combination of a fixed bias and an external control signal V.sub.ext. In this example, the VCO gain is 2/11 of the gain of the VCO shown in FIG. 1. Other VCO gains may be selected in a similar manner.

The VCO of the present invention may be employed, for example, in a PLL circuit such as the one shown in FIG. 4. A typical PLL includes a phase detector 26, a low pass loop filter 28 and a VCO 10. In clock extraction applications f.sub.IN is the incoming data stream and f.sub.OUT is the clock signal recovered or extracted from the data stream. The operation of PLLs is well known in the art and need not be described in detail. As the PLL input frequency f.sub.in is increased, a higher gain is required in order to achieve acceptable performance and noise margins. Prior systems could achieve the required frequencies only with VCOs including discrete components such as varactor diodes or surface acoustic wave devices. Even then, the VCO gains were unacceptably low for certain applications. Further, such components are relatively expensive and cannot be integrated on a chip with the other VCO and PLL components. Although the present VCO is illustrated in a PLL application, it may be employed in any application requiring such an oscillator.

The present invention thus provides a high frequency, high gain VCO having a selectable gain and frequency, wherein the VCO is integratable on a single integrated circuit chip.

While the invention has been shown and described with reference to particular embodiments thereof, it will be understood by those skilled in the art having the benefit of the foregoing detailed description that various changes in form and details may be made without departing from the spirit and scope of the invention as set forth in claims.