Apparatus for Processing Image Signal

The present invention relates to an apparatus for processing an image signal having functions of halftone image reproduction in binary.

Recently, facsimile systems have become frequently used in daily business. There arises a demand for halftone reproduction of pictorial images in addition to back-and-white binary reproduction of documents or the like. However, halftone reproduction often has many restrictions from the viewpoints of recording apparatuses and transmission systems. For example, an apparatus for recording an image on a silver chloride film used in conventional photography or a heat-sensitive printing apparatus has good recording characteristics for halftone recording. However, an electrostatic copying machine or an ink jet printing apparatus has good characteristics for binary recording. On the other hand, regarding transmission systems, digital data transmission is taking over from analog data transmission. In this field, data compression schemes are used to perform high-speed data transmission. Under these conditions, a pseudo halftone display system having a binary recording apparatus is proposed, which is suitable for digital data transmission, thereby providing an optimum fascimile system.

An electronic halftone-dot generating method for a printed image in a newspaper or magazine and a dither method for digitizing or quantizing an image signal in accordance with a threshold matrix table are typical examples of a pseudo halftone display system. However, these conventional methods have poor resolution of a two-valued (binary) image such as a character or line. Therefore, the halftone portion or binary image portion cannot help but be sacrificed.

For example, according to the dither method, in a threshold window consisting of a threshold pattern of a plurality of different threshold levels, a multilevel input image signal is compared with the threshold levels in units of picture elements. When a given picture element level of the original image data exceeds the corresponding threshold, the picture element is set to "black". Otherwise, the picture element is set to "white". In this manner, each picture element is converted to binary data. When a 4.times.4 matrix window is used, 16 threshold levels can be set. Therefore, halftone display having 17 levels can be performed for the original image data. In this manner, according to the conventional dither method, black elements appear in each threshold window in a number corresponding to the original image data levels, so as to represent an average halftone mode. When the window size is small, the displayed image has good resolution. In this case, however, the number of halftone levels is decreased. On the other hand, if the window size is large, the number of halftone levels is increased. However, in this case, resolution is degraded. In addition to this disadvantage, the quality of a reproduced image of a binary original image portion is degraded in accordance with the conventional dither method, as compared with general binary processing.

Some of inventors of this application previously invented an apparatus and a method for converting halftone image signals into binary signals. The method is now patent pending in United States and other countries (U.S. patent Ser. No. 501,873, now U.S. Pat. No. 4,538,184; British patent publication No. 2,129,652, etc.) The method comprises defining a successively shifted scanning window with respect to the signal level of each picture element from which said video signal has been derived, totalizing the quantum numbers of the picture elements in the scanning window corresponding to the original screen dot, and reconstructing black picture elements corresponding to the total value of the quantum numbers faithfully to the area of the original dot. This method realizes binary data reproduction with no moire pattern, but it is not sufficient to obtain both of high resolution and multiple halftone levels.

It is, therefore, an object of the present invention to provide an apparatus for processing an image signal so as to provide a displayed/recorded image of good image quality for both a binary image and a halftone image.

It is another object of the present invention to provide an apparatus for processing an image signal to obtain pseudo halftone reproduction compatible with both of high resolution and multiple halftone levels.

According to the present invention, there is provided an apparatus for processing an image signal comprising,

first and second image signal memory means for storing image signal levels of picture elements which are obtained by scanning an original image in a divided manner;

means for calculating a sum S of error correction data E.sub.a and a sum S.sub.m of the image signal levels of all picture elements within a first scanning window which a has a size corresponding to M picture elements and which scans said first image signal memory means, and obtaining N and A from equation

where C is a predetermined image signal level, N is an integer falling in a range O.ltoreq.N.ltoreq.M, and A is an image signal level falling in a range O.ltoreq.A.ltoreq.C;

preference circuit means for numbering all picture elements to one of which neighboured correction data E.sub.b is added, within a second scanning window which has a size corresponding to M picture elements so as to scan said second image signal memory means, in accordance with one of ascending and descending orders of the image signal levels;

rearrangement circuit means for assigning C as an image signal level to N picture elements of M picture elements in said first image signal memory means ordered by said preference circuit, A as an image signal level to a next picture element, and O as an image signal level to remaining picture elements,

means for comparing an image signal level of rearranged picture element with a predetermined quantizing level V for O.ltoreq.V<C, and for assigning C to the image signal level when the image signal level is greater than the quantizing level V as a binary image signal and assigning O to the image signal level when the image signal level is smaller than the quantizing level V as another binary image signal, and oprating the error correction data E.sub.a from the difference of the image signal level and the assigned binary image signal,

third memory means for storing preference correction data,

a first calculating means for calculating the neiboured correction data E.sub.b by the preference correction data neiboured to the refered picture element corresponding to that in said first or second scanning window and,

a second calculating means for calculating renewed preference correction data which are to be stored into address corresponding to the refered picture element with the preference correction data read out from said third memory, image signal level of the refered picture element in said second image signal memory, and the binary image signal level.

The present invention will now be described in further detail with reference to the accompanying drawings, in which:

FIG. 1 is a block diagram of an image signal processing apparatus of the first embodiment of the present invention;

FIG. 2 is a block diagram of the preference circuit of FIG. 1;

FIG. 3 is a flow chart for explaining processing steps of the embodiment of FIG. 1;

FIG. 4 is a block diagram of an image signal processing apparatus of the second embodiment of the present invention;

FIG. 5 is a flow chart for explaining processing steps of the embodiment of FIG. 4;

FIG. 6 is a block diagram of an image signal processing apparatus of the third embodiment of the present invention;

FIG. 7 is a flow chart for explaining processing steps of the embodiment of FIG. 6;

FIG. 8 is a block diagram of an image signal processing apparatus of the fourth embodiment of the present invention;

FIG. 9 is a flow chart for explaining processing steps of the embodiment of FIG. 8;

FIG. 10 is a block diagram of an image signal processing apparatus of the fifth embodiment of the present invention;

FIG. 11 is a flow chart for explaining processing steps of the embodiment of FIG. 10;

FIG. 12 is a block diagram of an image signal processing apparatus of the sixth embodiment of the present invention;

FIG. 13 is a flow chart for explaining processing steps of the embodiment of FIG. 12; and

FIG. 14 is a block diagram of an image signal processing apparatus of the seventh embodiment of the present invention.

Through this specification and drawings, size M of the scanning windows is fixed to 4. The picture element addresses in the first scanning window are denoted with symbols R.sub.00, R.sub.01, R.sub.10 and R.sub.11. Similarly, the picture element addresses in the second scanning window are denoted with symbols O.sub.00, O.sub.01, O.sub.10 and O.sub.11. In the third memory, the refered address is denoted with symbol E.sub.c5, and the neighboured addresses are E.sub.c1, E.sub.c2, E.sub.c3 and E.sub.c4. The picture element addresses R.sub.00, O.sub.00 and the address E.sub.c5 are corresponded to same picture element in referring. Defined R.sub.00, R.sub.01, R.sub.10 and R.sub.11 as a scanning window W.sub.r, O.sub.00, O.sub.01, O.sub.10 and O.sub.11 as a scanning window W.sub.0, and E.sub.c1, E.sub.c2, E.sub.c3, E.sub.c4 and E.sub.c5 as a scanning window W.sub.e respectively. The scanning windows W.sub.r, W.sub. o and W.sub.e are shifted right in synchronism with main scan of scanner 1.

FIG. 1 illustrates the first embodiment of the present invention. In FIG. 1, numeral 1 denotes a scanner which scans original and outputs image signal level as digital signal. The scanner 1 is almost same as those disclosed in U.S. patent application Ser. No. 501,873 or British patent publication No. 2,129,652. The output signal from the scanner is supplied to a rearrangement memory 2 and a preference memory 4. The rearrangement memory 2 stores the output signal from the scanner 1 and output signal from a data rearrangement circuit 6 and outputs image signal levels of four picture elements R.sub.00, R.sub.01, R.sub.10 and R.sub.11 in the scanning window W.sub.r. A rearrangement volue operator 3 calculates a sum S of an error correction data E.sub.a from a comparator 7 and a sum S.sub.m of the image signal levels of four picture elements R.sub.00, R.sub.01, R.sub.10 and R.sub.11 from the rearrangement memory 2, and obtaining N and A from following equation S=C.times.N+A, where C is a predetermined image signal level, N is an integer falling in a range O.ltoreq.N.ltoreq.M, and A is an image signal level falling in a range O.ltoreq.A.ltoreq.C. The preference memory 4 receives image signal of original from the scanner and outputs image signal levels of four picture elements O.sub.00, O.sub.01, O.sub.10 and O.sub.11 in the scanning window W.sub.o. The image signal levels from the preference memory 4 are supplied to a preference circuit 5 to which neighboured correction data E.sub.b is supplied from a multiplier 83. The preference circuit determines preference order of the four picture elements by comparing image signal levels of the four picture elements, to O.sub.00 picture element of which neighboured correction data E.sub.b is added from a multiplier 83, in accordance with one of ascending and descending orders of the image signal levels. A data rearrangement circuit 6 receives data N and A from the preference value operator 3 and assign C as an image signal level to N picture elements of four picture elements in the scanning window W.sub.r in order determined by the preference circuit 5, A as an image signal level to a next picture element, and O as an image signal level to remaining picture element. Numeral 7 denotes a comparator which compares image signal of rearranged picture element R.sub.00 from the rearrangement memory 16 with a predetermined quantitizing level V, where O.ltoreq.V<C, and outputs C as image signal level to be recorded or displayed when the image signal R.sub.00 is greater than the level V, and outputs O as image signal level to be recorded or displayed when the image signal R.sub.00 is smaller than the level V. At the same time, the comparator 7 outputs error correction data E.sub.a which is the difference between the image signal R.sub.00 and the output signal of the comparator 7. Numberal 8 designates a preference correction means which receives image signal level of the picture element O.sub.00 from the preference memory 4, output image signal level of the comparator 7, and preference correction data E.sub.c from a correction data memory 9 and operates neighboured correction data E.sub.b and preference correction data E.sub.c to be renewed. The renewed correction data E.sub.c are stored into address E.sub.c5 of the correction data memory 9. The output signal from the comparator 7 is supplied to a recording or display apperatus 10 to record or display binary image. The apparatus 10 may be same as that disclosed in U.S. patent application Ser. No. 501,873.

The preference correction means 8 comprises a subtracter 81 for subtracting output signal level of the comparator 7 from the image signal level of the picture element O.sub.00 in the scanning window W.sub.o, an average operator 82 for calculating average E.sub.ca of four preference correction data E.sub.c1, E.sub.c2, E.sub.c3 and E.sub.c4 in the scanning window W.sub.e, a first multiplier 83 for multiplying a predetermined coefficient K.sub.a to the average E.sub.ca, a second multiplier 84 for multiplying a predetermined coefficient K.sub.b to the average E.sub.ca, and an adder 85 for adding the output of the multiplier 84 and the output of the subtracter 81.

In FIG. 1, the constructions and operations of the scanner 1, the rearrangement memory 2, the rearrangement value operator 3, the preference memory 4, the preference circuit 5, the data rearrangement circuit 6, the comparator 7 and the recording or display apparatus 10 are substantially same as those of U.S. patent application Ser. No. 501,873 or British patent publication No. 2,129,652.

FIG. 2 illustrates a block diagram which realizes the part including from the rearrangement memory 2 to the correction data memory 9 of FIG. 1 with a microcomputer. Image signal level of original obtained from the scanner 1 is supplied to an input terminal 11. Input port 12 is a gate circuit which supplies image signal level from the input terminal 11 to CPU13 (central processing unit) in accordance with a selective signal given from the CPU13 through a signal line 14. ROM 15 (read only memory) stores a program for controlling the CPU13. In accordance with the program, the CPU takes in necessary data from the input port 12, performs predetermined operations by giving and taking data between RAM16 (random access memory), and supplies output data to output port 17. The output port 17 is a latch circuit which stores data temporarily in accordance with a control signal given from the CPU 13 through a signal line 18. The data stored in the output port 17 are took out to an output terminal 19 as a binary image signal to be recorded or displayed.

The CPU13, ROM15 and RAM16 can be constructed by wellknown microcomputer.

FIG. 3 illustrates a flow chart corresponding to the program stored in the ROM15.

When the program starts, the contents of the rearrangement memory 2, the preference memory 4 and the correction data memory 9 and error correction data E.sub.a are cleared (STEP 1). In STEP 2, the image signal of the original is written into the address of picture element R.sub.11 of the rearrangement memory 2 and the address of picture element O.sub.11 of the preference memory 4. In STEP 3, the rearrangement value operator 3 calculates a sum S of the error correction data E.sub.a and a sum S.sub.m of the image signal levels of picture elements R.sub.00, R.sub.01, R.sub.10 and R.sub.11 within the scanning window W.sub.r of the rearrangement memory 2, and operates integer N and remainder A from equation S=C.times.N+A. In STEP 4, the average operator 82 calculates an average E.sub.ca of four preference correction data E.sub.c1, E.sub.c2, E.sub.c3, and E.sub.c4 within the scanning window W.sub.e of the correction data memory 9, and the average E.sub.ca is multiplied by the predetermined coefficient K.sub.a in the multiplier 83 to obtain neighboured correction data E.sub.b (=K.sub.a .times.E.sub.ca). The coefficient K.sub.a is, for example, 1/2.sup.n, where n is an integer. In STEP 5, the preference circuit 5 adds the neighboured correction data E.sub.b to the image signal level of the picture element O.sub.00 within the scanning window W.sub.o of the preference memory 4, and determines rearranging order of four picture elements O.sub.00, O.sub.01, O.sub.10, and O.sub.11 in descending order by comparing the image signal levels thereof. In step 6, the data rearrangement circuit 6 rearranges N predetermined image signal level C, the remainder A and O which are obtained in STEP 3, as image signals of four picture elements R.sub.00, R.sub.01, R.sub.10 and R.sub.11 within the scanning window W.sub.r of the rearrangement memory 2 according to the order obtained in STEP 5. In STEP 7, the comparator 7 converts the image signal of the rearranged picture element R.sub.00 from the rearrangement memory 2 into binary image signal with the quantitizing level V, and the difference between the image signal of the picture element R.sub.00 and the converted binary signal is supplied to the rearrangement volue operator 3 as a renewed error correction data E.sub.a for next STEP 3. In STEP 8, the preference correction means 8 calculates the product of the coefficient K.sub.b and the average E.sub.ca obtained in STEP 4 by the multiplier 84, and adds the product to the difference between image signal level of the picture element O.sub.00 in the scanning window W.sub.o and the binary image signal level from the comparator 7, which is calculated by the subtracter 81, in the adder 85 to produce renewed preference correction data E.sub.c which is to be stored in the picture element E.sub.c5 within the scanning window W.sub.e of the correction data memory 9. In STEP 9, the binary image signal from the comparator 7 is supplied to the display apparatus 10. In STEP 10, it is judged whether the above processes are ended relating to all of image signals of original in both of main and sub scans. If the processes are not ended, the scanning windows W.sub.o, W.sub.r and W.sub.e are moved and the STEP 2 to STEP 10 are repeated. In this case, the error correction data E.sub.a is cleared in every end of main scans in STEP 11.

When the coefficient K.sub.a is 1/2.sup.n and K.sub.b is 114 1/2.sup.m, where n and m are positive integers, the operations in the microcomputer become easy.

The microcompter may be replaciable with logic circuits and memories. In this case, hardware thereof can be simplified by using the above valued coefficients K.sub.a and K.sub.b.

FIG. 4 illustrates another embodiment of the present invention. In Fig. a signal adder 20 is provided between the canner 1 and the preference memory 4. The signal adder 20 adds a periodical signal in synchronism with the picture elements of the original image and having different signal level thereof to the original image signal forn the scanner 1. The signal adder 20 is substantially same as that shown in British patent publication No. 2,129,652. Other portions of FIG. 4 are same as those of FIG. 1. In this embodiment, the periodical signal is supperposed to the original image signal as STEP 2 shown in FIG. 5. The remaining steps are same as those in FIG. 3. The embodiment improves visual characteristics of the reproduced image with diverging error data in the additive signal. When a random signal is superposed as the additive signal, the improvement of moire signal or reproduction of image having special effect are obtained.

FIG. 6 illustrates a third embodiment of the present invention. A compensator 21 is provided between the comparator 7 and the recording or display apparatus 10. The compensator 21 selects the binary image signal from the comparator 7 in accordance with the image signal level of the picture element O.sub.00 within the scanning window W.sub.o of the preference memory 4. Other portions of FIG. 6 are same as those of FIG. 1.

In the operation shown in FIG. 7, STEP 9 is newly added after renewing E.sub.c in STEP 8, which corresponding to STEP 8 of FIG. 3. In STEP 9 of FIG. 7, the compensator 21 compares the image signal level of the picture element O.sub.00 in the scanning window W.sub.o of the preference memory 4 with predetermined low level value T1 and high level volue Th, and selects onput signal level as below.

(1) Output O when O.sub.00 .ltoreq.T1;

(2) Output C when O.sub.00 .gtoreq.Th;

(3) Output the binary image signal from the comparator 7 when T1<O.sub.00 <Th;

where O.sub.00 is the image signal level of the picture element O.sub.00, and C is a predetermined recording level, which usually corresponds to maximum recording level. The embodiment suppresses noises contained in high and low level of the binary image signal.

FIG. 8 illustrates 9 fourth embodiment of the present invention. In FIG. 8, the constructions and/or connections of the rearrangement memory 22, the rearrangement volue operator 23 and the data rearrangement circuit 26 are different from those of FIG. 1. Other portions are same as those of FIG. 1. The rearrangement memory 22 receives rearrangement image signal level from the data rearrangement circuit 26, and stores upper U bit of the rearrangement image signal level in three picture element R.sub.00, R.sub.01, and R.sub.10 within the scanning window W.sub.r, and supplies the stored upper U bit signal to the rearrangement value operator 23. The rearrangement value operator 23 calculates a sum S of a volue Su which is obtained by inserting O to each of lower L bit of a sum of the three image signal levels of the picture elements R.sub.00, R.sub.01, and R.sub.10 from the rearrangement memory 22, error correction data E.sub.a from the comparator 7, image signal level F.sub.o of the original from the scanner 1, and rearrangement correction data S, from the data rearrangement circuit 26, and obtaining N and A from S=C.times.N+A similerly to the case of FIG. 1. The data rearrangement circuit 26 comprises means for determining arrangement of C for N picture elements, A and O for remaining picture elements in accordance with the preference order designated by the preference circuit 5, means for storing upper U bits data of the image signal levels for rearrangement into three picture elements R.sub.01, R.sub.10, and R.sub.11 within the scanning window W.sub.r of the rearrangement memory 22, means for obtaining the renewed rearrangement correction data S.sub.1 by summing lower L bits data of the image signal levels for rearrangement and means for supplying all bits data of the image signal levels corresponding to the picture element R.sub.00 within the scanning window W.sub.r of the rearrangement memory 22 to the comparator 7.

FIG. 9 illustrates a flow chart for explaining operations of the block diagram of FIG. 8.

When the program starts, the contents of the rearrangement memory 22, the preference memory 4 and the correction data memory 9, and error correction data E.sub.a and rearrangement correction data S.sub.1 are cleared (STEP 1). In STEP 2, the image signal level F.sub.o of the original is written into the rearrangement value operator 23 and the address of picture element O.sub.11 within the scanning window W.sub.o of the preference memory 4. In STEP 3, the rearrangement value operator 23 calculates the sum S (=Su+Ea+S.sub.1 +F.sub.o) and operates integer N and remainder A from equation S=C.times.N+A. STEP 4 and STEP 5 are similar to those of FIG. 3. In STEP 6, the upper U bits data of the image signal levels for rearrangement C, A and O into three picture elements R.sub.01, R.sub.10 and R.sub.11 within the scanning window W.sub.r of the rearrangement memory 22 in accordance with the preference order obtained in STEP 5, the sum of lower L bits data of the image signal levels in the three picture elements R.sub.01, R.sub.10, R.sub.11, within the scanning window W.sub.r is supplied to the rearrangement value operator 23 as renewed rearrangement correction data S.sub.1 and all bits data of the image signal levels of the rearranged picture element R.sub.00 are supplied to the comparator 7. These are performed by the data rearrangement circuit 26. STEP 7 to STEP 11 are similar to those of FIG. 3. The embodiment saves the amount of buffer memory used as the rearrangement memory 22 from U+L bits to U bits.

FIG. 10 illustrates a fifth embodiment of the present invention. The correction data memory 29 is smaller in bit number (U bit) than that (U+L bit) of the correction data memory 9 of FIG. 1. To compensate this, a lower bit gate 86, an upper bit gate 87 and an adder 88 are provided in the preference correction means 8. Other portions are same as those of FIG. 1.

FIG. 11 illustrates a flow chart for explaining operations of the block diagram of FIG. 10.

When the program starts, the contents of the rearrangement memory 2, the preference memory 4 and the correction data memory 9, and error correction data E.sub.a, preference correction data E.sub.ca from the adder 88, upper bit preference correction data E.sub.cu from the gate 87, and lower bit preference correction data E.sub.CL are cleared (STEP 1). STEP 2 and STEP 3 are same as those of FIG. 3. In STEP 4, the average operator 82 calculates average of four preference correction data which are formed with four upper bit preference correction data E.sub.CU having U bits from addresses E.sub.c1, E.sub.c2, E.sub.c3 and E.sub.c4 within the scanning window W.sub.e of the correction data memory and O inserted to lower L bit thereof, and the adder 88 adds the average from the average operator 82 and the lower bit preference correction data E.sub.CL selected by the gate 86 and delayed in time corresponding to one picture element. The thus obtained sum E.sub.ca is multiplied by a coefficient K.sub.a with the multiplier 83 to obtain neighboured correction data E.sub.b (=Ka.times.E.sub.ca). Step 5, 6 and 7 are same as those of FIG. 3. In STEP 8, the multiplier 84 calculates the product of the coefficient K.sub.b and the average E.sub.ca obtained in STEP 4 and adds the product to the difference between image signal level of the picture element O.sub.00 in the scanning window W.sub.o and the binary image signal level from the comparator 7, which is calculated by the subtracter 81, in the adder 85 to produce renewed upper bit preference correction data E.sub.cu and lower bit preference correction data E.sub.CL. The renewed upper bit preference correction data E.sub.CU is stored into address corresponding to the picture element E.sub.c5 in the scanning window W.sub.e through the gate 87. STEP 9, 10 and 11 are same as those of FIG. 3. In this case, the error correction data E.sub.a, the preference correction data E.sub.ca, the upper bit preference correction data E.sub.CU and lower bit preference correction data E.sub.CL are cleared in every end of main scans in 11.

In this embodiment, the preference correction data E.sub.ca may be replaced with average of the upper bit preference correction data E.sub.CU as upper bits and average of the lower bit preference correction data E.sub.CL as lower bits.

The embodiment has advantages of saving the amount of buffer memory used as the correction data memory 29 from U+L bits to U bits.

FIG. 12 illustrates a sixth embodiment of the present invention. The embodiment is that combined with the embodiments of FIG. 8 and FIG. 10, and each of the components is same as that of FIG. 8 or FIG. 10 with same reference numeral. The operation is performed as illustrated in FIG. 13, which is the combination of FIG. 9 and FIG. 11. Therefore explanation is not repeated.

FIG. 14 illustrates a seventh embodiment of the present invention. An error data memory 31 and an error matrix 32 are same as the correction data memory 29 and the scanning window W.sub.e of FIG. 10. Numeral 33 denotes memory location in which an error E.sub.xy at co-ordinates xy of the original image is stored. An original image data I.sub.xy from the co-ordinates xy of the original image is supplied to input terminal 35. An adder 36 calculates a sum I'xy of the original image data Ixy and a mean error E.sub.a. A comparator 39 compares the signal I'xy with a predetermined value R/2 from a terminal 38 to obtain binary data Pxy=R when I'xy>R/2, and Pxy=O when I'xy.ltoreq.R/2. The output Pxy from the comparator 39 is supplied to an output terminal 37. A subtracter 40 calculates the error Exy by subtracting the binary data Pxy from the signal I'xy. A weighted mean calculating means 41 calculates a weighted mean of error data stored in the error matrix 32 of the error data memory 31. Numeral 42 denotes a delay circuit.

The error data memory 31, the error matrix 32 and the weighted mean calculating means 41 correspond to the correction data memory 2P, the scanning window W.sub.e and the average operator 82 of FIG. 10 respectively.

The weighted mean calculating means 41 calculates a weighted mean E.sub.w of the data within the error matrix 32 by the following equation: ##EQU1## where, i and j are co-ordinates in the error matrix 32, and A.sub.ij is a matrix coefficient which gives weights of distances from the co-ordinates xy of the referred picture element to the error. For example, A.sub.ij is represented by: ##EQU2## where * is a location of the refered picture element. The mean error E.sub.a consists of upper bits forned with the weighted mean E.sub.w and lower bits formed with a lower L bits data E.sub.x-1, y (L) of the error E.sub.x-1,y which is obtained by delaying the error Exy from the subtractor 40 in the delay circuit 42. The adder 36 adds the mean error Ea and the original image data Ixy to obtain output I'xy (=Ixy+Ea). The comparator 39 compares the output I'xy of the adder 36 and the predetermined value R/2, and supplies the binary signal Pxy to the output terminal 37. The subtracter 40 calculates difference Exy of the output I'xy of the adder 36 and the binary signal Pxy, and the upper U bit Exy(U) of the difference Exy is supplied to the error data memory 31 as a renewed error for the coordinate xy of the original image. The renewed error data Exy(U) is stored in the memory location 33 of the error data memory 31. On the other hand, the lower L bit Exy(L) of the difference Exy is supplied to the delay circuit 42. The delay circuit 42 replaces the data E.sub.x-1,y (L) before one picture element with the data Exy(L) and holds the same.

In calculating the mean error Ea, it is possible to add the output of the delay circuit 42 to a weighted mean which is obtained by calculating the same using the data consisted of upper U bit error data in the error matrix 32 and 0 added to lower L bits thereof. The method improves precision of calculating the weighted mean. Furthermore, the delay circuit 42 can be omitted by adjusting the subtractor 40 in holding previously subtracted results until the adder 36 receives the mean error Ea.

In experimental results, no deterioration of the reproduced image is observed by deleting lower 5 bit data from 8 bit data of the output Exy of the subtractor 40. On the contrally, a texture of a stripe pattern which is inherent to conventional mean error minimizing method is removed by delating the lower bit data. According to the embodiment of FIG. 14, the memory capacitance of the error data memory 31 can be reduced L bit per one picture element without deteriorating halftone reproducing characteristics.