FET Voltage Reference Circuit With Threshold Voltage Compensation

This invention relates to a voltage converting circuit which outputs an intermediate level of power supply voltage and particularly to a voltage converting circuit which is suitable for use in a MIS type integrated circuit.

It is often required in a MIS type integrated circuit to use a constant voltage having an intermediate level with respect to the power supply voltage supplied from an external circuit. For instance, an intermediate level of, for example, 2.5 V is steadily applied to a common capacitor electrode incorporated into memory cells in a MIS type dynamic random access memory operative under a power supply voltage of 5 V.

The intermediate level is obtained easily using a resistance dividing circuit as shown on FIG. 1. In this figure, resistors R.sub.1, R.sub.2 divide the power supply voltage V.sub.cc in order to obtain an intermediate voltage V.sub.cc ' to be provided to a load circuit L. For a sufficiently low load current, when R.sub.1 =R.sub.2, then V.sub.cc '=V.sub.cc /2. However, when a load circuit L consumes a current that is sufficiently high, such a relation is not maintained. Moreover, in this example, the resistors R.sub.1, R.sub.2 are connected in series between the power source V.sub.cc of +5 V and the power source V.sub.ss of 0 V, a current always flows from V.sub.cc to V.sub.ss, and thereby a large amount of power is consumed. This is one disadvantage of this circuit. Such power consumption can be reduced by making large the resistors R.sub.1, R.sub.2. However, if a resistance value is large, the above change in the voltage V.sub.cc ' at node N1 due to a load current becomes large.

The circuit shown in FIG. 2 is effective for reducing power consumption and fluctuation of the load voltage V.sub.cc ' due to a change of the load current. In this circuit, a divided voltage of power source V.sub.cc obtained through the resistors R.sub.1, R.sub.2 is given to the gate of a MIS transistor Q.sub.1 and an output of said transistor Q.sub.1 is applied to the load circuit L. Q.sub.1 constitutes an output transistor of low output impedance. Therefore, a load current flows through the drain and source of transistor Q.sub.1 but does not flow into the voltage dividing circuit R.sub.1, R.sub.2. There is no change of load voltage V.sub.cc ' and, since the dividing circuit only gives a voltage to the gate of the MIS transistor Q.sub.1, the circuit is allowed to have a high resistance value, thus resulting in less power consumption. Because of the relation V.sub.N -V.sub.th =V.sub.cc ' between the voltage V.sub.N of node N.sub.1 and load voltage V.sub.cc ' , when V.sub.cc '=V.sub.cc /2 is required, V.sub.N is selected to have a value satisfying the relation, V.sub.N =V.sub.th +V.sub.cc /2. V.sub.th indicates the gate threshold voltage of the MIS transistor Q.sub.1.

However, this circuit has a problem in that a threshold voltage V.sub.th of the transistor Q.sub.1 directly affects a load voltage V.sub.cc ' and V.sub.th changes in accordance with the integration circuit manufacturing process, whereby the load voltage V.sub.cc ' fluctuates for each product.

Namely, it is well known that a resistance ratio of two resistors in an integrated circuit has only a small error, although there are changes of V.sub.th depending on the manufacturing process. For example, it is easy to ensure that an error of resistance value ratio is as small as 1% or less. Therefore, a voltage V.sub.N of node N.sub.1 can be set accurately. Meanwhile, the gate threshold voltage of a MIS transistor is easily affected by a process fluctuation, and an error as small as 0.2 V can easily be generated. This error means, for example, that an error of about 10% easily occurs in the circuit for generating an output voltage V.sub.cc ' of 2.5 V.

An object of this invention is to provide a voltage converting circuit which outputs an intermediate level of power source voltage.

Another object of this invention is to provide a voltage converting circuit which consumes less power.

Yet another object of this invention is to provide a voltage converting circuit comprising an output MIS transistor which gives a small output impedance.

A further object of this invention is to prevent an output voltage from being affected by a variation of the threshold voltage V.sub.th caused by a fluctuation in the manufacturing process for output MIS transistors of voltage converting circuits.

In accordance with the present invention, a voltage converting circuit is provided for receiving a power source voltage and providing a constant voltage having the level of a predetermined porportional division of said power source voltage, comprising:

an output MIS transistor for outputting said constant voltage, with the MIS transistor having a gate which receives a gate control voltage; and

a gate control means for providing said gate of said MIS transistor with said gate control voltage, comprising an impedance means connected to receive said power source voltage for providing said predetermined proportional division, and compensating means having at least one compensation MIS transistor connected to said impedance means, for compensating the gate control voltage for the gate threshold voltage of said output MIS transistor to provide said constant voltage corresponding to said predetermined proportional division irrespective of variation of said gate threshold voltage.

The above and other objects and advantages of the present invention will be more apparent from the following description of the preferred embodiments with reference to the accompanying drawings, wherein:

FIG. 1 is a circuit diagram of a voltage converting circuit in the prior art;

FIG. 2 is a schematic diagram of the other voltage converting circuit in the prior art;

FIG. 3 is a schematic diagram of a voltage converting circuit in an embodiment of this invention;

FIG. 4 is a schematic diagram of a voltage converting circuit in another embodiment of this invention;

FIG. 5 is a schematic diagram of a voltage converting circuit in yet another embodiment of this invention;

FIG. 6 is a schematic diagram of a voltage converting circuit in a further embodiment of this invention;

FIGS. 7(a) and (b) are respective the graphs which show the change in time of the converted voltage output after the power source is turned ON in the circuits of the prior art and of the embodiments of this invention; and

FIG. 8 is a schematic diagram of a voltage converting circuit in still a further embodiment of this invention.

FIG. 3 shows an embodiment of this invention. From FIG. 1 to FIG. 8, the same portions as those in FIG. 1 and FIG. 2 are given the same symbols for convenience of description. In comparison with the circuit of the prior art as shown in FIG. 2, the circuit of FIG. 3 is different therefrom in such a point that the MIS transistors Q.sub.2, Q.sub.3 are inserted into the voltage dividing circuit (gate voltage control circuit). In the circuit of FIG. 3, a pair of N channel MIS transistors Q.sub.2, Q.sub.3 are connected in series to the resistor elements R.sub.1 and R.sub.2 which give a voltage dividing ratio. A divided output from the series circuit of resistor elements R.sub.1, R.sub.2 and MIS transistors Q.sub.2, Q.sub.3 is given at the node N.sub.1 to the gate of the output N channel MIS transistor Q.sub.1. The transistors Q.sub.2, Q.sub.3 are provided for compensating its gate threshold voltage, and the number of transistors depends on the voltage dividing ratio. The circuit of FIG. 3 is provided for outputting a voltage of V.sub.cc /2 and two transistors Q.sub.2 and Q.sub.3 are required in this case. Said circuit of FIG. 3 operates normally when a voltage of the power source voltage supply line is higher than the normal voltage V.sub.cc /2 to be output. In this case, the voltage of node N.sub.2 is V.sub.th, the voltage of node N.sub.3 is 2.times.V.sub.th. When R.sub.1 =R.sub.2, the voltage of node N.sub.1 is indicated by (V.sub.cc -2V.sub.th)/2+2V.sub.th =V.sub.cc /2+V.sub.th. Since the transistors Q.sub.1, Q.sub.3 are formed by the same process on a semiconductor substrate, these transistors can be considered to have the same threshold voltage. When the node N.sub.1 has the above voltage, a load voltage V.sub.cc ' is V.sub.cc /2, which is lower than the above voltage by V.sub.th. Thereby, a voltage V.sub.cc ' irrespective of the threshold voltage of a transistor can be supplied to the load L.

FIG. 4 is a second embodiment of this invention. The circuit of FIG. 3 is based on the assumption that the load L always receives an input current through the transistor Q.sub.1 (a current flows through V.sub.cc -Q.sub.1 -L-V.sub.ss) and that a current does not flow out from the load L toward the source of the transistor Q.sub.1. However the circuit of FIG. 4 can operate properly even if current flows out from the load L. In this circuit, the circuit portion formed by R.sub.1, R.sub.2, Q.sub.3, Q.sub.2 is the same as that in FIG. 3, a load voltage V.sub.cc ' is held thereby to V.sub.cc /2, irrespective of V.sub.th. The MIS transistors Q.sub.4, Q.sub.5, Q.sub.6 resistors R.sub.3, R.sub.4 form a circuit which holds the load voltage V.sub.cc ' to V.sub.cc /2 in such a case where a current flows into the power supply V.sub.ss through the transistor Q.sub.4 from the load L. Here, Q.sub.4 , Q.sub.5, Q.sub.6 are P channel transistors. Namely, the voltage of node N.sub.6 is V.sub.cc -V.sub.thp, the voltage of node N.sub.5 is V.sub.cc -2V.sub.thp and the voltage of node N.sub.4 is (V.sub.cc -2V.sub.thp)/2=V.sub.cc /2-V.sub.thp when R.sub.3 =R.sub.4. V.sub.thp is the gate threshold voltage of the p channel transistor Q.sub.4. Since a voltage of node N.sub.4 is lower than V.sub.cc ' by V.sub.th of Q.sub.4, V.sub.cc ' becomes V.sub.cc /2. In the circuit of FIG. 4, a load voltage can be set constant irrespective of a load voltage V.sub.th, in either case where a current flows into the load or a current flows out from the load.

It is desirable in actual design of the circuit of FIG. 4 to assure the avoidance of a steady current in the series circuit of transistors Q.sub.1 and Q.sub.4 by providing a small difference between the voltage dividing ratio of the resistors R.sub.1, R.sub.2 and the voltage dividing ratio of the resistors R.sub.3, R.sub.4. For example, the voltage of node N.sub.1 should advantageously be V.sub.cc /2+V.sub.th minus several 10 mV and the voltage of node N.sub.4 should be V.sub.cc /2-V.sub.thp plus several 10 mV. Thereby, when the output voltage V.sub.cc ' is V.sub.cc /2, both output transistors Q.sub.1, Q.sub.4 are set to the cut-off condition. IF the output voltage V.sub.cc ' rises or drops, the output transistors Q.sub.1 or Q.sub.4 become selectively ON and suppress the change of voltage described above.

FIG. 5 and FIG. 6 show the third and fourth embodiments of this invention. The former holds a load voltage V.sub.cc ' to V.sub.cc /3, while the latter to 2V.sub.cc /3. Namely, since the voltage of node N.sub.7 is 3V.sub.th and the resistance values of resistors R.sub.1, R.sub.2 are selected in such a relation as R.sub.1 =2R.sub.2 in FIG. 5, the voltage of node N.sub.1 becomes equal to (V.sub.cc -3V.sub.th)/3+3V.sub.th =V.sub.cc /3+2V.sub.th, and the load voltage V.sub.cc ' is lower than this voltage level by 2V.sub.th due to the voltage drop across transistors Q.sub.8 and Q.sub.1 thus becoming equal to V.sub.cc /3. In FIG. 6, the voltage of node N.sub.7 is 3V.sub.th, the voltage of node N.sub.1 is 2(V.sub.cc -3V.sub.th)/3+3V.sub.th =2V.sub.cc /3+ V.sub.th when 2R.sub.1 =R.sub.2, and the load voltage V.sub.cc ' is lower than this voltage by V.sub.th, becoming equal to 2V.sub.cc /3.

In general, the load voltage of V.sub.cc '=mV.sub.cc /n can be obtained by using n transistors as the transistors Q.sub.2, Q.sub.3, . . . to be inserted in series with the resistance voltage dividing circuit, of the gate voltage control circuit and (n-m-1) transistors as the transistors Q.sub.8 . . . to be inserted into the gate circuit of the output transistor Q.sub.1, and by setting a resistance ratio R.sub.2 /(R.sub.1 +R.sub.2) to m/n. Thereby, a variety of load voltages V.sub.cc ' which are not affected by V.sub.th can be obtained. In the above, m and n are integers for which m<n.

When the resistance value is made large in order to reduce power consumption in the resistance voltage dividing circuit, the time constant becomes large and the rising edge of the load voltage becomes gentle as shown in FIG. 7(a). In case a transistor Q.sub.1 is used as in the case of FIG. 3, the load voltage V.sub.cc ' quickly rises as shown in FIG. 7(b) and, when the power supply becomes ON, operation can be started immediately.

In the circuit of FIG. 3, the resistor R.sub.2 may be shifted, for example, to the location between Q.sub.3 and V.sub.ss from the location indicated. The alternate location for the resistor R.sub.2 is indicated by the resistor R.sub.2 ', shown with the dotted line in the lower left corner of FIG. 3. In this case, the same result can also be obtained. Moreover, this method is superior in such a point that each transistor Q.sub.1, Q.sub.2, or Q.sub.3 receives a similar back gate bias effect on its own V.sub.th, since the source voltage of Q.sub.2, Q.sub.3 rises up to a value close to that of Q.sub.1 and, thereby, V.sub.th of Q.sub.2 and Q.sub.3 becomes equal to that of Q.sub.1.

FIG. 8 shows an embodiment where the resistors R.sub.1, R.sub.2 in FIG. 3 are replaced by depletion transistors T.sub.1, T.sub.n, T.sub.1 ' T.sub.n '. The same transistors and the same nodes are indicated by the same symbols. In general, a resistance of the polysilicon layer or diffusion layer used in a MIS dynamic memory is as small as several 10 ohms/square. If it is desired to obtain a resistance of several 100 k-ohm as required for the resistors R.sub.1, R.sub.2 by using these resistance layers, an area of several hundreds of thousand .mu..sup.2 becomes necessary. In order to avoid this, it is recommended to use one or a plurality of depletion transistors connected in series in place of resistors. Thereby, a current can be reduced using a small area.