Method and Apparatus for Controlling Multiple Motors

This invention generally relates to a method and apparatus for controlling step motor operation and, more particularly, to a method and apparatus for simultaneously controlling a multiplicity of step motors having individual operating characteristics.

Step motors, or stepper motors, are motors which move in discrete increments. For example, four phase control windings may be provided which can be separately activated in response to inputs from a control system. By addressing the windings in a proper sequence a controllable incremental stepped revolution of the motor shaft is obtained. Thus, step motors are very useful in a control system for positioning mechanical components with a requisite accuracy.

In some instances a number of step motors are used to position component parts of a mechanism. Simultaneous control of the motors typically involves a microprocessor for manipulating data. In some operations a relatively complex computer may be used for the motor control. In other systems, a microprocessor may be associated with each motor for stepping the motor. A central control computer requires complex wiring and a comparatively slow operation is obtained to accommodate the time for data transfer and manipulation with the individual motors. Individual microprocessor applications require relatively complex and expensive control circuits for each motor.

Recent control systems have used programmable array logic circuits (PAL), also known as programmable logic array circuits (PLA), to logically combine selected inputs to obtain outputs for further processing by microprocessor circuitry. For example, U.S. Pat. No. 4,481,569 teaches use of a PAL for bookkeeping signal condition functions ancillary to microprocessor circuitry for controlling robotic servo motors. U.S. Pat. No. 4,509,114 teaches use of a PLA in a control system to interface between an instruction register and primary control circuitry. An operation code in an instruction register is inputted to a PLA to obtain a microword output related to a desired control action. The use of logic arrays taught by the subject patents is in combination with processing circuitry, with a single PAL (PLA) used to obtain a bookkeeping or a translation function.

Available systems for controlling more than one motor generally use a start/stop routine for addressing the motor phases to rotate the motor at an operating speed. Abrupt acceleration and the resulting forces can be significant during the start or the stop of the motor.

Thus, the circuit complexity of conventional systems limits the application of conventional systems to the control of a relatively small number of motors for simultaneous operation. Further, the start/stop characteristics of existing control systems limits the stepping speed for the motors to keep forces within acceptable limits. System operating speed is further limited by the time required for data manipulation and transfer within microprocessor controlled devices.

It is an object of the present invention to simultaneously control a large number of motors.

It is another object of the present invention to program motor acceleration to permit high speed operation without large acceleration forces.

One other object of the present invention is to pipeline data flow and manipulation for improved operating response characteristics.

Yet another object of the present invention is to enable the simultaneous control of a multiplicity of motors, each of which can have individual operating characteristics.

The disadvantages of the prior art are overcome by the present invention, however, and improved method and apparatus are provided for simultaneously controlling a multiplicity of step motors.

Additional objects, advantages and novel features of the invention will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art upon examination of the following or may be learned by practice of the invention. The objects and advantages of the invention may be realized and attained by means of the instrumentalities and combinations particularly pointed out in the appended claims.

To achieve the foregoing and other objects, and in accordance with the purposes of the present invention, as embodied and broadly described herein, the apparatus of this invention may comprise a motor control system for simultaneously controlling a plurality of stepper motors. An addressing means generates address data for each motor in a periodic address sequence. A memory means responds to the address data for each motor by accessing a memory location corresponding to the address data. The accessed memory location contains a first data set functionally related to a direction for moving the motor, a number of steps remaining for moving the motor, speed data for moving the number of steps, and rate of change data for the speed. First logic circuits are provided for inputting the first data set and for outputting a second data set for commanding the addressed motor to make a single step in a determined direction after a number of the periodic addresses of the motor. Second logic circuits provide for inputting the second data set and for outputting a third data set which is functionally related to a status of the motor after responding to the second data set. Circuit means then provide for replacing the first data set with the third data set in the memory at the location corresponding to the address of the motor. The third data set then becomes the first data set at the next periodic addressing of the motor.

In another embodiment of the present invention a method is provided for simultaneously controlling a plurality of stepper motors. Address data is generated for each of the motors in a periodic address sequence. A memory location is accessed which corresponds to the address data and contains a first data set for the addressed motor. The first data set is functionally related to a direction for moving the motor, a number of steps which remain for moving the motor, speed data for moving the number of steps, and rate of change data for the speed. The first data set is input to first logic circuits which output a second data set for commanding the motor to make a single step in a determined direction after a number of periodic motor addresses. The second data set is input to second logic circuits which output a third data set functionally related to a status of the motor in response to the second data set. The first data set is then replaced in the memory with the third data set at the location corresponding to the address of the motor. The third data set thereafter becomes the first data set at the next periodic addressing of the motor.

In yet another characterization of the present invention, a motor control system is provided for simultaneously controlling a plurality of stepper motors. A memory means defines a memory location for each of the plurality of motors for storing a first set of data functionally related to an operational status of each of the motors. A first plurality of programmable array logic (PAL) circuits manipulates the first set of data according to predetermined logic to derive a second set of data for moving each motor. Circuit means are provided for combining the second set of data with the first set of data to derive a third set of data which is functionally related to a revised operational status of each motor. Writing means thereafter replace the first data set in the memory with the third data set.

The accompanying drawings, which are incorporated in and form a part of the specification, illustrate an embodiment of the present invention and, together with the description, serve to explain the principles of the invention. In the drawings:

FIG. 1 is a functional block diagram of a system for simultaneously controlling a plurality of stepper motors.

FIG. 2 illustrates one embodiment of the present invention as a schematic of the data processing system in functional block diagram format.

FIG. 3 is a block diagram of the state sequence generator depicted in FIG. 1.

FIG. 4 is a block diagram of a motor sequencer depicted in FIG. 1.

FIG. 5 is a block diagram of motor drivers depicted in FIG. 1.

FIG. 6 is a schematic for control and status register circuits shown in FIG. 2.

FIG. 7 is a schematic for board state control circuits depicted in FIG. 2.

FIG. 8 is a schematic for multibus interface circuits depicted in FIG. 2.

FIG. 9 is a schematic for address buffer circuits depicted in FIG. 2.

FIG. 10 is a schematic for combinational logic circuits depicted in FIG. 2.

FIG. 11 is a schematic for support function generator circuits depicted in FIG. 2.

FIG. 12 is a schematic for state sequencer circuits depicted in FIG. 2.

FIG. 13 is a schematic for data storage circuits depicted in FIG. 2.

FIG. 14 is a schematic for motor data development circuits depicted in FIG. 2.

FIG. 15 is a schematic for ramp level generator circuits depicted in FIG. 2.

FIG. 16 is a schematic for the motor drivers depicted in FIG. 5.

FIG. 1 is a functional block diagram of one embodiment of the present invention. The system hereinafter described is illustrated for controlling 32 step motors, each of which includes four phase windings for discretely stepping the motor in response to digital commands. It will be understood that the specific number of step motors under control and the specific operating characteristics of each step motor are not limitations herein and are presented only for purposes of illustration.

Data storage 20 is provided as the memory system between circuits for generating motor movement data and circuits for monitoring and registering circuit performance to provide continuous and current motor status data. Control and status registers 10 communicate with support function circuits 14 and data storage 20 through data bus 18 and multibus interface 12. Address lines 16 (A0-A7) enable communications between multibus interface 12 and control and status registers 10. Inputs to control and status registers 10 include system malfunction information, such as a Bad Phase State or Board Over-Temp. A DONE input signal indicates that all of the motors have stepped to their designated locations. A RUN output is a basic enabling signal for State Sequencer 34, as hereinafter described.

Multibus interface 12 provides latch and buffer circuitry connecting address line 16 and data bus 18 with address lines 22 and data bus 24.

Data storage 20 provides a memory location block for each of the motors being controlled. The contents of each motor memory location block indicate the operating status of the particular motor: 1. the number of steps to be taken by that motor toward a new location; 2. the last phase state for the motor; 3. the contents of a skip counter for speed control; 4. a ramp level number for acceleration control; 5. the direction for motor movement; and 6. upper and lower speed limits for the motor.

Each memory location is loaded with a first data set prior to any motor movement. Thereafter, each motor is addressed in a periodic sequence, placing the addressed motor memory in communication with data bus 26. As hereinafter described, the contents of the addressed memory location are placed onto data bus 26 and updated by first logic circuits in motor data development block 28 and ramping block 30 to form a second data set. The second data set is then provided to second logic circuits in motor data development block 28 and ramping block 30 to obtain a third data set. The third data set is placed on data bus 26 and returned to data storage 20 to the memory location of the addressed motor. Thus, the third data set becomes the first data set when the motor is next addressed.

Data placed on data bus 26 are provided to motor data development circuits 28 and ramping circuits 30. State sequencer 34 then sequentially enables and clocks latches and logic circuits within motor data development block 28 and ramping block 30 to process the data on data bus 26 to data suitable for moving the addressed motor. A complete state sequence routine is completed by sequencer 34 each time a motor is addressed.

At the completion of a sequence routine, the system logic has enabled the addressed motor to accept a movement command, has determined whether a movement command (ACTION) is appropriate, and has provided data to motor drivers 40 for energizing a next set of phase windings to step the addressed motor in a determined direction. In addition, motor data development block 28 and ramping block 30 have updated internal counters and other motor status information. Thereafter sequencer 34 writes the updated third data set back into data storage 20 for use when the motor is next addressed.

Motor sequencer 36 enables motor movement when an ACTION signal is received on signal line 38. As shown, one of sectors 1, 2, 3 or 4 is enabled, with eight motors per sector. A CHIP SELECT signal enables the chip controlling the addressed motor. A MOTOR BANK signal further enables the appropriate one of the two motors controlled by each chip. Motor drivers 40 then supply power to the appropriate phase (.PHI..sub.a, .PHI..sub.b, .PHI..sub.c, .PHI..sub.d) to cause the addressed motor to make a single phase change in the required direction.

The detailed descriptions of FIGS. 2-16 refer to various internal signals by terms shown on the drawings. The following glossary of signal terms more particularly defines the terms used herein.

Referring now to FIG. 2, there are more particularly depicted block diagram schematics of the functional blocks depicted in FIG. 1. Control and status register circuits 10 include status register 46, which may conveniently have three input ports A, B, C for receiving output signals from various system sources indicative of the system operational status, the enablement signals, and any malfunction signals to derive an output to data bus 18. Three programmed array logic circuits (PAL) 48, 50, 52 are provided for logically processing the input signals.

Board state control 68 is also a PAL for logically processing selected outputs from PALs 48, 50, and 52 to set latches 70. The output of latches 70 provides flag and enabling signals to data logic circuitry as hereinafter discussed.

Finally, address buffer 54 and data buffer 56 communicate along address path 58 and data path 60, respectively, with multibus 24. Data signals along data bus 18 and address signals along address line 16 are input to multibus 24 through buffers 54 and 56.

Multibus interface 12 includes multibus 24 for accepting address signals and data from status and control register 10. Data buffers 62 and 64 communicate between multibus 24 and internal data bus 26 for data transfer. Multibus 24 also communicates with address enable buffer 78 to provide address information to data storage block 20, as hereinafter discussed. Data swap buffer 66 is provided to enable data to be processed in 8-bit format or 16-bit format from multibus 24 onto internal data bus 26 in 8-bit format.

Combinational logic 67 is within multibus interface block 12. Data source and read/write data is provided to combinational logic block 67 which enables the overall circuit board to read/write to adjacent systems and enable memory elements within data storage 20 to read/write on associated bus lines. Combinational logic 67 also detects an address code which places a motor control board in an operational condition.

Multibus interface 12 includes interrupt latches 71 with jumpers 72 to direct fault/interrupt outputs onto jumpered multibus 24 lines. Address decoding circuit 79 acts to decode information on multibus 24 to determine that a particular control board is operationally enabled.

Thus, multibus interface 12 transfers data between multibus 24 and internal data bus 26 and addresses motor memory locations within HI MEMORY BYTE 74 and LOW MEMORY BYTE 76. Motor data address sequencer 80 and memory section select 82 process inputs from state sequencer 34 (FIG. 1) to enable memory sections of memory units 74 and 76 to be written onto and read from internal data bus 26. Memory units 74 and 76 each have two memory sections, for a total of four memory block sections for each motor. As hereinafter explained, when each motor is addressed, the memory sections for that particular motor are enabled to read from and write on internal data bus 26.

Support function block 14 generates data to determine possible malfunction status of the control system. Analog-to-digital converter 84 receives analog temperature data from the circuit board and analog current data from the motor sectors. Converter 84 provides a digital output to data bus 18 indicative of a malfunction occurrence.

Once a motor is addressed, operational status data for the addressed motor is provided from memories 74, 76 to internal data bus 26. Data line decoder 128 is a PAL unit which monitors the data on data bus 26 to logically derive various status information. The data indicates whether the motor speed is going up or down and whether ramp schedule PROM 90 should be enabled to initiate an acceleration schedule. Further, if all of the counters are zero at the end of a board cycle, Board Action Complete circuit 126 outputs a DONE signal.

Phase Error PAL 116 receives data relating to the present motor phase state and data relating to the next motor phase state, as derived by Next Phase State PAL 118. If the next phase state is not compatible with the present phase state, a phase error signal is latched into latch 124 to indicate a Bad Phase condition. The data in memory units 74 and 76 also sets direction latch 122 for use by Next Phase State PAL 118 in logically deriving the next phase state for the addressed motor to assume. It will be noted that there is no output from PAL 118 unless an output is indicated by the SKIP input, hereinafter explained. Once a next phase has been determined it is latched in Next Phase latch 120 to form a portion of the third data set for return to Data Storage 20.

Ramping circuit 30 is a particular feature of the present control system. Ramping circuits 30 can obtain initial speed information from speed switch 106 through buffer 108 or from an alternate speed source through speed selector 104. Speed data is provided to input RAM speed latch 110 for initial input to ramp schedule PROM 90. Output RAM speed buffer 112 thereafter places speed data on data bus 26 for return and storage in memory 76.

It should be noted that the speed determination by ramping circuit 30 is provided through skip counter 102. A SKIP 32 output is obtained from counter 102 when counter 102 is in an overflow condition. Thus, the rate of output of SKIP signal 32 depends on a preload into skip counter 102. An initial preload count represents a minimum speed for the addressed motor. Thereafter, the count in skip counter 102 is incremented each time the motor is addressed.

The count within skip counter 102 is returned along data bus 26 for writing to memory board 20 when the address cycle is complete. The count data is read from memory 20 and returned to skip counter 102 at the next address cycle. Thus, the contents of skip counter 102 represent an incremented data count. Skip count input latch 98 latches data from data bus 26 for presentation to skip counter 102. The initial preload to skip counter 102 is provided by ramp schedule PROM 90. Thereafter the skip counter 102 data is updated from memory data on data bus 26 until an overflow condition exists. After SKIP 32 signal is output, the skip counter 102 is again preloaded from PROM 90. Skip counter input control 92 loads skip counter 102 from PROM 90 when PROM 90 is enabled for data processing. Control 92 thereafter provides updated count data from memory 20.

PROM 90 provides for increasing or decreasing the speed of stepping a selected motor in programmed increments:

In a preferred embodiment there are eight ramp levels within PROM 90. A change in ramp level occurs after a motor has taken a programmed number of steps at a present ramp level. The ramp level number is determined by ramp level PAL 94 which receives ramp level data which represents a present motor speed and prescaler data which determines the rate of change of motor speed. The selected prescaler data increments or decrements a ramp level number after a predetermined number of SKIP inputs have been counted. The UP/DOWN input determines whether the present ramp level number is incremented or is decremented. Ramp level data is provided to data bus 26 for return to memory.

Thus, the SKIP 32 output generated by ramping circuits 30 indicates that a step is to be taken by the selected motor. As discussed above, SKIP signal 32 is presented to Next Phase State PAL 118 to enable an output to motor drivers 40 (FIG. 1) and to generate ACTION signal 38 indicating that a step is to be taken.

Referring now to FIG. 3 there is shown in block diagram a schematic of State Sequence Generator 34. State Sequence Generator 34 has 32 outputs to enable a series of internal operations to occur in predetermined sequence. Address generator 134 is enabled by a RUN input and clocked by clock source 132. The addresses from generator 134 are provided to state decoders 134, 136, 138, 140 to provide an output on one of the 32 sequence lines. As hereinafter discussed, one entire sequence routine is generated each time a motor is addressed to provide for motor movement and/or memory update.

A functional block diagram of the motor driver circuitry is provided in FIG. 4. An ACTION signal is provided to chip select shaping circuit 144 to indicate that a motor step is to be taken. Motor sequencer 146 has an input clock to step the output of motor sequencer 146 in a preselected manner. The output of motor sequencer 146 is provided to motor select circuits 148, 152 to address a particular motor control chip CS1-16. The selected chip controls two motors and motor bank select circuits 150 provide output MB to select a first motor and then a second motor controlled by one of the signals CS1-16.

FIG. 5 is a functional block diagram of motor drivers 40 (FIG. 1). Voltage inputs (V.sub.OD, V.sub.S), a motor bank signal (MB), and phase state data (A.0., Al, DATA IN) are provided to motor phase output decoders, illustrated as decoders 164A-D in Sector 1. The motor driver chip select signal (CS1-16) enables a particular decoder, e.g., CS1, CS2, CS3, or CS4 in Sector 1.

As shown in FIG. 5, motor drivers 40 are grouped into four sector control groups 154, 156, 158, 160 and the sectors are sequentially enabled to provide for the control of 32 motors. As shown, sector 1 is comprised of motor phase output decoder chips 164A-D, which in turn control motors 1 through 8. Four phase output control signals are provided to energize the motor phases, .PHI.A-D, in a sequence effective to step the motor to a new position.

A detailed schematic of components forming a portion of control line status registers 10 (FIG. 1) is shown in FIG. 6. MC PAL 48, C1 PAL 50, and C2 PAL 52 provide logic circuits relating inputs to outputs as shown in Master Control Table B, Latched Commands Table C, and Unlatched Commands Table D, respectively. The following symbols are used in defining the PAL logic: #=OR; &=AND; !=invert.

Address data and various system read, write, enable, and fault inputs are provided to PALs 48, 50, 52 which logically combine and output a plurality of enablement signals and various command signals to data bus 18 (FIG. 1). It will be noted that in one embodiment of the invention, inverting amplifiers 238A and 232B invert the analog-to-digital write and read enablements, respectively, for input to support function circuits 14 (FIG. 1). Likewise, inverting amplifiers 234A-F invert various outputs from command PAL 52 for further use in the motor control system.

Referring now to FIG. 7, there is shown a schematic of one embodiment of board state control PAL 68 and latches 70 (FIG. 2). The state control is basically provided by CM PAL 68 which logically combines inputs as shown in FIG. 7 to derive output signals representing the operational status of the system. The outputs from PAL 68 are presented to NOR gates 238A, B, C, D, E, F for presentation to J-K flip-flops 240A, B, C, D, E, F, where the output from a NOR gate toggles the associated flip-flop to place an output on the Q line from the flip-flop. OR gate 242 further combines outputs from flip-flops 240C and 240D to provide a Write Enabled output.

The outputs from CM PAL 68 are also provided to timing circuits for use in system operation. Delay timing one-shot flip-flop 248 provides timing for the high voltage (HV) signals where the high voltage supply is terminated after an interval with no control activity. Start delay one-shot flip-flop 246, NAND gate 250, and NOR gate 252 provide a delayed output to one-shot flip-flop 254 to provide time for the system to place itself in a start condition prior to beginning a control run.

The high voltage control signals are derived through NOR gate 262 and NOR gate 264 to provide a first preset to J-K flip-flop 260 as a fault condition indicator. SET fault and CLEAR fault signals are also provided to flip-flop 260 and derive a clocking output through NOR gate 258 to derive a FAULT signal for input to AND gate 268 along with a voltage timeout signal from flip-flop 248. A High Voltage ON output is obtained from AND gate 268 and a High Voltage OFF (HV ON) output is obtained through inverting amplifier 270 to turn off the high voltage. Thus, motor voltages are terminated when motor movement is completed or where a fault condition exists in the system.

Referring now to FIG. 8, there is shown a schematic of components forming a portion of multibus interface circuits 12 (FIG. 1). Status register 46 in control and status board 10 (FIG. 1) obtains a plurality of inputs, shown in FIG. 8, from the outputs of PALs 48, 50, 52 (FIG. 6) and provides an output on data bus 18 (FIG. 1), to data buffer 56. Data buffer 56 thereafter outputs data lines 60 (FIG. 2) to multibus 24 data lines (D.0.-D9/D.sub.A -D.sub.F). Data buffers 62 and 64 accept data from multibus interface 24 and transmit the data to internal data bus lines (IDB.0.-15). Data swap buffer 66 may be enabled to permit either 8-bit or 16-bit data to be handled.

It will be noted in FIG. 2 that the multibus 12 interface function includes circuitry 79 for developing an address code (ADDECODE). Schematically this circuit is parallel address lines with associated parallel inverting amplifiers which may be jumper connected to outputs in a preselected manner. These jumper outputs are provided to a NAND gate which simply provides an address output when the preselected address signals are present to enable one particular motor control circuit board.

The remaining portions of multibus interface 12 function are shown in FIG. 10. Combinational logic 67 (FIG. 2) is formed from a plurality of logic elements. A data source may be selected from a computer (MRC, MWC) or from an IN/OUT port (IORC, IOWC). Conversion status information is provided from the analog-to-digital converter 84 (FIG. 2). AND gates 282A, B process the memory/in-out data and OR gate 284 handles the analog-to-digital data. Data processing is provided through NOR gate 286 with inverting amplifiers 298B and 292A, B. Additional status input, as shown in FIG. 10, is processed through AND gates 288A, B. The output from NOR gate 286 is further processed through amplifier 292D and inverting amplifier 290C to form the final output enabling signals as shown.

Interrupt latches 71 comprise flip-flops 294A, B, C with parallel outputs and inverted outputs through inverting amplifiers 296A, B, C. The outputs and inverted outputs may be connected with jumpers 298 in a preselected manner to provide interrupt signals to multibus 24.

Support function circuitry 14 (FIGS. 1, 2) is shown schematically in FIG. 11. Analog-to-digital converter 302 receives temperature, current, and voltage inputs in analog form for conversion to digital data. Temperature sensor 310 detects the circuit board temperature which is amplified by amplifier 312 for presentation to converter 302 and to comparator 314. Reference voltage source 304 and voltage controlled oscillator 306 are provided for the conversion process. Comparator 314 directly provides a status output of an over-temperature condition on the circuit board (BD OVER TEMP).

Status information on the conversion process (signals A/D WRITE, START CON, A/D READ) are provided to converter 302 for enabling analog data input, the conversion process, and digital data output. The status signals are also provided through OR gate 318 to latch 320 and then to OR gate 322. The output of OR gate 322 is a status signal that the analog-to-digital conversion process is complete, enabling the system to accept the digital data.

State Sequencer 34 (FIG. 2) is schematically shown in FIG. 12. A sequential Address Generator 334 is clocked from clock 330 through AND gate 332 in conjunction with a RUN signal. Flip-flop 336 and Address Generator 334 provide inputs to State Decoders 338A, B, C, D, which thereafter provide a sequence of 32 output signals to sequentially enable an operational routine for system components as shown in FIGS. 13-16. The routine of operational events triggered by State Sequencer 34 is the following:

In several of the state conditions, a plurality of elements are enabled for data processing to pipeline data through the logic circuits. Either the leading [+] or the trailing [-] edge of the clock pulses may trigger a sequence event. It will be apparent from the State Sequence Routine that motor data is read onto the data buses along with various counter totals and loaded into various system components. The loaded data is logically processed to a second data set which is further logically processed to determine if the selected motor should move and the direction and phase information for a movement. The counter totals are updated and the derived third data set is placed back in memory for use during the next motor address sequence. Thus, existing data is processed directly to produce movement of a motor, the data is updated in parallel with this processing, and the updated data is returned to the memory system. There are no data processing loops which must be satisfied and the data moves directly, or pipelines, through the logical processing networks.

Referring now to FIG. 13, there is shown a schematic of data storage circuits 20 (FIGS. 1, 2). RAM storage is provided in memory units 342, 344. Portions of the RAM memories are selectively enabled by State Sequencer 34 (FIGS. 1, 3, 12). LO MEM BYTE 344 accepts data from data lines IDB.0.-7. HI MEM BYTE 342 accepts data from data lines IDB8-15. Specific memory locations are addressed on address lines IAB1-7.

State sequencers 34 specifically enable one memory data section A, B, C at a time through AND gates 346, 348 and flip-flops 350, 352 through amplifiers 354, 356 onto selected address lines. Thus, the memory sections are enabled in the sequence depicted in the State Sequence Routine, hereinabove set out.

Motor Address Sequencer 360 provides a clocking address sequence for specific motor data stored in RAMs 342 and 344. Each motor data section has memory groups A, B, C containing the data noted in Table E, Memory Layout.

The memory locations for the addressed motor are enabled and the enabled memory sections read data on data bus 26 upon an enabling output logically derived through NOR gate 362, flip-flop 364, and AND gate 366 from enabling signals generated by State Sequencer 34. Data from the enabled memory sections are written to data bus 26 when enabled by State Sequencer 34 signals processed through AND gate 368.

Motor data development circuits 28 (FIG. 1) process the data in RAM memories 342, 344 to derive new phase state information from the present status data for an addressed motor. Phase information is processed through PAL 372 and PAL 374. Phase Error PAL 372 logically processes input data from Data Storage 20 (FIG. 1) for input to Next Phase PAL 374, which determines the next phase data for moving the selected motor. A SKIP input is also provided to PAL 374 for enabling an output if a movement is to actually occur.

The next phase data is latched into next phase latch 376 and further returned to PAL 372. PAL 372 logically determines from the present phase state data from memory and the next phase state data from PAL 374 if a phase error exists. Table F is the output logic for Phase Error PAL 372. Table G is the output logic for Next Phase PAL 374.

If the present phase state and the next phase state are not logically compatible then an error condition exists. A flag is output for processing through NAND gate 408, flip-flop 410, NAND gate 412, and inverting amplifier 414 to provide a Bad Phase State status signal and a NO ACTION signal, where necessary. Flip-flop 378 enables the contents of latch 376 to be read back into memory as enabled by the state signals from State Sequencer 34.

The phase state circuitry also counts step data relative to the number of steps taken by the motor toward the final destination. Counters 382 and 384 communicate with memory section A, which contains step count data. A present step count is loaded into counters 382, 384 and is updated during each address cycle of the motor by State Sequencer 34. State address lines are provided to AND gate 386 and flip-flop 388 for input to counters 382 and 384.

Counters 382 and 384, thus, receive step count data from data bus 26, update the step count data, latch the updated data for return to RAM memories 342 and 344, and enable the data to be returned.

AD PAL 392 monitors data bus 26 and logically decodes the data, as shown in Table H. PAL 392 determines whether the motor is accelerating or decelerating. Motor acceleration is programmed to occur within a predetermined number of steps from a motor start condition, preferably 256 steps. Likewise, deceleration is predetermined to begin within a preselected number of steps of reaching the motor destination, again preferably 256 steps. Count data within counters 382, 384 enable this determination to be made.

AD PAL 392 further monitors all counter data during the state sequence routines. When the counter data is zero for all motors at the completion of a board cycle, an output is obtained to indicate that the board action is complete. Thus, where flip-flop 402 is cleared by a Board Cycle Request through NOR gate 404, memory section A data is latched per amplifier 396 output, and ALL ZERO signal is present, NAND gate 398 clocks flip-flop 402 to provide an input to flip-flop 406 to derive a DONE output, indicative of movement completion, on a clocking signal.

One of the unique aspects of the present apparatus is the ramping circuitry. One embodiment of a ramping circuit is depicted in FIG. 15. Conventional step motor systems generally began moving the step motor at a preselected rate and the instantaneous acceleration forces can severely stress motor components. The present apparatus provides for reducing the acceleration forces by accelerating and decelerating the step motor according to a predetermined schedule.

As herein described, eight speed levels, herein ramp levels, are provided. Each step motor can be provided with an independent minimum initial stepping speed and a final operating maximum stepping speed. Ramp schedule PROM 434 will then begin motor stepping at the minimum speed and progressively increase the operating speed until the maximum operating speed is obtained. At each step level PROM 434 outputs a programmed speed as a percentage of the maximum speed permitted by input maximum speed data. Ramp Level PAL 428 outputs a ramp level number from one to eight for input to ramp schedule PROM 434. The logic output for Ramp Level PAL 428 is set out in Table I.

A ramp level is maintained for a predetermined number of steps and after a motor has taken the predetermined number of steps the ramp level number is incremented. Ramp level latch 426 receives data from data bus 26 and latches the data upon receipt of a latch ramp level state signal. The received data have one data portion with the ramp level number stored in memory and another portion with the number of steps taken at the stored ramp level number. The data are latched in latch 426 with the ramp level number portion provided to both PROM 434 and PAL 428. The step count data are provided to ramp level PAL 428. When a PAL clock signal is provided through OR gate 430, PAL 428 logically combines the ramp status data with flags indicating an accelerating or decelerating condition (UP/DOWN) and a SKIP flag indicating whether an actual motor step was taken. The step count is incremented when an actual motor step has been taken. When a motor is accelerating, the UP/DOWN flag increments the ramp level number and, when decelerating, decrements the ramp level number after a predetermined number of steps has been taken.

Speed data may be input from a variety of sources. As shown in FIG. 15, switches 106 are provided for setting a lower speed or an upper speed through buffer 108. The speed input source is selected through NAND gate 422 and inverting amplifier 324 to enable a source from switches 106 or from RAM memories 342 and 344 (FIG. 13). Speed data from RAM memories 342 and 344 may be input through latch 110 to Ramp Schedule PROM 434. Thereafter, buffer 112 serves to transfer data from data bus 26 to ramp schedule PROM 434.

Thus, the output from ramp schedule PROM 434 is functionally related to a derived stepping speed for the motor being addressed. Skip counter 102 logically combines input data to determine whether action should be taken by a motor. The operation of skip counter 102 is determined by a preload count which is provided from PROM 434. An overflow signal from skip counter 102 indicates that an action should be taken. It is apparent that the higher the preload number, the fewer the counts required to produce an overflow condition, and the faster the stepping speed of the motor will be.

Once an initial preload count has been provided to skip counter 102, however, counter data are incremented as skip counter clocking pulses arrive through AND gate 444. The incremented data are stored in RAM memories 342, 344 until the appropriate motor is next addressed.

Upon an appropriate state sequence signal, latch 98 is enabled to accept data from data bus 26 for latching into counter 102. Logic circuit components NOR gate 436, flip-flops 438 and 442, and NAND gates 440A, B determine the source of the preload count for counter 102. When PROM 434 is enabled to derive an output speed, the initial preload count is from PROM 434. Thereafter, the logic circuit disables the count from PROM 434 and enables the latched count in latch 98 to preload counter 102.

Ramping circuit 28 (FIG. 1) provides SKIP signal outputs at a rate which is functionally related to the desired maximum speed of the stepping motor. The stepping speed is incrementally increased or decreased to accelerate/decelerate the motor to the speed limits. Once a maximum operating speed in determined, RAM memories 342, 344 (FIG. 3) control the steady state operating speed until the motor is within a predetermined number of steps from completing its movement. Thereafter, PROM 434 is again enabled to decelerate the motor within the remaining steps. The motor data development circuitry 28 (FIG. 1) has now provided a phase data output indicative of a phase address and the direction in which the motor will turn to reach that phase address (see data outputs ADD0, ADD1, DATA IN in FIG. 1). Motor sequencer 36 outputs an address of the selected motor chip and a data bit selecting one of two motors from the selected motor chip.

FIG. 16 presents schematic circuitry showing one control sector for driving output motors. It will be appreciated that the motor and sector groupings herein discussed represent only one embodiment of the present invention and other combinations may obviously be obtained without limitation to the invention herein disclosed. Common to all of these sectors are components for sequantially addressing a motor to be stepped and input lines controlling the phase selection and currents.

A sector is first selected by an enablement signal, SEC (1, 2, 3 or 4) ENBL, from Latch Command PAL 50 (FIG. 6). Within a sector, with Sector 2 being illustrated in FIG. 16, a specific motor address is generated by sequential addressor 452, with clock signals input through amplifier 458 and a system status signal generated through OR gate 454, flip-flop 456, and inverting amplifier 462. The chip address generated by sequencer 452 is delivered to decoder units 482 (Sectors 1 and 2) and 484 (Sectors 3 and 4) to enable a specific chip.

It will be appreciated that no output is delivered to a motor unless an enabling signal is received from flip-flop 466, the CS ENABLE signal. The inputs to flip-flop 466 include a Preset input if the system is ready for action, an ACTION input indicating that the skip counter has determined that the addressed motor is to be stepped and a clock signal to synchronize the enabling output. The enabling output is provided to decoders 482 and 484 to combine with a specific chip address from sequencer 452, a SECTOR enable signal, and a motor bank MB signal to place a single motor in condition to take a single step. The phase information (A2, A1, DATA) is now provided through the selected motor phase output data decoder 486A, B, C, or D through the safety diodes to the selected motor. Thereafter, the motor takes one step in the indicated direction.

It should be recognized that the motor control system herein described may interface with a system, not herein described, for deriving the positions to which the step motors are to be stepped. Position data from this separate system can be interfaced with RAM memories 342 and 344 to enable enhanced control of step motor positions. In the described embodiment a total of 32 motors are controlled from a single circuit board layout. Up to six circuit boards have been combined to control 192 motors at an operating address rate of 40,000 addresses per second. Thus, a motor stepping rate of up to about 20,000 steps per second might be taken with 192 controlled motors, depending on the capabilities of the selected motors, where each motor has a unique set of operating parameters stored in the system RAM memories 342, 344. Stored data are logically combined for pipelining directly to effect motor movement, with the data reflecting the status of the moved motor being logically derived and returned to memory for storage and subsequent use.

The foregoing description of the preferred embodiment of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed, and obviously many modifications and variations are possible in light of the above teaching. The embodiment was chosen and described in order to best explain the principles of the invention and its practical application to thereby enable others skilled in the art to best utilize the invention in various embodiments and with various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims appended hereto.