Interface Circuit for Connecting Peripheral Equipment to a Computer Terminal

The present invention relates to an electronic interface controller configured to connect a number of functionally distinct pieces of peripheral equipment to a financial terminal. A typical configuration of peripheral equipment includes a keyboard, a magnetic stripe reader and a printer, though other reading and visually perceivable output means are contemplated additions. As embodied, the interface controller selects the peripheral equipment, prescribes the operating mode, and establishes the timing and synchronism which regulates the transfer of data between the terminal and the selected piece of equipment. The embodying interface controller also incorporates a section of random access memory (RAM) and a section of read only memory (ROM); the former for temporary data storage and the latter for expanding the financial terminal control logic to handle the peripheral equipment.

One unique aspect of the invention resides in a novel counter circuit which exhibits operational features particularly suited for dividing frequencies in synchronously operated circuits. The various embodiments of the counter circuit are characterized by their use of D-type flip-flops (FFs) in combination with steering logic in multiple feedback loops to cause the division of the clock frequency according to the design modulo. The utilization of D-type FFs with feedback ensures synchronism in the start and stop operation, appropriate sequencing of the count, and the absence of race conditions and timing skews. This combination of structural and operational features is particularly valuable in the context of integrated circuits, where each D-type FF consumes a relatively small amount of chip area when compared to the J-K type FFs conventionally used to implement counting circuits.

These and the other novel features which are inherent in the interface controller and counter circuits will be understood upon considering the ensuing description of the preferred embodiment.

FIG. 1 schematically illustrates the structural relationship of the interface controller to the composite financial system.

FIG. 2 is a functional block diagram of the interface circuit.

FIG. 3 is a legend relating functional equivalents.

FIGS. 4, 5, 7, 9, 10 and 11 are schematic block diagrams of various sections in the embodying interface circuit.

FIGS. 6, 13 and 14 contain schematic block diagrams of counters utilized in the embodying interface circuit.

FIGS. 8 and 12 contain timing diagrams for various signals in the interface controller.

The connection of multiple financial terminals directly to a single financial computer is a widely-recognized approach to providing the terminal operator, for instance a bank teller, with access to the stored data and the computational capabilities of the computer. With the trend toward greater automation in transactions between financial institutions and their customers, there is a growing recognition that future financial systems will include some form of direct customer access to limited features of the computer system through distinct peripheral equipment functionally different from the financial terminal. In such a case, the financial terminal would be retained as an intermediate control, to selectively designate the peripheral equipment and to regulate the content of the data transferred to and from the financial computer.

One aspect of the invention relates to an interface controller by which various pieces of peripheral equipment are coupled to a financial terminal. Another aspect relates to unique configurations of counting circuits.

To understand the composite invention as presently embodied, consider the generalized financial system depicted in FIG. 1 of the drawings, in the context of a banking system. The peripheral equipment is first selectively enabled by a teller, using Financial Terminal 2. The customer then identifies himself and his account with a magnetically-coded Credit Card, 6, by moving the card through Magnetic Stripe Reader 5. Thereafter, the customer makes his request known using Pin Pad Keyboard 7 and receives a copy of the complete transaction in the form generated by Dot Matrix Printer 4. From the arrangement of the equipment shown in FIG. 1, it is clear that Interface Controller 3 not only selects and regulates the peripheral equipment, but provides a path for bidirectional transfer of instructions and data between Financial Terminal 2 and the attached pieces of peripheral equipment. As shown generally in FIG. 1, Financial Terminal 2 is merely one of multiple financial terminals connected to Financial Computer 1.

Interface Controller 3, as presently embodied, is comprised of four individual sections: Interface Circuit 8, RAM 9, ROM 11 and Latch 12. ROM section 11 expands the addressable instruction set for the controller to accommodate the peripheral equipment, while RAM section 9 serves as temporary storage for Magnetic Stripe Reader 5 data when Financial Terminal 2 is occupied with other functions. Latch 12 holds the binary coded data sent from Financial Terminal 2 to Pin Pad Keyboard 7 in the course of determining which keys are depressed. Though shown as a separate entity, a preferable configuration would integrate RAM 9, ROM 11, Latch 12 and Interface Circuit 8 into a single unit when all three pieces of peripheral equipment, 4, 5 and 7, are contemplated for the overall system.

The ensuing analysis of Interface Circuit 8 will commence with a functional overview. Thereafter, the operations of RAM section 9, ROM section 11 and Latch section 12 will be described individually. The unique counter circuits noted previously will be developed in conjunction with the concluding description of the structural circuits which constitute Interface Circuit 8.

The functional block diagram of Interface Circuit 8 is depicted in FIG. 2 of the drawings. The direction of data flow, input (I) or output (0), is represented by the arrowhead orientation on the signal flow lines. Any line may actually represent multiple electrical paths. The line symbols, the direction of data flow, and functional summaries of the lines, are presented in Table I, below.

Though the operational logic for interfacing Financial Terminal 2 (FIG. 1) to Printer 4, Magnetic Stripe Reader 5, Keyboard 7, RAM 9, ROM 11 and Latch 12 can be discerned by one practicing in the art upon an analysis of the schematics in the ensuing drawings, logic Tables II-VIII are provided to summarize the

relationships and ease the understanding of the numerous and often related functions being performed. In the tables, the symbol "X" represents a "don't care" condition.

The RAM and ROM selection logic is considered first. Table II presents the combination of input signals used to generate output signals RAMB and ROMB, respectively enabling RAM section 9 (FIG. 1) and ROM section 11.

The determination of which key is depressed on Pin Pad Keyboard 7 (FIG. 1) follows a sequence established in Financial Terminal 2, during which a group of coded binary data patterns are entered into Latch 12 and applied to Pin Pad Keyboard 7. The output of the keyboard is monitored by Financial Terminal 2. Since the structure of Pin Pad Keyboard 7 is mechanically fabricated to generate an output only when the code in the data pattern and the depressed key correspond, a single output line, coupled directly to Financial Terminal 2, is suitable to convey the match signal. The detailed circuit arrangements are relatively well known by those practicing in the art.

The signal on PLEDB sequentially latches the group of coded data patterns into Latch 12 (FIG. 1) as they are generated by Financial Terminal 2. The logic defining the signal on line PLEDB is presented in Table III. In particular, note that a demultiplexing command signal must appear on line ALE before the coded data from Financial Terminal 2 is coupled to AD Bus 25 (FIG. 2).

The logic for establishing the magnetic stripe format generates a signal on line PBSB to Magnetic Stripe Reader 5 (FIG. 1). The logic conditions are summarized in Table IV. The PBSB signal is used to distinguish whether the data signals are to be generated by a passbook or a credit card. Though both have magnetically encoded stripes which are sensed by Reader 5, the stripes differ in the format utilized for the data. Again, demux command signal ALE is required to enable transmission of data.

The enablement of the light-emitting diode (LED 15) by a signal on line MLEDB to Magnetic Stripe Reader 5 (FIG. 1) is defined by Logic Table V. As was true for the previous two tables, the appropriate ALE signal must exist.

The operation of Magnetic Stripe Reader 5 (FIG. 1) is initiated when a document present, DOCP, signal is generated. Table VI defines the logic conditions to generate a signal on line DOCP, a signal indicating the physical presence of a document in the slot of Magnetic Stripe Reader 5.

Data representing the state and availability of Dot Matrix Printer 4 (FIG. 1) are coupled to Financial Terminal 2 on AD Bus 25 (FIG. 2), lines ADO and ADl, as defined by Table VII.

The generation of a service request signal from Dot Matrix Printer 4 (FIG. 1) to Financial Terminal 2 is prescribed according to the logic in Table VIII.

With the interface logic generally defined, attention will now focus on the operation of the functional blocks depicted in FIG. 2 to electrically create the prescribed control signals. Recall that the functional blocks in FIG. 2 represent only the section of Interface Controller 3 entitled Interface Circuit 8. The remaining sections, entitled RAM 9 (FIG. 1), ROM 11 and Latch 12, represent relatively routine arrangements of conventional devices. Also, note the correspondence of the reference symbols used with the lines in FIG. 2, in Table I, and in the ensuing figures of the drawings.

Attention is now again directed to FIG. 2. As shown by the blocks, RAM 9 (FIG. 1) or ROM 11 are enabled by Memory Select Logic block 14, using respective lines RAMB and ROMB, when the appropriate binary patterns are applied to lines Al0-Al5, IOMB, and HLDA. Control Logic block 16 performs numerous preliminary logic operations which relate to the proper operation of blocks 14, 17, 18, 21, 22, 24 and 34. Consequently, the contributions of block 16 will be considered at the time the affected blocks are described.

Pin Pad Clock block 17 generates an output signal on the PLEDB line. This signal is used to synchronously latch a coded binary pattern into Latch 12 (FIG. 1) for transmission on AD Bus 25 to Pin Pad Keyboard 7.

Latch And Decode block 18 in FIG. 2 generates a series of internal clock signals to synchronize the transmission of signals on AD Bus 25 within Interface Circuit 8.

Reader And Printer Logic block 19 senses the various status conditions for Dot Matrix Printer 4 (FIG. 1) and Mag Stripe Reader 5.

Passbook Logic block 21 and Mag Stripe LED Logic block 22 in FIG. 4 interact with Mag Stripe Reader 5. Block 21 is used to select the magnetic format, prescribing either a credit card format or a passbook stripe format. Block 22 contains logic to signal the availability of Mag Stripe Reader 5. The outputs of logic blocks 21 and 22, lines PBSB and MLEDB respectively, are determined by the input signals on AD Bus 25, as prescribed previously in Tables IV and V.

Printer Service Request Logic block 24, Printer Data Bit Synch block 29, and Printer Word Strobe block 31 in FIG. 2 generate control signals which relate to the operation of Dot Matrix Printer 4 (FIG. 1). Block 24 generates a signal to indicate the availability of Printer 4, while block 29 generates validation pulses in synchronism with the data. The strobe pulses generated by block 31 signal the end of each 8 bit serial word transmitted from Serial Shift Register block 32 to Printer 4 on line JSDO.

Mag Stripe Service Request Logic block 34 in FIG. 2 generates a signal to indicate the availability of Mag Stripe Reader 5 (FIG. 1). Address/Data Bus Buffer block 23 represents a group of bidirectional, tristate devices used to buffer incoming and outgoing signals on lines AD0-AD7 of AD Bus 25. The eight lines of parallel data on AD Bus 25 are converted to serial format for Printer 4 (FIG. 1) using Parallel Register 26 and Serial Shift Register 32. Serial data generated in Mag Stripe Reader 5 (FIG. 1) is coupled back into AD Bus 25 from line MSRD, by way of Shift Register block 36, Parallel Register block 37, and Address/Data Bus Buffer 23.

The master clock signal on line CLK is divided down in frequency to convert data signals between serial and parallel formats. The division is performed by counter blocks 27, 28 and 33. The novel features which characterize the structural organizations of the embodying counters will be described in significant detail hereinafter.

With a functional understanding of Interface Circuit 8 at hand, attention will now be directed to the relationships between Interface Circuit 8 and RAM 9, ROM 11 and Latch 12 (FIGS. 1 and 2). ROM 11 expands and modifies the firmware in Financial Terminal 2 to operate the terminal with one or more pieces of peripheral equipment, e.g. Dot Matrix Printer 4. RAM 9 provides the additional data storage capacity required in the terminal to retain data from Magnetic Stripe Reader 5 when Financial Terminal 2 is occupied with other operations. Therefore, RAM 9 and ROM 11 of Interface Controller 3 are coupled directly into Financial Terminal 2, with Interface Circuit 8 merely serving to energize the appropriate memory when Financial Terminal 2 generates the appropriate bit code on address lines Al0-Al5 (FIG. 2).

As was briefly described hereinbefore, Latch 12 is coupled to AD Bus 25 to retain sets of coded data generated by Financial Terminal 2. Each set of coded data is subsequently coupled to Pin Pad Keyboard 7 (FIG. 1) in the process of matching the coded data with the depressed keys. The output from Keyboard 7 is coupled directly back into Financial Terminal 2 using a line from AD Bus 25.

FIG. 3 of the drawings provides a legend showing the correspondence between the contemporary designation of logic blocks utilized herein and the formerly followed convention. The remaining blocks, flip-flops, latches and registers, follow a self-evident marking convention. The blocks marked with the symbols "(INP)" and "(OUT)" are the opposite halves of tristate buffers. The letter "P" within a small square at the termination of a line represents an input or output pin, and corresponds by line symbol to the input and output lines depicted in FIG. 2.

The detailed analysis of the preferred embodiment structure begins with FIG. 4 of the drawings. Logic AND gates 38 and 39 receive binary patterns of data on lines Al0-Al5 and generate signals on lines RAMB and ROMB to selectively enable RAM block 9 (FIG. 1) and ROM block 11, respectively. Lines HLDA and IOMB also couple signals from Financial Terminal 2 (FIG. 1) into gates 38 and 39. A signal on either line, HLDA or IOMB, disables Interface Controller 3, while the absence of a signal, i.e. a binary "0", enables the selection of RAM 9 or ROM 11 according to the binary logic in Table II.

Lines AD0-AD7 of AD Bus 25 are connected through tristate input amplifiers 41, 42, 43, 44, 46, 47, 48 and 49 to latch 51. These amplifiers permit bidirectional operation of AD Bus 25, and further serve to interface the voltage levels on the AD Bus, typically TTL signals, with the MOS levels internal to Interface Circuit 8 (FIG. 1). The CLOCK line attached to latch 51 causes the data on AD Bus 25 to be latched, separating the address signals, which appear during the first sequence, from the data signals, which appear during the successive sequence. Latch 51 is reset by gate 52 when either line IOMB or RSTB receives a binary "1" level signal.

Logic AND gates 53, 54, 56, 57, 58 and 59 in FIG. 5 decode the AD Bus signals held in latch 51 (FIG. 4). Note that outputs from the logic gates, on lines CS0-CS6, represent a combination of AD Bus data joined with signal CSE, which signal is itself generated by AND gate 67 from a combination of signals originating on bus lines AD3-AD7 with HLDA and IOMB. According to the logic conditions imposed by gate 67, the generation of a signal on line CSE requires the absence of signals on HLDA and LA3-LA7 together with the presence of signals on IOMB and LA7.

FIG. 5 shows that the signal on the CLOCK line, used to operate latch 51 (FIG. 4), is generated in logic gate 66 when signals on lines IOMB and ALE appear concurrently. Reference to Table I indicates that ALE carries a demultiplexing signal for AD Bus 25 (FIG. 2) and is used, as noted hereinbefore, to separate the sequence of signals according to whether they represent address information o data information.

The series connected logic gates 54 and 61 are combined with FFs 62 and 63 to generate signals which enable Mag Stripe Reader 5 (FIG. 1), to synchronize its operation and to couple its data onto AD Bus 25. It should be recognized that Mag Stripe Reader 5 generates serial data whose time sequence varies according to the rate at which Card 6 (FIG. 1) is moved through Reader 5. During the operation of Mag Stripe Reader 5 a signal on line CSl indicates the selection of the mag stripe reader from among the peripheral equipment, and a concurrent signal from Financial Terminal 2 (FIG. 1) on line WRB activates AD Bus 25 to transmit data to the financial terminal. Gate 61 generates the clocking signal for FF 62. When clocked, FF 62 enters the data on line BDO from Financial Terminal 2 (FIG. 1) and generates opposite signals on output lines BlDO and BB2RST. The signal on line B1DO actually enables Mag Stripe Reader 5. The signal on BB2RST is used to reset the serial-to-parallel converter depicted in FIG. 7, which converter effectively groups serially generated mag stripe reader data into eight bit sets for AD Bus 25. FF 63 detects the enablement of the mag stripe reader, and generates a signal on line MQ to indicate the actual movement of a magnetically coded card or passbook through Reader 5 when the first bit sequence is detected by the presence of a signal on Q6.

The mag stripe reader generated clock signal on line RCLB is combined with the power supply voltage V.sub.DD in logic AND gate 68 to generate the clock signals for converting mag stripe reader data from serial to parallel format. The conversion is performed by a segment of the circuit shown in FIG. 7.

Logic gate 64 in FIG. 5 generates the clock signal to latch the data on AD bus 25 (FIG. 2) into externally located Latch 12 (FIG. 1) in preparation for a write action using Pin Pad Keyboard 7.

The circuit composition of the modulo 8 counter is depicted in FIG. 6. Functionally, it performs the divide-by-eight operation shown in block 33 of FIG. 2. The counter generates an output signal on line Q6 for every eight clock pulses appearing on line BlRCLDO, the signal generated in Mag Stripe Reader 5. The analysis of the novel implementation by which D-type FFs, 69, 71, 72 and 73, are combined with logic gates, 74, 76 and 77, in a feedback loop arrangement, will be deferred until the analogous modulo 12 and modulo 16 counter circuits are considered in detail.

Now consider the circuit in FIG. 7. The combination of gates 78, 81 and 82, together with FF 83, generates a service request signal on line SRQlB. The service request signal is coupled to Financial Terminal 2 (FIG. 1) to indicate that mag stripe reader data is available on AD Bus 25 (FIG. 2). The functions of the signals on lines RDB, DOCP and SRQ1B are described in Table I. The origins of signals on lines CS0, B1D0 and MQ were described previously with reference to FIG. 5.

The serial data generated by Mag Stripe Reader 5 (FIG. 1) appears on line MSRD in FIG. 7 and is converted by the combined action of shift register 84 and latch 86 to parallel format. The conversion is performed by having the serial data on line MSRD shifted synchronously into register 84 by the card-generated clock signals appearing on line B2RCLDO. The signal on line Q6, generated by the modulo 8 counter in FIG. 6, latches eight bit groups of data into latch 86. Thereafter, tristate output amps 87, 88, 89, 91, 92, 93, 94 and 96 are enabled by signals on lines RDB and CSE to write the latched data onto AD Bus 25.

FIG. 8 contains a timing diagram showing the wave shapes and sequencing of signals on selected lines from FIGS. 5, 6 and 7. Progressing in time sequence from the left of FIG. 8, the first event is the clock "1" transition on line B2RCLDO. Coincident with each successive falling edge of B2RCLDO, mag stripe reader data on line MSRD is shifted into register 84 (FIG. 7). The clock "1" falling edge of BlRCLDO enables and commences the counting by the modulo "8" counter depicted in FIG. 6. The falling edge of Q.sub.6 coincides with the falling edge of BlRCLDO at clock "7," to latch the data from register 84 (FIG. 7) in the course of converting it from serial to parallel format. Thereafter, SRQlB indicates the availability of converted data on the AD Bus 25 (FIG. 2).

In the overview of FIG. 7, note that the entry of data into shift register 84, corresponding to the clocking of B2RCLDO, always precedes the serial-to-parallel converter timing signals on B1RCLDO. Also note that BlDO is enabled throughout the time interval being considered.

The circuit blocks appearing in FIG. 9 perform other sequencing control functions used during the operation of Dot Matrix Printer 4 (FIG. 1) and Mag Stripe Reader 5. Gate 97 and FFl0l combine a signal on line CS2, representing data received from Financial Terminal 2 (FIG. 1), with a signal on line WRB, defined in Table I, to clock in the data signal appearing on line BD0 and generate an output signal on line PBSB. The PBSB signal is used by firmware within Financial Terminal 2 to determine whether the magnetic stripe data is in credit card or passbook format.

Gate 98, FFl02 and gate 104 combine signals on lines CS5, WRB and BUSY to generate a printer service request signal on line SRQ2B, which notifies Financial Terminal 2 accordingly. Gate 99 is used in conjunction with FFl03 to generate a signal energizing LED 15 (FIG. 1) on Mag Stripe Reader 5, as a means of indicating the reader's availability.

The data representations on lines MD0, DOCP, BUSY, MDl and SLIP are multiplexed onto two lines, D0O and D1O, for coupling to AD Bus 25 and eventually into Financial Terminal 2 (FIG. 1). The state of the multiplexer is established by a logic combination of signals generated in Financial Terminal 2 according to the arrangement of logic gates 106, 107, 108, 109, 111, 112 and 113. Lines MD0 and MD1 originate at latch 86 in FIG. 7. The DOCP, BUSY and SLIP lines present signals indicating conditions as defined in Table I.

The circuit in FIG. 10 illustrates an embodiment of the logic by which data directed to Dot Matrix Printer 4 (FIG. 1) is converted from the parallel format of AD Bus 25 (FIG. 2) to the serial format required by Printer 4. Line JSDO conveys the output signals to the printer. Gate 114 generates a signal on line PLD when the bus is in the write mode and the printer is selected. Data on AD Bus 25 (FIG. 2) are coupled on lines BD0-BD7 to the preset inputs of a group of D-type FFs connected to operate as a shift register. For instance, data on line BD7 is logically combined in gate 115, then connected to the preset input "P" of FFll7. FFll7 is reset by the output of logic gate 116. Note also that the "Q" outputs of shift register FFs serves as the "D" inputs to successive FFs in the register. For instance, FFl2l is preset according to gate 118, reset according to gate 119, and receives its "D" input signal from the "Q" output of FFll7. The structural arrangement of the circuit is repeated in area 122 for BD5, BD4, BD3, BD2 and BDl, finishing with gates 123 and 124 for generating a JSDO line output from FFl26. The shift register arrangement in FIG. 10 is clocked by a signal on line SK.

The circuitry shown in FIG. 11 controls the transmission of data to Dot Matrix Printer 4 (FIG. 1) by establishing the timing and data format. FIG. 12 presents the timing diagram illustrating an exemplary pattern of signals generated by the circuit in FIG. 11. Consequently, the two figures should be considered together in developing an understanding of interface between Financial Terminal 2 (FIG. 1) and Dot Matrix Printer 4. Again, reference is made to Table I for a definition of the functional contributions of the signals on lines WRB, BCPO, JSDO and JWRSB.

The transmission signals to Dot Matrix Printer 4 (FIG. 1) begins with a change in the signal on PLD, which signal is the result of a logic combination involving signals WRB and CS4 in gate 114 (FIG. 10). Gate 232, FFl33 and gate 136 operate in combination with gates 134 and 135 to generate the validation signal, BCPO, during the appropriate segment of each bit sequence. FFl35 also generates the SK signal to establish a bit transmission rate corresponding to one twentyfourth the CLK rate. FFl27, FFl3l, gate 128 and gate 129 detect the completion of each serial eight bit word sequence.

In operation, the transmission of data to Printer 4 commences with the concurrent presence of a signal on line WRB, and continues thereafter until a strobe signal is received on line JWRSB. Note that each group of eight data bits is actually comprised of 192 CLK pulses divided into 16 segments of 12 pulses each. The 12 pulse segments are paired for each SK signal. A validation signal on BCPO is generated for each bit, SK cycle, during the interval between CLK pulses 12 and 20. At the conclusion of the 192 CLK pulses, all BD0-BD7 data, originating in parallel format, has been shifted out to Printer 4 in serial format.

The unique timing of the validation signal BCPO within each cycle of the SK signal substantially suppresses leading and trailing edge disturbances which would otherwise provide erroneous bit data to the printer.

With an understanding of the operations performed by Interface Controller 3 (FIG. 1) at hand, the ensuing development will focus on the unique implementation of D-type FFs to create modulo X counters of the type illustrated in FIGS. 6, 13 and 14. Note that X is numerically defined by the inequality 2.sup.n-1 <.times..ltoreq.2.sup.n, where n is the number of FF stages. Initially, the modulo 8 counter in FIG. 6 will be described with relation to the classic Johnson counter. Thereafter, the modulo 12 counter in FIG. 13 will be developed and the design description then extended to the modulo 16 counter in FIG. 14. In terms of the function shown in FIG. 2, the counters perform the division operations attributed to blocks 27, 28 and 33.

It is no doubt clear from the foregoing structural arrangements and operations that synchronism of the data and control signals is crucial to the proper operation of the composite system. Inherently, this requires that any frequency dividers utilized within Interface Controller 3 (FIG. 1) not introduce significant skewing of signals between successive counter stages or exhibit spurious intermediate count signals in the course of accumulating count patterns. For these and other reasons, conventional ripple type counters configured with J-K type FFs are inherently unsatisfactory for the synchronous form of operation presently sought. Though compensating circuits are available, the additional complexity is clearly not preferred. Furthermore, such compensating circuits often complicate the synchronous starting requirement or increase the likelihood of a race condition in the asynchronous feedback logic utilized.

To satisfy these ends, the present invention provides a modulo 8 counter according to structure depicted in FIG. 6 and operational sequence defined by the binary data pattern presented in Table IX. The clocking signal on line B1RCLD0 is generated by Mag Stripe Reader 5 (FIG. 1) and is coupled to Interface Circuit 8 on line RCLB (FIG. 5).

The modulo 8 counter illustrated in FIG. 6 is structurally similar to the classic Johnson counter. However, the present arrangement not only maintains the clock-synchronized entry of data, at the D inputs of all FF stages, but provides multiple, logically controlled feedback loops to generate modulos in numerical values other than steps of 2.sup.n. The binary sequence in Table IX shows that the embodying modulo 8 counter shifts through a sequence of eight unique states and generates an output signal on line Q.sub.6 from gate 77 with each decimal count of 6. Gates 74 and 76 provide steering logic in feedback loops for D-type FFs 69, 71, 72 and 73.

The modulo 12 and 16 counters shown in respective FIGS. 13 and 14 further illustrate the use of D-type FFs to create synchronous counters of differing modulos.

Consider the modulo 12 counter in FIG. 13 first. Note that the modulo 12 counter includes four FF stages, devices 138, 139, 141 and 142, clocked by inverting amplifier 137. The counter is enabled by way of the signal on line BTB, which is coupled into gates 156, 157, 158 and 159 of the feedback loop. As embodied, the output from the modulo 12 counter is further synchronized in gate 161 with the clock signal on line CLK to generate the output signal on line BRC.

The structure in FIG. 13 illustrates a further advantage over the classic Johnson counter. Whereas the Johnson counter is limited to a count of 2n, for n FFs, the present configuration, with only four D-type FFs, is capable of counting to 12.

Table X provides a tabulation of the binary states and equivalent decimal counts as the FFs are incremented through the modulo 12 cycle. The feedback signals that generate the sequence of binary states are created in the logic blocks at the right in FIG. 13. For instance, the signal on DlA is generated by logic gate 156. The signal on line DlB is defined by Exclusive OR gate 154 and logic gate 157.

The logic necessary to generate DlC is more complex. Considering Table X and FIG. 13 together, note that gate 152 generates a binary "1" state with decimal number 3, which state then remains by action of QlC on gate 151 until both QlA and QlB become binary "1." Then, the output of gate 149 changes to binary "0". With this logic organization, gates 153 and 159 remain at binary "1" for the decimal numbers 3-6.

The signal on line DlD is generated using a similar combination of logic gates. Namely, the binary "1" output condition is first generated by gate 147, then held by the QlD input to gate 146 until disabled by gate 144. Together, gates 146, 147 and 148 generate a binary "1" for the group of decimal numbers 7-10.

The modulo 16 counter depicted in FIG. 14 utilizes an architecture similar to the modulo 12 counter in FIG. 13. FFs 162, 163, 164 and 166 are again D-type FFs whose output states are sequentially modified by the steering logic in the feedback loop. The signal on line CLRSHFT, generated by FFl3l in FIG. 11, resets the counter. Gate 178 ensures that the counter output signal on SHIFT 15 is fully synchronized to the clocking signal on BRC.

The organization of the feedback logic for the modulo 16 counter is clearly depicted in FIG. 14. For FF 166, the inverse output QA is coupled directly back into the "D" input. The input of FFl64 is defined by the output Exclusive OR gate 177. Gates 172, 173, 174 and 176 together define the input to FF 163, while gates 167, 168, 169 and 171 do likewise for FF 162.

It is no doubt apparent to one skilled in the art that the above-described embodiment illustrates merely one of many potential arrangements by which the invention may be practiced. Consequently, the embodiment and its various features serve only as examples of the full scope and spirit of the invention as now claimed.