Boost Word-Line Clock and Decoder-Driver Circuits in Semiconductor Memories

1. Field of the Invention

The present invention relates to voltage boosting and decoder circuits, and more particularly to semiconductor clock and decoder-driver circuits for boosting word-line voltage in a random access memory.

2. Description of Prior Art

The present invention relates to a voltage boosting word-line clock circuit including a fast decoder.

Voltage boosting circuits are described in the prior art in various configurations for a variety of purposes.

U.S. Pat. No. 4,061,929 issued Dec. 6, 1977 to Asano entitled CIRCUIT FOR OBTAINING DC VOLTAGE HIGHER THAN POWER SOURCE VOLTAGE describes a voltage boosting circuit which comprises a plurality of units connected in sequence and each composed of a condenser and a plurality of MOS-FETs without any transformer or diode.

U.S. Pat. No. 4,029,973 issued June 14, 1977 to Kobayashi et al entitled VOLTAGE BOOSTER CIRCUIT USING LEVEL SHIFTER COMPOSED OF TWO COMPLEMENTARY MIS CIRCUITS discloses an improvement for a voltage booster circuit. The improvement lies in the use of MISFETs as switching means in a level converting circuit constructed in a complementary MIS semiconductor integrated circuit and therefore the voltage loss due to the conventional switching means can be prevented.

In U.S. Pat. No. 4,216,390 issued Aug. 5, 1980 to Stewart entitled LEVEL SHIFT CIRCUIT a gating means, biased to pass current only during signal transitions, transfers binary signals from an input signal source to a latch circuit when the signal source and the latch are operated at similar voltages. Following data transfer, the operating voltage across the latch is increased. The voltage levels of the latch output signals are correspondingly increased but the state to which the latch was set is maintained and there is no steady state current conduction through the gating means.

In U.S. Pat. No. 4,045,691 issued Aug. 30, 1977 to Asano, also entitled LEVEL SHIFT CIRCUIT, a level shift circuit is disclosed including an inverter connected to a first voltage supply source and supplied with an input pulse. A condenser and a directional switching element are connected in series between the output point of the inverter and one potential point of the first voltage supply source. The input of a first MOS-FET is connected to the output of the inverter while the input of a second MOS-FET is connected to a connection point between the condenser and the directional switching element. The source of the first MOS-FET is connected to a common terminal of first and second voltage supply sources while the source of the second MOS-FET is connected to the other terminal of the second voltage supply source. An output voltage is generated between a common connecting point of the the drains of the first and second MOS-FETs and one potential point of the second voltage supply source.

Circuits for generating pulsating potentials and voltage levels outside the range of, and/or of greater magnitude than, the operating potential applied to the circuits are described in U.S. Pat. No. 4,000,412 issued Dec. 28, 1976 to Rosenthal et al entitled VOLTAGE AMPLITUDE MULTIPLYING CIRCUITS. Each circuit includes first and second transistors for applying a first voltage to one plate of a capacitor and a second voltage to the other plate of the capacitor, during one time interval. During a subsequent time interval, the first and second transistors are turned off and a third transistor applies the second potential to the one plate of the capacitor. The change in the potential at the one plate of the capacitor is coupled to the other plate of the capacitor at which is produced an output potential outside the range of the first and second voltages. The potential difference between the first voltage and the output potential difference is greater in amplitude than the potential difference between the first and second voltages. The circuit may also include means alternately applying the first voltage and then the output potential to an output point for generating pulsating signals of greater amplitude than the magnitude of the applied potential. The outputs of two or more circuits may be combined to produce direct current (d.c.) levels. Also included are circuits which operate from a pulsating source of operating potential.

Other references in the general field of voltage or level boosting include the following U.S. Patents:

U.S. Pat. No. 3,999,081 by T. Nakajima entitled CLOCK-CONTROLLED GATE CIRCUIT issued Dec. 21, 1976;

U.S. Pat. No. 3,982,138 by Luisi et al entitled HIGH SPEED-LOW COST, CLOCK CONTROLLED CMOS LOGIC IMPLEMENTATION issued Sept. 21, 1976;

U.S. Pat. No. 3,947,829 by Y. Suzuki entitled LOGICAL CIRCUIT APPARATUS issued Mar. 30, 1976;

U.S. Pat. No. 3,943,377 by Y. Suzuki entitled LOGIC CIRCUIT ARRANGEMENT EMPLOYING INSULATED GATE FIELD EFFECT TRANSISTORS issued Mar. 9, 1976;

U.S. Pat. No. 3,852,625 by M. Kubo entitled SEMICONDUCTOR CIRCUIT issued Dec. 3, 1974;

U.S. Pat. No. 3,801,831 by J. S. Dame entitled VOLTAGE LEVEL SHIFTING CIRCUIT issued Apr. 2, 1974.

A variety of decoder circuits for semiconductor memories are described in the prior art.

In U.S. Pat. No. 4,309,629 issued Jan. 5, 1982 to Kamuro, entitled MOS TRANSISTOR DECODER CIRCUIT, an MOS transistor decoder circuit is disclosed including a plurality of MOS transistors, a load element, and at least one additional MOS transistor connected to the plurality of MOS transistors and the load element for selecting either of two output terminals for the plurality of MOS transistors, through which decoded output signals are developed. The two additional MOS transistors connected to the two output terminals have normal and complement bit signals, respectively.

In U.S. Pat. No. 4,264,828 issued Apr. 28, 1981 to Perlegos et al, entitled MOS STATIC DECODING CIRCUIT, a metal-oxide-semiconductor static decoding circuit for selecting an addressed line in a high density memory array, or the like, is disclosed. The circuit is laid-out along array lines where the lines have a given pitch. Three levels of decoding are employed. The highest level permits the pulling-up of a common node in the second level decoder. The third level of decoding selects one of a plurality of array lines coupled to this node. Zero threshold voltage MOS devices are employed for coupling the first and third decoders to the second decoder.

In U.S. Pat. No. 4,259,731 issued Mar. 31, 1981 to Moench, entitled QUIET ROW SELECTION CIRCUITRY, there is provided a quiet row select circuit for holding unselected word-lines or row select lines in a memory array at a predetermined voltage potential.

Transistors are used to couple each row select line to the predetermined voltage potential. The adjacent row select lines of at least one of the adjacent select lines is always coupled to the predetermined voltage when in an unselected state. A transistor is also used to couple each of the adjacent row select lines together and this transistor is enabled whenever the adjacent row select lines are nonselected so that both row select lines are coupled together to the predetermined voltage level.

In another reference of Moench, U.S. Pat. No. 4,200,917 issued Apr. 29, 1980, entitled QUIET COLUMN DECODER, a decoder is provided for semiconductor memory systems which prevents glitches from being coupled into the silicon substrate during the period of time that the sense amplifiers are sensing data on the bit sense lines. The quiet column decoder has double clock NOR gates which allows the address lines to be continuous non-multiplexed lines. The double clocked NOR gate has two transistors for precharging a first and a second node within the NOR gate. Another transistor is coupled between the second node and a voltage reference terminal to serve as an enabling device for the NOR gate. The first node of the NOR gate serves as an output for the column decoder.

In U.S. Pat. No. 4,429,374 issued Jan. 31, 1984 to Tanimura, entitled MEMORY ARRAY ADDRESSING, an address decoder for one memory axis is disclosed which comprises NAND circuits while the address decoder for the other axis comprises NOR circuits.

A semiconductor memory circuit device comprises at least first and second decoder circuits. The first decoder circuit is so constructed as to receive at least partial address signals among address signals of a plurality of bits and to provide decoded signals of the partial address signals as intermediate signals. The second decoder circuit is so constructed as to receive the intermediate signals, to thereby provide signals for selecting from among a plurality of memory circuits a memory circuit determined by the address signals of the plurality of bits.

A publication entitled "CMOS Decoder Circuit" by L. M. Terman, at page 2135 of Vol. 25, No. 4 September 1982 of the IBM Technical Disclosure Bulletin relates to improvements in CMOS decoder circuits, and particularly to a decoder circuit which does not dissipate DC power. The decoder is followed with two branches with CMOS drivers for word-lines.

In Vol. 18, No. 12, May 1976 of the IBM Technical Disclosure Bulletin, G. H. Parikh in a publication entitled "High Speed FET Decoder" at page 3955 describes a field-effect transistor decoder circuit which allows improved speed of decoding FET random-access memories, by reducing the capacitance required to be discharged in an unselected decoder. The speed is further increased by reducing the capacitance of the nodes to be discharged wherein isolation transistor devices are provided to isolate the capacitance on word-line voltage nodes to allow bootstrapping to occur if a node has not been discharged.

Other related prior art includes the following references:

U.S. Pat. No. 4,194,130 to Moench issued Mar. 18, 1980, entitled DIGITAL PREDECODING SYSTEM;

U.S. Pat. No. 4,433,257 to Kinoshita issued Feb. 21, 1984, entitled VOLTAGE SUPPLY FOR OPERATING A PLURALITY OF CHANGING TRANSISTORS IN A MANNER WHICH REDUCES MINORITY CARRIER DISRUPTION OF ADJACENT MEMORY CELLS;

U.S. Pat. No. 4,156,938 to Proebsting et al issued May 29, 1979, entitled MOSFET MEMORY CHIP WITH SINGLE DECODER AND BI-LEVEL INTERCONNECT LINES;

U.S. Pat. No. 4,344,005 to Stewart issued Aug. 10, 1982, entitled POWER GATED DECODING.

The prior art listed above is representative of the state of the art prior to the present invention, and does not anticipate or make obvious the inventive features described herein.

An object of the present invention is to provide an improved clock circuit for boosting word-line voltage in a random access memory.

Another object of the present invention is to provide an improved clock circuit for boosting word-line voltage using substrate bias in addition to the supply voltage.

A further object of the present invention is to provide an improved CMOS clock circuit for boosting word-line voltage in a DRAM.

Still another object of the present invention is to provide a boosting word-line clock in CMOS DRAM including a fast decoder circuit using a NMOS device pass-gate device as decoder driver.

A further object of the present invention is to provide improved decoders for a boosting word-line clock using PMOS transistors to isolate a NMOS pass-gate device node from a decoder node.

The foregoing and other objects, features and advantages of the invention will be apparent from the following more particular description of the invention as illustrated in the accompanying drawings.

FIG. 1 is a schematic diagram of an embodiment of a word-line clock generator circuit according to the principles of the present invention.

FIGS. 2 and 3 are illustrations of waveforms at selected points in the circuit of FIG. 1 which are useful in describing its mode of operation.

FIG. 4 is a schematic diagram of a decoder to be connected in combination with the word-line clock generator of FIG. 1 according to the principles of the present invention.

FIGS. 5 and 6 are illustrations of waveforms at selected points on the circuit of FIG. 4 which are useful in describing its mode of operation.

In many NMOS semiconductor memories such as dynamic random access memories (DRAM's) the word-line voltage is boosted above the supply voltage VDD so that full signal can be stored in or read from the storage cell without threshold voltage loss. In available CMOS semiconductor memories (DRAM's) N-well technology is used and a PMOS transistor is chosen as an access transistor of the memory cell to reduce soft error rates due to radiation and minority carrier injection from peripheral circuits. Therefore, the selected word-line level changes, for example, from a nominal 5 to 0 V and if the word-line signal is not boosted, the charge storage suffers a PMOS threshold voltage loss. For example, if VDD=4.5 V, threshold voltage VT of PMOS=1.6 V, the actual stored voltage is only 2.9 V. By including the leakage effect, the signal can be reduced to less than 2.5 V. Although such small signal can still be tolerated for 64 K DRAM using very large storage capacitor, it becomes very undesirable for higher density chip. Also, when the chip density increases up to 1 megabits and/or the supply voltage scales down below the standard 5 V, because the storage capacitor area has to be limited below a certain value to maintain reasonable chip size, the threshold voltage loss during the signal restoring is hardly tolerated. Therefore, the boost word-line circuit is an important element of the system.

The present invention provides a CMOS boost word-line clock circuit which can be used for CMOS DRAM's with substrate bias in addition to VDD supply. Simple CMOS inverters are used for the word-line boost and the possible voltage overshoot, which usually occurs because of capacitor two-way boost, can be completely eliminated. Also, the circuit can be triggered by a single clock.

The present invention also provides a high performance decoder circuit in combination with the aforesaid CMOS boost word-line clock circuit, such decoder using NMOS pass-gate in the decoder driver and providing fast word-line boosting. The timing between the decoder and the word-line clock activation is not crucial.

In order to boost the word-line below 0 V, a negative substrate bias is preferred. It avoids the junction forward-biasing due to voltage undershoot below 0 V at NMOS source or drain, thus simplifying the design and speeding up the word-line clock pull-down when compared to the word-line boost clock circuit without using the substrate bias. Also, by using the negative substrate bias, a fast decoder can be used to pass the boost word-line clock onto the word-line. In addition, the substrate bias gives less substrate sensitivity of NMOS transistors and smaller junction capacitances, both of which speed up the circuit performance. Also, one problem on designing CMOS boost circuits is that the PMOS source or drain cannot tolerate voltage overshoots above VDD+0.6 V. A voltage overshoot will forward-bias the P.sup.30 N junctions to cause carrier injection, thus inducing either malfunction of the dynamic circuits and storage charge or latch-up. However, since a boost capacitor is used between the output of the word-line clock circuit and the output of an inverter used to boost the word-line clock, the unavoidable two-way boost occurring between these two outputs can easily cause overshoot. The circuit of the present invention eliminates such an overshoot under two-way boost.

An embodiment of a word-line clock generator is shown in FIG. 1. The clock generator is responsive to a plurality of system clock signals which are designated .PHI..sub.B, .PHI..sub.C, .PHI..sub.D and .PHI..sup.40 .sub.RAS. These signals will be described more particularly hereinafter.

In FIG. 1, block 11 is a NOR gate which sums the two clock signals .PHI..sub.B and .PHI..sup.41 .sub.RAS. Blocks 13 and 15 include a chain of delay circuits. Block 17 is a delay circuit for clock signal .PHI..sub.B. Blocks 19 and 21 also include chains of delay circuits. Block 23 functions as a gate wherein clock signal .PHI..sub.C is stored at device Q.sub.24 and is gated to delay block 19 when a signal is applied to device Q.sub.23.

Block 25 is a NOR circuit for delayed signal .PHI..sub.C from block 15 and delayed signal .PHI..sub.D from block 21. Block 27 is a NAND circuit for the output of NOR circuit 25 and an external boost output signal (from block 33). Block 29 is an internal boost circuit for node 22 to control the device Q.sub.3. Block 31 is a clock driver means and block 33 is an external boosting means. Block 35 performs a NAND function for the delayed .PHI..sub.D signal from block 21 and the delayed .PHI..sub.B signal from block 17.

The specific circuitry for the embodiment of the word-line clock generator is shown within the blocks in FIG. 1. The output waveform signal .PHI..sub.x at the node 10 can be fed into the individual word-line through a selected decoder driver such as will be later described relative to FIG. 4. Clock signal .PHI..sub.B which is applied at node 12 is used to initiate the pull-down of the output signal at the front phase of circuit operation and to reset the output signal at the back phase. Clock signal .PHI..sup.41 .sub.RAS is generally used as row circuit clock in DRAM's for faster reset of the circuits. Clock signal .PHI..sub.C is used to preset the circuit ready for boosting, and clock signal .PHI..sub.D is used to trigger boosting the output voltage below the ground. Clock signal .PHI..sub.C is generated from the clock signal .PHI..sub.B through delay circuits from node 12 to node 14, and the clock signal .PHI..sub.D is generated from the clock signal .PHI..sub.C by delay circuits through node 14, node 16, and node 18 to node 20. Transistor devices Q.sub.1, Q.sub.2 and Q.sub.3 form the output stage, in which Q.sub.1 and Q.sub.2 are connected as complementary pairs to avoid dc current. The PMOS transistor device Q.sub.4 is used as pass-gate between the nodes 22 and 24 and, by discharging node 16 from high to low voltage, the voltage at node 22 can be coupled down below ground sufficiently to turn off device Q.sub.3 through a coupling capacitor 26. Then, by discharging node 28, the output voltage at node 10 is boosted below ground through the coupling capacitor 30. The design key point is to achieve a boost word-line clock without causing any overshoot at PMOS source/drain. Undershoot at NMOS source/drain can be tolerated as long as it is of the same magnitude as substrate bias voltage.

The operation of the circuit illustrated in FIG. 1 is described in the following with reference to the waveforms illustrated in FIGS. 2 and 3. For purposes of explanation, VDD is 5 volts and the substrate bias is -2.5 volts. Before activation, the clock signals .PHI..sub.B, .PHI..sup.".sub.RAS, and the output .PHI..sub.x are high (at 5 volts) and .PHI..sub.C, .PHI..sub.D, are low (at zero volts). The voltages at nodes 28 and 16 are low and the voltage at the node 22 is high. Activation starts by first pulling down signal .PHI..sup.".sub.RAS, and then signal .PHI..sub.B, turning on device Q.sub.1 such that the node 10 is discharged to ground through devices Q.sub.1 and Q.sub.3. Meanwhile, the pulling down of signal .PHI..sub.B also triggers the pull-up of node 28 to 5 volts through circuits from node 12, node 32, and node 34 to node 28. Since node 10 has been discharged, no overshoot above 5 V can occur by coupling through the capacitor 30 when node 28 is pulled up to 5 V. After a certain time delay for allowing complete discharge of node 10, the clock signal .PHI..sub.C is pulled up, discharging nodes 24 and 22. Afterwards, node 16 is charged up, which gives a voltage coupling at node 22 through the capacitor 26 but certainly not an overshoot above 5 volts because node 22 has been discharged and the NMOS capacitor 26 is not fully turned on. The rise of node 16 also turns on device Q.sub.23 to discharge node 18 and subsequently pulling up the clock signal .PHI..sub.D. The rise of clock signal .PHI..sub.D first pulls down the node 16, which boosts the node 22 below ground through capacitor 26, completely turning off device Q.sub.3. Then the node 28 is pulled down to boost the output node 10 below ground through the capacitor 30. To reset the circuit, the clock signal .PHI..sup.".sub.RAS is pulled up to charge the output .PHI..sub.x to 5 volts and then signal .PHI..sub.B is reset to 5 volts and both signals .PHI..sub.C and .PHI..sub.D are reset to ground. Node 22 is charged to 5 volts. Since both nodes 28 and 16 remain low, no overshoot due to capacitor two-way boost occurs.

What has been described is a new CMOS boost word-line clock circuit which can be used for CMOS technology using substrate bias in addition to VDD supply.

In the new CMOS boost word-line clock circuit, only CMOS inverters are used, but no overshoot due to capacitor two-way boost can occur so that the possible junction forward-biasing is completely eliminated. Furthermore, the new CMOS boost word-line clock circuit provides simple timing because the entire circuit operation can be triggered by a single clock .PHI..sub.B. (.PHI..sup.".sub.RAS is used only for resetting the boost word-line clock circuit in a right time sequence related to other clock circuits used in the entire memory circuits.)

A novel high-speed decoder circuit is also provided in combination with the CMOS boost word-line clock circuit with negative substrate bias described hereinabove which uses NMOS pass-gate in the decoder driver and gives fast word-line boosting. Also, the timing between decoder set and word-line clock activation is not crucial. The circuit is especially important for high-performance CMOS DRAM technology.

The novel high-speed decoder circuitry is shown in FIG. 4. The decoder includes block 37 which specifically performs the decoding function. Blocks 39 and 41 are the decoder driver means which are connected to the word-lines WL1 and WL2. Devices Q.sub.76 and Q.sub.78 function as decoupling devices between the decoding means 37 and the driver means 39 and 41. Devices 84 and 86 are word-line pass gate devices. Devices Q.sub.88, Q.sub.92, Q.sub.90 and Q.sub.94 function as active clamp devices and devices Q.sub.96 and Q.sub.98 function as word-line precharge devices. In FIG. 4, it is assumed that the well is biased at 5 V and substrate at -2.5 V. Transistors Q.sub.70, Q.sub.72 and Q.sub.74 are parts of a static NOR decoder. The node Q.sub.76 is charged up from 0 to 5 V in the selected one and remains 0 V in other unselected decoders. .PHI..sub.x1 and .PHI..sub.x2 are two word-line boosting clocks generated from word-line boosting clock circuitry described above. Q.sub.76 and Q.sub.78 are used to allow nodes 80 and 82 floating in unselected drivers such that they can be coupled down by word-line clocks. Q.sub.84 and Q.sub.86 are the pass-gates between word-line clocks and word-lines. Q.sub.88, Q.sub.90, Q.sub.92, Q.sub.94 are active word-line clamping devices during RAM active operation and Q.sub.96 and Q.sub.98 are word-line precharge devices. WL1 and WL2 represent two adjacent word-lines.

The circuit functions in the following with reference to the simulated waveforms in FIGS. 4 and 5. For a selected decoder (represented by the waveforms in FIG. 4), the node 76 is set to high voltage. This high voltage at node 76 can quickly charge up the nodes 80 and 82 through PMOS transistors Q.sub.76 and Q.sub.78. Assuming the word-line clock .PHI..sub.x1 is pulled down and .PHI..sub.x2 remains high, WL1 can be quickly discharged through NMOS Q.sub.84 and no slow source-follower effect in prior art decoder-driver circuits occurs. WL2 is firmly clamped at 5 V (Q.sub.94 is an active clamping device used to reduce noises on WL2 due to WL1 coupling). Since the voltage at node 80 does not have to be boosted for the selected decoder, the timing between the decoder set and word-line clock activation is not crucial. In prior art decoder drivers, the word-line clock can be activated only after decoder has been selected and this timing constraint slows down the word-line boost. At reset, fast .PHI..sub.R clock reset the decoder to avoid voltage overshoot at node 80 before charging up the word-line. For unselected decoders (represented by the waveforms in FIG. 5), the node 76 is at 0 V. The nodes 80 and 82 are floating at V.sub.TP, where V.sub.TP is the threshold voltage of PMOS Q.sub.76 and Q.sub.78, respectively. The pulled-down .PHI..sub.x clock self-boosts down the voltage at node 80 through capacitance C.sub.2out, which cuts off Q.sub.84 and further turns on Q.sub.88 to clamp the WL1. WL2 is also clamped through Q.sub.90 and Q.sub.94.

The high speed decoder circuit of FIG. 4 uses an NMOS transistor as transfer device between boosted word-line clock and word-line. Compared to the prior art boost word-line clock and decoder circuits, the word-line pull-down has fast speed because of avoiding slow source-follower effect. Also, the voltage at the pass-transistor gate does not have to be boosted below the boosted word-line level, which relaxes the requirement of having high P.sup.+ N junction breakdown voltage and high dielectric strength of the gate oxide. In addition, the non-crucial timing between decoder set and word-line clock activation gives faster speed. The decoder driver circuit uses PMOS transistors Q.sub.76 and Q.sub.78 to isolate nodes 80 and 82 from decoder node 76, thus allowing self-cut-off pass transistors in unselected decoders.

The above circuits are made in an assumed n-well CMOS technology and assumed pull-down word-line waveforms for PMOS memory cell array. For a P-well CMOS technology, the NMOS transistors are made in many separate P-wells which are biased at ground. The n-substrate is biased at V.sub.DD. Since only the source or drain regions of Q.sub.1 and Q.sub.3 in FIG. 1 as well as Q.sub.84 and Q.sub.86 in FIG. 4 have voltages at the negative boosted word-line level, these devices can be located at P-wells which are biased at a negative voltage supplied by an on-chip bias generator to avoid junction forward-biasing due to voltage undershoot. Therefore, the general principles disclosed in the above circuits can be widely applied to different technologies and also to pull-up/pull-down word-line waveforms.