Semiconductor Memory Device

This invention relates to a semiconductor memory device in which memory cells are allocated with successive addresses.

A conventional semiconductor memory device has a structure such as shown in, for example, FIG. 1. In the memory device shown in FIG. 1, row decoder 11 selects one of a plurality of row lines 12 according to a row address signal. Column decoder 13 selects one of a plurality of selecting lines 14 for selecting one of a plurality of column lines 16 according to a column address signal. When one selecting line 14 is selected, transistor 15, whose gate is connected to the selected selecting line 14, is turned on and column line 16, to which the selected transistor 15 is provided, is selected. When one row line 12 and one column line 16 are selected, memory cell 18, which is located at the cross point of the selected row line 12 and column line 16, is selected. Data is then read out of the selected memory cell 18.

In the conventional semiconductor memory device, row lines 12 are made of polysilicon. This gives large resistances to row lines 12. Furthermore, a plurality of memory cells 18 are connected to row lines 12, giving large capacitances to row lines 12 and thereby, in combination with the resistance factor, providing row lines 12 with heavy loads. Consequently, the time period required from when a row address signal is changed to when data is read out of the selected memory cell 18 to a selected column line 16, is significantly longer than the time period required from when a column address signal is changed to when the column line 16 is selected, so much so, in fact, that the time taken by a sense amplifier for sensing data is unsatisfactorily long. This is particularly so in a semiconductor memory device in which data is successively read out of memory cells which are allocated with successive addresses.

This invention has been carried out in light of the above mentioned circumstances and has, as its object, the provision of a semiconductor memory device in which the time required for data sensing is shortened.

According to the invention, there is provided a semiconductor memory device comprising a plurality of row lines; a plurality of column lines; an array of a plurality of memory cells provided at cross points of said row and column lines, said memory cells being allocated with successive addresses, and said memory cells, whose addresses are continuous being connected to said column lines differently from one another; row decoder means for receiving a signal of row address, for selecting a row line designated by said row address and connected to a memory cell allocated for an address designated by said row address and a column address, as well as for selecting at least one other row line to which a memory cell allocated for an address continuous to said designated address is connected; column decoder means for receiving a signal of column address, for selecting a column line designated by said column address and connected to said memory cell allocated for said designated address; and sense means connected to said column lines for detecting data stored in said selected memory cell allocated for said designated address.

FIG. 1 shows a conventional semiconductor memory device;

FIG. 2 shows a semiconductor memory device of an embodiment according to the invention;

FIG. 3 is a truth table, applied to the memory device of FIG. 2, which shows the relationship between input address signals, selected memory cells and selected row lines; and

FIG. 4 shows a semiconductor memory device of another embodiment according to the invention.

In the semiconductor memory device shown in FIG. 2, row decoder 111 receives and decodes a row address signal A0-A4. Row lines 112.sub.1, 112.sub.2, 112.sub.3, 112.sub.4, 112.sub.5 and 112.sub.6 are connected to row decoder 111. Only six row lines are shown for simplicity of illustration, more row lines may actually be provided. Row lines 112.sub.1, 112.sub.3 and 112.sub.5 are provided at the right part of row decoder 111, when the row line pattern is seen in FIG. 2. Similarly, row lines 112.sub.2, 112.sub.4 and 112.sub.6 are provided at the left part of row decoder 111, when the row line pattern is seen in FIG. 2.

The counterpart of the row decoder, the column decoder 113, receives and decodes a column address signal A0 and A1.

Only four column lines, the provided column lines 116.sub.0, 116.sub.1, 116.sub.2 and 116.sub.3, are shown, for simplicity of illustration. More column lines may actually be provided. Column lines 116.sub.0 and 116.sub.1 are provided at the right part of column decoder 113, when the column line pattern is seen in FIG. 2. Column lines 116.sub.0 and 116.sub.1 cross over row lines 112.sub.1, 112.sub.3 and 112.sub.5. Column lines 116.sub.2 and 116.sub.3 are provided at the left part of column decoder 113, when the column line pattern is seen in FIG. 2. Column lines 116.sub.2 and 116.sub.3 cross over row lines 112.sub.2, 112.sub.4 and 112.sub.6. Column lines 116.sub.0 and 116.sub.1, 116.sub.2 and 116.sub.3 are connected to sense amplifier 119 through transistors 115.sub.0, 115.sub.1, 115.sub.2 and 115.sub.3, respectively. Selecting lines 114.sub.0, 114.sub.1, 114.sub.2 and 114.sub.3, for selecting column lines 116.sub.0, 116.sub. 1, 116.sub.2 and 116.sub.3, are provided, said selecting lines 114.sub.0, 114.sub.1, 114.sub.2 and 114.sub.3 being connected between column decoder 113 and the gates of transistors 115.sub.0, 115.sub.1, 115.sub.2 and 115.sub.3, respectively. Memory cells 118.sub.1 and 118.sub.2 are provided at the cross points of row line 112.sub.1 and column lines 116.sub.0 and 116.sub.1, respectively. Memory cells 118.sub.3 and 118.sub.4 are provided at the cross points of row line 112.sub.2 and column lines 116.sub.2 and 116.sub.3, respectively. Memory cells 118.sub.5 and 118.sub.6 are provided at the cross points of row line 112.sub.3 and column lines 116.sub.0 and 116.sub.1, respectively. Memory cells 118.sub.7 and 118.sub.8 are provided at the cross points of row line 112.sub.4 and column lines 116.sub.2 and 116.sub.3, respectively. Memory cells 118.sub.9 and 118.sub.10 are provided at the cross points of row line 112.sub.5 and column lines 116.sub.0 and 116.sub.1, respectively. Memory cells 118.sub.11 and 118.sub.12 are provided at the cross points of row line 112.sub.6 and column lines 116.sub.2 and 116.sub.3, respectively. Only twelve memory cells are shown for simplicity of illustration, more memory cells may actually be provided. Memory cells 118.sub.1, 118.sub.2, 118.sub.3, . . . , 118.sub.12 are allocated for successive addresses 1, 2, 3, . . . , 12. The suffixes 1, 2, 3, . . . , 12, attached to memory cells 118, denote the successive addresses allocated to memory cells 118. Memory cells whose addresses are continuous are connected to column lines differently from one another.

When row decoder 111 receives input address signal A0-A4, which is also a row address signal, row decoder 111 selects not only a row line designated by the row address signal A0-A4, to which a memory cell to be selected by the input address signal is connected, but also row lines to which are connected memory cells allocated with addresses both preceding and succeeding the address allocated to the selected memory cell.

The preceding and succeeding addresses are younger and elder, by one, than the address allocated to the selected memory cell.

Assume now that row decoder 111 receives input address signal A0-A4, which is also a row address signal, for designating the memory cell 118.sub.6 allocated for address 6 and inputted when the row address signal A0-A4 designates row line 112.sub.3, and the column address signal A0, A1 designates column line 116.sub.1, to both of which memory cell 118.sub.6 is connected. Then, in addition to selecting now line 112.sub.3, to which memory cell 118.sub.6, with address 6, is connected row decoder 111 also selects row lines 112.sub.3 and 112.sub.4 to which memory cells 118.sub.5 and 118.sub.7, with addresses 5 and 7, respectively, are connected, preceding and succeeding address 6, allotted to the selected memory cell 118.sub.6. Memory cells 118.sub.5 and 118.sub.6 are both connected to row line 112.sub.3 and, thus, row line 112.sub.3 is commonly selected for memory cells 118.sub.5 and 118.sub.6. When row line 112.sub.3 is selected, data are read out of memory cells 118.sub.5 and 118.sub.6, both connected to row line 112.sub.3, and appear on column lines 116.sub.0 and 116.sub.1. As well, data are read out of memory cells 118.sub.7 and 118.sub.8, both connected to row line 112.sub.4, and appear on column lines 116.sub.2 and 116.sub.3. Column decoder 113 selects selecting line 114.sub.1 to turn transistor 115.sub.1 on, thereby also selecting column line 116.sub.1. Therefore, memory cell 118.sub.6, which is connected to the selected row line 112.sub.3 and selected column line 116.sub.1, is selected, and data stored in the selected memory cell 118.sub.6 is sensed by sense amplifier 119.

Now, assume that input address signal A0-A4 increases to designate address 7, which is elder, by one, than address 6, designated at the preceding address cycle. In this case, row decoder 111 selects row line 112.sub.4, to which memory cell 118.sub.7, with address 7, is connected, as well as row lines 112.sub.3 and 112.sub.4 to which memory cells 118.sub.6 and 118.sub.8, with addresses 6 and 8, respectively, are connected, preceding and succeeding address 7, allotted to the selected memory cell 118.sub.7. Row lines 112.sub.3 and 112.sub.4 have been selected in the preceding address cycle and, thus, row lines 112.sub.3 and 112.sub.4 are continuously selected from the preceding address cycle. Therefore, data read out of memory cells 118.sub.5 and 118.sub.6, both connected to row line 112.sub.3, continue to appear on column lines 116.sub.0 and 116.sub.1 from the preceding address cycle. Similarly, data read out of memory cell 118.sub.7 and 118.sub.8, both connected to row line 112.sub.4, also continue to appear on column lines 116.sub.2 and 116.sub.3 from the preceding address cycle. Column decoder 113 selects selecting line 114.sub.2 to turn transistor 115.sub.2 on, thereby also selecting column line 116.sub.2. Therefore, memory cell 118.sub.7, which is connected to the selected row line 112.sub.3 and selected column line 116.sub.2, is selected, and data stored in the selected memory cell 118.sub.7 is sensed by sense amplifier 119.

As can be understood from the above, with the memory device, row lines 112.sub.3 and 112.sub.4, selected at the preceding address cycle, are continuously selected from the preceding address cycle to the succeeding address cycle. Consequently, data to be read out at the succeeding address cycle is read out in advance the preceding address cycle, and appears constantly on column line 116.sub.2 in the succeeding address cycle. Therefore, data appearing on column line 116.sub.2 is read out at the succeeding address cycle when only column line 116.sub.2 is selected. As a result, a time delay on data reading, which occurs due to a heavy load imposed on row lines 112.sub.1 -112.sub.6, is significantly shortened and, thus a high speed sensing of data can be provided.

Substantially the same thing can be applied to a case in which input address signal A0-A4 decreases to designate an address younger, by one, than the address designated in the preceding address cycle.

Row decoder 111 is programmed to carry the logic operation shown in the truth table of FIG. 3. As shown in the truth table, row decoder 111 selects row line 112.sub.1 when the input address signal (row address signal) A0=0, A1=0, A2=0, A3=0 and A4=0, for designating memory cell 118.sub.1, is inputted. Row decoder 111 selects row lines 112.sub.1 and 112.sub.2 when input address signal A0=1, A1=0, A2=0, A3=0 and A4=0, for designating memory cell 118.sub.2, is inputted. Row decoder 111 selects row lines 112.sub.1 and 112.sub.2 when input address signal A0=0, A1=1, A2=0, A3=0 and A4=0, for designating memory cell 118.sub.3, is inputted. Row decoder 111 selects row lines for another input address signal A0-A4 as shown in the truth table shown in FIG. 2.

A logic equation I1 for selecting row line 112.sub.1 is given from the truth table shown in FIG. 2 by

A logic equation I2 for selecting row line 112.sub.2 is given from the truth table shown in FIG. 2 by

In the memory device shown in FIG. 4, sense amplifiers 119.sub.0, 119.sub.1, 119.sub.2 and 119.sub.3 are provided to respective column lines 116.sub.0, 116.sub.1, 116.sub.2 and 116.sub.3. Sense amplifier 119.sub.0 is inserted into column line 116.sub.0 between transistor 115.sub.0 and the cross points of row lines 112.sub.1, 112.sub.3 and 112.sub.5. Sense amplifier 119.sub.1 is inserted into column line 116.sub.1 between transistor 115.sub.1 and the cross points of row lines 112.sub.1, 112.sub.3 and 112.sub.5. Sense amplifier 119.sub.2 is inserted into column line 116.sub.2 between transistor 115.sub.2 and the cross points of row lines 112.sub.2, 112.sub.4 and 112.sub.6. Sense amplifier 119.sub.3 is inserted into column line 116.sub.3 between transistor 115.sub.3 and the cross points of row lines 112.sub.2, 112.sub.4 and 112.sub.6. With this embodiment, sensing speed is increased, since the length between memory cells 118.sub.1 -118.sub.12 and sense amplifiers 119.sub.0 -119.sub.3 is shortened.

This invention is not limited to the above mentioned embodiments. Other embodiments may be considered. For example, it is not necessarily required to select row lines to which are connected the memory cells with addresses preceding and succeeding, respectively, addresses allocated to a selected memory cell. Only one memory cell allocated with the preceding or succeeding address need be selected. A memory cell allocated with the preceding address is selected when input address signal A0-A4 increases, while, a memory cell allocated with the succeeding address is selected when input address signal A0-A4 decreases. Furthermore, this invention can be applied to a memory device with a variety of bits, though the embodiments disclose only 5 bit memory devices.