IC Input Buffer Emitter Follower With Current Source Value Dependent Upon Connection Length for Equalizing Signal Delay

1. Field of the Invention

The present invention relates to a semiconductor device, and more particularly, to the improvement of a signal input portion of an emitter-coupled logic (ECL) integrated circuit.

2 Description of the Related Art

The chip area of an advanced ECL integrated circuit is often increased, and therefore, some connection lines between a plurality of input signal pads and a plurality of input signal buffers such as address buffers become long. Consequently, if the distance between an input signal pad and an emitter follower transistor used as a signal input portion is large, for example, the input capacitance of an input signal is increased due to the parasitic capacitance of a long connection therebetween, thus increasing the access time.

To avoid this, in the prior art only the emitter follower transistor of the signal input portion is in proximity to the input signal pad, while a current source of the signal input portion is left on the circuit side of the input signal buffer, thereby reducing the input capacitance for an input signal. In this case, however, if the current flowing through the emitter follower is increased, the potential fall due to the resistance of signal paths is large so that the post input stage circuits may not operate normally. Contrary to this, if the current flowing through the emitter follower is decreased, the propagation speed of the input signal level becomes large due to the parasitic capacitance, thereby reducing the access time. Thus, in this case, it is impossible to satisfy the two conditions regarding the potential fall and the propagation speed of the signal level.

An object of the present invention is to minimize the potential fall of signal level due to the resistance of the signal path in a long connection line, and to minimize the delay in the access time.

According to the present invention, a constant current source is provided in proximity to the emitter follower and is connected thereto, and a current value of the constant current source is changed in accordance with connection line length, i.e., the parasitic capacitance between the emitter follower and the input signal buffer. That is, the larger the connection line length, the greater the current value of the constant current source.

Thus, since the current flowing through the connection line between the emitter follower and the input signal buffer is greatly reduced, reduction in potential due to the connection resistance is reduced, i.e., the reduction of a signal level is lessened. Also, since the current value of the constant current source is increased when the parasitic capacitance is large, the delay in the fall of the signal level is reduced.

The present invention will be more clearly understood from the description as set forth below with reference to the accompanying drawings, wherein:

FIG. 1 is a partial layout diagram of a general semiconductor device;

FIGS. 2 and 3 are circuit diagrams showing prior art semiconductor devices;

FIG. 4 is a timing diagram showing the operation of the circuit of FIG. 3;

FIG. 5 is a circuit diagram illustrating an embodiment of the semiconductor device according to the present invention;

FIGS. 6A and 6B are circuit diagrams of the constant current sources I.sub.il of FIG. 5;

FIGS. 7A, 7B, 8A and 8B are layout diagrams of FIGS. 6A and 6B; and

FIG. 9 is a circuit diagram illustrating a second embodiment of the semiconductor device according to the present invention.

In FIG. 1, which illustrates a general semiconductor device such as an ECL memory device, a plurality of pads P.sub.1 through P.sub.7 are connected via connection lines or conductor L.sub.0 through L.sub.7 to a signal input portion such as address buffers BUF. As the integration of the device is advanced or increased to reduce the size of the address buffers BUF, some of the connection lines L.sub.0 through L.sub.7 become long. For example, in FIG. 1, the connection line L.sub.0 between the pad P.sub.0 and the address buffers BUF is relatively short, but the connection line L.sub.7 between the pad P.sub.7 and the address buffers BUF is very long. Note that the signal input portion includes emitter followers, diodes, current sources, and the like, other than the address buffers BUF.

The device of FIG. 1 will be explained in detail with reference to FIGS. 2 and 3.

In FIG. 2, emitter followers Q.sub.01, . . ., and Q.sub.71, diodes D.sub.01, . . ., and D.sub.71, and constant current sources I.sub.01, . . ., and I.sub.71 are linked between the pads P.sub.0, . . ., and P.sub.7, and the address buffers BUF.sub.0, . . ., and BUF.sub.7. Each of the address buffers BUF.sub.0, . . ., and BUF.sub.7 has the same configuration. For example, the address buffer BUF.sub.0 comprises two transistors Q.sub.02 and Q.sub.03, and a constant current source I.sub.02, to form a current switch. Note that the diode D.sub.01 serves as a level shift means so that the center of the input amplitude of a signal applied to the base of the transistor Q.sub.02 conforms to a reference potential V.sub.ref0 applied to the base of the transistor Q.sub.03, thereby improving the operation speed of the address buffers. For example, if the center of the input amplitude of the signal applied to the base of the transistor Q.sub.02 is too high as compared with the reference potential V.sub.ref0, i.e., if the high level of the signal applied to the base of the transistor Q.sub.02 is too high as compared with the reference potential V.sub.ref0, the change of the output signal A.sub.0 from high to low is delayed as compared with the change of the output signal A.sub.0 from low to high. This delay is reduced by the diode D.sub.0. However, note that the number of such diode stages may be increased or decreased as occasion demands. Also, V.sub.EE designates a power supply voltage such as -5 V.

In FIG. 2, the distance between the pad P.sub.1 and the emitter follower Q.sub.01 is relatively small, and accordingly, the input capacitance encountered by an address signal applied to the pad P.sub.1 is small due to the parasitic capacitance C.sub.p0 of the short connection line L.sub.0, thus reducing the access time. On the other hand, the distance between the pad P.sub.7 and the emitter follower Q.sub.171 is relatively long, and accordingly, the input capacitance of an address signal applied to the pad P.sub.7 is large due to the parasitic capacitance C.sub.P7 of the long connection line L.sub.7, thus increasing the access time.

In order to reduce the input capacitance for an address signal, in FIG. 3, the emitter followers Q.sub.01, . . ., and Q.sub.71 are provided in proximity to the pads P.sub.0, . . ., and P.sub.7, respectively, and are connected thereto. That is, in this case, the input capacitance at the post input stage of each of the pads P0 , ..., and P.sub.7 is reduced by 1/.beta. (.beta. represents the current amplification factor of the emitter follower such as Q.sub.01)

In FIG. 3, however, when the emitter current of the emitter follower Q.sub.71, i.e., the current I.sub.71 is increased, the reduction in potential due to the resistance of the connection line L.sub.7 is large since the connection L.sub.7 is long, and as a result, the signal level is greatly reduced so that the post-stage circuit which, in this case, is the address buffer BUF.sub.7 does not operate normally. Contrary to this, when the emitter current I.sub.71 of the emitter follower Q.sub.71 is small, the fall at the signal level is slow due to the parasitic capacitance C.sub.P7 as shown in FIG. 4, thereby increasing the access time.

In FIG. 5, which illustrates an embodiment of the semiconductor device according to the present invention, the constant current sources I.sub.01 through I.sub.71 are provided in proximity to the emitter followers Q.sub.01 through Q.sub.71, respectively. As a result, since a current required for driving the address buffer such as BUF.sub.0, . . ., and BUF.sub.7 is small, the current values of the constant current sources can be reduced even when the length of the connections lines L.sub.0 through L.sub.7 is large. Even in this case, however, the access time is dependent upon the length of the connection lines L.sub.0 through L.sub.7 which should be charged or discharged. Therefore, the current values of the constant current sources I.sub.01 through I.sub.71 are determined in accordance with the length of the connection lines L.sub.0 through L.sub.7 , i.e., the parasitic capacitances C.sub.P0 through C.sub.P7, respectively. That is, the ability of the emitter followers Q01 through Q.sub.71 to charge the lines are changed in accordance with the parasitic capacitances C.sub.P0 through C.sub.P7. For example, when the length of the connection line such as L.sub.0 is small, the current value of the constant current source I.sub.01 is small, and when the length of the connection line such as L.sub.7 is large, the constant current source I.sub.07 is large.

As shown in FIG. 6A, the constant current source I.sub.01 is comprised of a transistor Q.sub.R having a base to which a definite voltage V.sub.RB is applied, and a resistor R. Also, as shown in FIG. 6B, the constant current source I.sub.71 is comprised of a transistor Q.sub.R having a base to which the definite voltage V.sub.RB is applied, and five resistors R. That is, the current value of the constant current source is determined in accordance with the number of resistors R. For example, as shown in FIGS. 7A and 7B, the number of resistors R is substantially determined by the number to contacts of the resistors R. Also, as shown in FIGS. 8A and 8B, the number of resistors R can be determined by changing the connection pattern of the transistor Q.sub.IR and the resistors R.

In FIG. 5, the current values of the constant current sources I.sub.01 through I.sub.71 are changed in accordance with the parasitic capacitances C.sub.P0 through C.sub.P7, respectively. This change of the current values of the constant current sources slightly affects the base-emitter voltage V.sub.BE of the emitter followers Q.sub.01 through Q.sub.71. As a result, the high and low levels of an address signal at the base of the transistor Q.sub.02 (or Q.sub.72) are slightly changed, and accordingly, the center of the amplitude of the address signal at the base of the transistor Q.sub.02 (or Q.sub.72) is shifted from the reference potential V.sub.ref0 (or V.sub.ref7).

In FIG. 9, which illustrates another embodiment of the semiconductor device according to the present invention, the reference potential such as V.sub.ref0 is changed in accordance with the current value of the constant current source such as I.sub.01, so that the center of the amplitude of the address signal at the base of the transistor such as Q.sub.02 conforms to the reference potential such as V.sub.ref0, thereby improving the operation of the address buffers. For this purpose, the circuits on the circuit side of reference potential V.sub.ref0 through V.sub.ref7 have the same configuration as the circuits on the circuit side of the address signals. That is, transistors Q.sub.01 ' through Q.sub.71 ', diodes D.sub.01 ' through D.sub.71 ', and constant current sources I.sub.0 ' through I.sub.71 ' corresponding to the transistors Q.sub.01 through Q.sub.71, the diodes D.sub.01 through D.sub.71 and the constant current sources I.sub.01 through I.sub.71 are provided for the reference potentials V.sub.ref0 through V.sub.ref7. Also, a reference potential V.sub.R.phi. (-1.3 V) is applied to the bases of the emitter followers Q.sub.01, through Q.sub.71 '. Herem it is important that the current value of the constant current source such as I.sub.01 ' on the circuit side of the reference potential be the same as the current value of the corresponding constant current source I.sub.01 on the address signal circuit side. Thus, the fluctuation in the base-emitter voltage V.sub.BE of each of the emitter followers Q.sub.01 through Q.sub.71 is the same as the fluctuation in the base-emitter voltage V.sub.BE of each of the emitter followers Q.sub.01 ' through Q.sub.71 ', and as a result, the fluctuation in the comparison operation between the base potential of the transistor such as Q.sub.02 and the base potential of the transistor such as Q.sub.03 is eliminated.

Also, in FIG. 9, the number of diode stages such as D.sub.01 ', . . ., and D.sub.71 ' is increased or decreased as occasion demands.

Note that, in the above-mentioned embodiments, an address signal is used as an input signal. However, the present invention can be applied to various signals (external clock signals) other than address signals.

As explained above, according to the present invention, the reduction in signal level due to the long connection line can be avoided, and in addition, the reduction in access time can be avoided.