US 4,667,280 AGrant
Voltage Multiplying Rectifier
Issue Date:1987-05-19
•2 Claims
•3 Drawing Sheets
Abstract
A step-up rectifier circuit includes first and second input terminals for applying AC outputs of opposite polarities, a third input terminal connected between the first and second input terminals, a plurality of rectifier elements connected between the third input terminal and a first output terminal, a plurality of output capacitors connected in parallel to the rectifier elements, a second output terminal connected to a node between said output capacitors, a plurality of first capacitors connected between nodes between those of said rectifying elements located between the first output terminal and the second output terminal and a plurality of second capacitors connected between nodes between those of the rectifying elements which are between the second output terminal and the third input terminal, wherein the capacitance of the capacitors is defined such that the output voltages at individual output terminals can be made constant, regardless of whether other output terminals are loaded or unloaded.
Metadata
Assignee
- Kabushiki Kaisha Toshiba
Inventors
- Yoshio Takamura
- Akira Nakajima
Application Information
Application Number:US 6648533
Filing Date:1984-10-25
Priority Date:1983-12-16
Art Unit:212
Classifications
IPC:
H02M 318
Field of Search:
36332030759;60;61;1261110
Patent Drawings (3 sheets)
Description
Background of the Invention
The present invention relates to a step-up rectifier circuit and, as disclosed herein, to a step-up rectifier circuit which multiplies the input voltage and can generate different output voltages and currents at a plurality of output terminals, by using a plurality of diodes and a plurality of capacitors.
Description of the Prior Art
As is well-known in the art, a step-up rectifier circuit constructed with a plurality of diodes and capacitors usually has a high internal impedance. As a result, the step-up rectifier circuit has the defect that the output voltage varies widely with changes in load. When an output voltage is provided from an intermediate portion of the rectifier circuit, it has a very strong influence upon the voltage at another output terminal, so that it is difficult to keep the voltages at each output terminal at a constant level when the load condition varies at other terminals.
Summary of the Invention
An object of this invention is, therefore, to provide a step-up rectifier circuit in which the output voltages at individual output terminals can be made constant, regardless of the load conditions.
Another object of this invention is to provide a step-up rectifier which can provide output voltages and currents at each of a plurality of output terminals without causing a change in the output voltages and currents at the other terminals.
Additional objects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned from the practice of the invention. The objects and advantages may be realized and attained by means of the instrumentalities and combinations particularly pointed out in the appended claims.
In order to achieve the objects of the present invention as embodied and broadly disclosed herein, a step-up rectifier circuit is provided for multiplying input voltage applied to said rectifier circuit, comprising first and second input terminals for supplying AC inputs of opposite polarities, a third input terminal connected between said first and second input terminals, rectifier means provided with a plurality of rectifying elements connected in series with said third input terminal and aligned in the same direction of rectification, a plurality of series-connected output capacitors having one end connected to said third input terminal, and connected in parallel to said plurality of rectifying elements, a first output terminal connected to the other end of said series-connected output capacitors, a second output terminal connected to a node between said output capacitors, a plurality of first capacitors connected between said first and second input terminals and nodes formed between those rectifying elements located between said first output terminal and said second output terminal, and a plurality of second capacitors connected between said first and second input terminals and nodes formed between those rectifying elements located between said second output terminal and said third input terminal, wherein each capacitance (Ca) in farads of said first capacitors is defined by the following equation:
in which I.sub.1 designates the current in amperes flowing through the first output terminal; n.sub.1 designates one-half of the number of said first capacitors; f designates the frequency in Hertz of said power supply; E.sub.0 designates the voltage in volts between said first and second input terminals; E.sub.1 designates output voltage in volts between first and second output terminals.
The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate several embodiments of the invention, and together with the description, serve to explain the principles of the invention.
Brief Description of the Drawings
FIG. 1 is a circuit diagram of one embodiment of the step-up rectifier circuit constructed according to the present invention;
FIG. 2 is a circuit diagram used to explain the operation of the embodiment of the present invention; and
FIG. 3 is a circuit diagram of another embodiment of the step-up rectifier circuit constructed according to the present invention.
Description of the Preferred Embodiments
The present invention will be described in connection with two embodiments thereof, and with reference to the accompanying drawings.
In FIG. 1, AC power supply A is connected to the primary winding n.sub.1 of a transformer T. The secondary winding n.sub.2 of this transformer T is provided with a middle tap m. Two terminals a, b of the secondary winding n.sub.2 and the middle tap m of the transformer provide first to third input terminals, so that AC inputs of opposite polarities are supplied to the two terminals a, b of the secondary winding n.sub.2. The tap m, acting as the third input terminal, is grounded. A plurality of diodes D.sub.1 to D.sub.15 are connected in series between the tap m and a first output terminal P.sub.1 so that their rectification directions are identical. More specifically, the anode of diode D.sub.1 is connected to the tap m, and the cathode of diode D.sub.15 is connected to the first output terminal P.sub.1.
A plurality of capacitors C.sub.1 to C.sub.5 are connected between one side a of the secondary winding n.sub.2 of the transformer T acting as the first input terminal and predetermined nodes of the diodes D.sub.1 to D.sub.15. More specifically, the capacitors C.sub.1 and C.sub.2 are connected in series between one side a of the secondary winding n.sub.2 and the node j between diodes D.sub.5 and D.sub.6 ; and a node between the capacitors C.sub.1 and C.sub.2 is connected to the node f between diodes D.sub.2 and D.sub.3. The capacitors C.sub.3, C.sub.4 and C.sub.5 are connected in series between one side a of the secondary winding n.sub.2 and the node x between diodes D.sub.14 and D.sub.15. The node between capacitors C.sub.3 and C.sub.4 is connected to the node n between diodes D.sub.8 and D.sub.9, and the node between capacitors C.sub.4 and C.sub.5 is connected to the node u between diodes D.sub.11 and D.sub.12.
Five output capacitors C.sub.6 to C.sub.10 are connected between the anode of diode D.sub.1 and the cathode of diode D.sub.15. As shown, the node between capacitors C.sub.6 and C.sub.7 is connected to the node g between diodes D.sub.3 and D.sub.4, and the node between capacitors C.sub.7 and C.sub.8 is connected to the node k between diodes D.sub.6 and D.sub.7. The node between capacitors C.sub.8 and C.sub.9 is connected to the node s between diodes D.sub.9 and D.sub.10, and the node between capacitors C.sub.9 and C.sub.10 is connected to the node v between diodes D.sub.12 and D.sub.13.
A plurality of capacitors C.sub.11 to C.sub.15 are connected between the other side b of the secondary winding n.sub.2 of the transformer T, which acts as a second input terminal, and predetermined nodes between diodes D.sub.1 to D.sub.15. More specifically, capacitors C.sub.11 and C.sub.12 are connected in series between the other side b of the secondary winding n.sub.2 and the node h between diodes D.sub.4 and D.sub.5. The node between these capacitors C.sub.11 and C.sub.12 is connected to the node e between diodes D.sub.1 and D.sub.2. The capacitors C.sub.13, C.sub.14 and C.sub.15 are connected in series between the other side b of the secondary winding n.sub.2 and the node w between diodes D.sub.13 and D.sub.14. Of these, the node between capacitors C.sub.13 and C.sub.14 is connected to the node 1 between diodes D.sub.7 and D.sub.8, and the node between capacitors C.sub.14 and C.sub.15 is connected to the node t between diodes D.sub.10 and D.sub.11.
To provide a general explanation, the following designations are made for the construction described above. The current output from the first output terminal P.sub.1 is designated by i.sub.1 (A); the current output from a node P.sub.2 (which will be referred to as the "second output terminal P.sub.2 ") between capacitors C.sub.7 and C.sub.8 is designated by i.sub.2 (A); the number of circuit steps between the grounded portion and the second output terminal P.sub.2 (i.e., one-half of the number of capacitors connected between the nodes between rectifying elements located between the tap m and the second output terminal P.sub.2 and the first input terminal a and the second input terminal b) is designated by N.sub.2, wherein N.sub.2 =2 in FIG. 1; the number of steps between the output terminal P.sub.2 and the output terminal P.sub.1 (i.e., one-half of the number of capacitors connected between the nodes between the rectifying elements located between the output terminal P.sub.2 and P.sub.1 and the first and second input terminal a and b) is designated by N.sub.1, wherein N.sub.1 =3 in FIG. 1; the voltage between the grounded portion and the output terminal P.sub.2 is designated by E.sub.2 (V); the voltage between the output terminal P.sub.2 and the output terminal P.sub.1 is designated by E.sub.1 (V); the secondary voltage of the transformer T is designated by E.sub.O (V); and the frequency of the power supply is designated by F(=1/T) (HZ). The capacitances of the capacitors C.sub.1, C.sub.2, C.sub.6, C.sub.7, C.sub.11 and C.sub.12, constituting the circuit from the grounded portion to the output terminal P.sub.2, are designated by C.sub.b (F), and the capacitances of the capacitors C.sub.3 to C.sub.5, C.sub.8 to C.sub.10 and C.sub.13 to C.sub.15, constituting the circuit from the output terminal P.sub.2 to the output terminal P.sub.1, are designated by C.sub.a (F).
Where capacitors C.sub.3 -C.sub.5 or C.sub.13 -C.sub.15 are connected in parallel to capacitors C.sub.1, C.sub.2 or C.sub.11, C.sub.12, if this circuit is operated with a full output but zero current, i.e., under no load, the voltages E.sub.1 and E.sub.2 are expressed by the following equations:
Before the steps of deducing the above equation are explained, the operation of the circuit of FIG. 1 will be described.
First, assume side a of secondary winding n.sub.2 is at a voltage of Eo/2 with respect to ground potential. In this case, diode D.sub.1 is turned on so that capacitor C.sub.11 is charged to a voltage Eo/2, in the direction such that its node e becomes positive, by a current which flows through node m, diode D.sub.1, node e, capacitor C.sub.11 and the output terminal b. Next, side b of the secondary winding n.sub.2 is at a voltage of Eo/2, with respect to ground potential. In this case, diode D.sub.2 is turned on so that capacitor C.sub.1 is charged to a voltage 3/2Eo which is the sum of the output voltage Eo of the secondary winding and the charged voltage Eo/2, in the direction such that node f becomes positive, by a current which flows through the output terminal b, capacitor C.sub.11, node e, diode D.sub.2, node f, capacitor C.sub.1 and terminal a.
Next, the output terminal a of the secondary winding is at a voltage of Eo/2. In this case, diode D.sub.3 is turned on so that capacitor C.sub.6 is charged to a voltage of 2Eo which is the sum of the output voltage Eo/2 between the terminal a and node m of secondary winding and the charged 3/2Eo of capacitor C.sub.1, in the direction such that node g becomes positive, by a current which flows through the output terminal a, capacitor C.sub.1, node f, diode D.sub.3, capacitor C.sub.6 and node m. At the same time when the diode D.sub.3 is turned on, the diode D.sub.4 is turned on so that capacitor C.sub.12 is charged to a voltage of 2Eo which is the sum of the output voltage Eo of the secondary winding, the charge 3/2Eo of capacitor C.sub.1 and the charged -Eo/2 (a charge direction which is the reverse of that at the capacitor C.sub.12) of capacitor C.sub.11, in the direction such that node h becomes positive, by a current which flows through node m, terminal a, capacitor C.sub.1, diode D.sub.3, diode D.sub.4, capacitor C.sub.12, capacitor C.sub.11 and the terminal b.
Next, the output terminal b of the secondary winding is at a voltage of Eo/2. In this case, the diode D.sub.5 is turned on so that capacitor C.sub.2 is charged to a voltage of 2Eo which is the sum of the output voltage Eo of the secondary winding, the charged voltage Eo/2 of capacitor C.sub.11, the charged voltage of 2Eo of capacitor C.sub.12 and the charged voltage -3/2Eo of capacitor C.sub.1, in the direction such that node j is positive, by a current which flows through the secondary winding n.sub.2, capacitor C.sub.11, capacitor C.sub.12, diode D.sub.5, capacitor C.sub.2, and capacitor C.sub.1. Next, the output terminal a of the secondary winding is at a voltage of Eo/2. In this case, the diode D.sub.6 is turned on so that capacitor C.sub.7 is charged to a voltage of 2Eo which is the sum of the output voltage Eo/2 between the terminal a and node m of secondary winding n.sub.2, the charged voltage 3/2Eo of capacitor C.sub.1, the charged voltage 2Eo of capacitor C.sub.2 and the charged voltage -2Eo of capacitor C.sub.6, in the direction such that node k becomes positive, by a current which flows through terminal a, capacitor C.sub.1, capacitor C.sub.2, diode D.sub.6, capacitor C.sub.7, capacitor C.sub.6 and node m.
At the same time the diode D.sub.7 is turned on so that capacitor C.sub.13 is charged to a voltage of 9/2Eo which is the sum of the output voltage Eo of secondary winding n.sub.2, the charge voltages 3/2Eo of capacitor C.sub.1 and the charged voltage 2Eo of capacitor C.sub.2, in the direction such that node 1 becomes positive, by a current which flows through the secondary winding n.sub.2, capacitors C.sub.1, C.sub.2, diode D.sub.6, D.sub.7, and capacitor C.sub.13.
Next, the terminal b of the secondary winding n.sub.2 is at a voltage of Eo/2. In this case, diode D.sub.8 is turned on so that capacitor C.sub.3 is charged to a voltage of 11/2Eo which is the sum of the output voltage Eo of the secondary winding n.sub.2 and the charged voltage 9/2Eo of capacitor C.sub.13, in the direction such that node n becomes positive, by a current which flows through the secondary winding n.sub.2, capacitor C.sub.13, diode D.sub.8 and capacitor C.sub.3. Next, the terminal a of the secondary winding is at a voltage of Eo/2. In this case, diode D.sub.9 is turned on so that capacitor C.sub.8 is charged to a voltage of 2Eo which is the sum of the output voltage Eo/2 between the terminal a and node m, the charged voltage 11/2Eo of capacitor C.sub.3 and the charged voltage -2Eo, -2Eo of capacitor C.sub.7 and C.sub.6, respectively, in the direction such that node s becomes positive, by a current which flows through node m, terminal a, capacitor C.sub.3, diode D.sub.9 and capacitors C.sub.8, C.sub.7, C.sub.6.
At the same time, diode D.sub.10 is turned on. In this case, capacitor C.sub.14 is charged to a voltage of 2Eo which is the sum of the output voltage Eo of the secondary winding n.sub.2, the charged voltage 11/2Eo of capacitor C.sub.3 and the charged voltage -9/2Eo of capacitor C.sub.13, in the direction so that node t becomes positive, by a current which flows through the secondary winding n.sub.2, capacitor C.sub.3, diodes D.sub.9, D.sub.10, and capacitors C.sub.14, C.sub.13.
Next, the terminal b of the secondary winding n.sub.2 is at a voltage Eo/2. In this case, the diode D.sub.11 is turned on so that a capacitor C.sub.4 is charged to a voltage of 2Eo which is the sum of the voltage Eo of the secondary winding n.sub.2, charged voltages 9/2Eo, 2Eo of capacitors C.sub.13, C.sub.14, and the charged voltages -11/2Eo of capacitor C.sub.3, in the direction such that node u becomes positive, by a current which flows through the secondary winding n.sub.2, capacitors C.sub.13, C.sub.14, diode D.sub.11, and capacitors C.sub.4, C.sub.3.
Next, the terminal a is positive. In this case, diode D.sub.12 and diode D.sub.13 are turned on. As a result, capacitor C.sub.9 is charged to a voltage 2Eo which is the sum of the output voltage Eo/2 between the terminal a and node m, the charged voltages 11/2Eo, 2Eo of capacitors C.sub.3, C.sub.4 and the charged voltages -2Eo, -2Eo, -2Eo of capacitors C.sub.8, C.sub.7, C.sub.6, in the direction such that node v becomes positive, by a current which flows through node m, terminal a, capacitors C.sub.3, C.sub.4, diode D.sub.12, capacitors C.sub.9, C.sub.8, C.sub.7, C.sub.6. At the same time, capacitor C.sub.15 is charged to a voltage 2Eo which is the sum of the voltage Eo of the secondary winding n.sub.2, the charged voltages 11/2Eo, 2Eo of capacitors C.sub.3, C.sub.4 and the charged voltages -2Eo, - 9/2Eo of capacitor C.sub.14, C.sub.13, in the direction such that node w is positive, by a current which flows through the secondary windings n.sub.2, capacitors C.sub.3, C.sub.4, diodes D.sub.12, D.sub.13 and capacitors C.sub.15, C.sub.14, C.sub.13.
Next, the terminal b of the secondary winding is positive. In this case, diode D.sub.14 is turned on so that capacitor C.sub.5 is charged to a voltage 2Eo which is the sum of the output voltage E.sub.o of the secondary winding n.sub.2, the charged voltage 9/2E.sub.o 2E.sub.o, 2E.sub.o of capacitors C.sub.13, C.sub.14, C.sub.15 and the charged voltage -2Eo, -11/2E.sub.o of capacitors C.sub.4, C.sub.3, in the direction such that node x is positive, by a current which flows through the secondary winding n.sub.2, capacitors C.sub.13, C.sub.14, C.sub.15, diode D.sub.14 and capacitors C.sub.5, C.sub.4, C.sub.3. Next, the terminal a is positive. In this case, the diode D.sub.15 is turned on so that capacitor C.sub.10 is charged to a voltage 2E.sub.o which is the sum of the output voltage Eo/2 between terminal a and node m, the charged voltages 11/2E.sub.o, 2E.sub.o, 2E.sub.o of capacitors C.sub.3, C.sub.4, C.sub.5 and the charged voltages -2E.sub.o, -2E.sub.o, -2E.sub.o, -2E.sub.o of capacitors C.sub.9, C.sub.8, C.sub.7, C.sub.6, in the direction such that the output terminal is positive, by a current which flows through node m, terminal a, capacitors C.sub.3, C.sub.4, C.sub.5, diode D.sub.15 and capacitors C.sub.10, C.sub.9, C.sub.8, C.sub.7, C.sub.6.
As described above, each of the output capacitors C.sub.6 to C.sub.10 is charged to voltage 2E.sub.o which is twice the output voltage E.sub.o of the secondary winding n.sub.2. The voltages E.sub.1 and E.sub.2 are obtained by summing the voltages on the capacitors C.sub.6 and C.sub.7 for voltage E.sub.2 to capacitors C.sub.8 and C.sub.10 for voltage E.sub.1. Thus, the voltages obtained are as expressed in equations (1) and (2) above.
The equations (1) and (2) are formed under no load. When load current flows from the output terminals P.sub.2 and P.sub.1, a voltage drop E.sub.d is established, which will now be considered with reference to FIG. 2.
In FIG. 2, the mean value of the load current flowing during one period T (=1/f) is designated by I (A), and the voltage drop which occurs during one period in an output capacitor of a capacity C (F) is designated by e.sub.O (V). The capacitances of the individual capacitors are assumed to be equal.
The following conditions (a) to (c) hold for FIG. 2:
(a) A load current flows through the output capacitors C.sub.11, C.sub.12 and C.sub.13 connected in series, so that each output capacitor produces an equal voltage drop e.sub.o of predetermined value.
(b) The voltage drops during one period generated in capacitors C.sub.11, C.sub.12 and C.sub.13 at the instant within that period at which point a becomes positive are supplied by capacitors C.sub.21, C.sub.22 and C.sub.23 (i.e., they are charged to compensate for discharges due to the current flows).
(c) The voltage drops during one period, generated in capacitors C.sub.21, C.sub.22 and C.sub.23 at the instant within that period at which point b becomes positive are supplied by capacitors C.sub.31, C.sub.32 and C.sub.33.
As a result, the voltage drops in the individual capacitors during one period are as follows:
C.sub.11, C.sub.12 and C.sub.13 : e.sub.O,
C.sub.21 : e.sub.O, (i.e., the voltage drop due to the supply of C.sub.11)
C.sub.31 : e.sub.O, (i.e., the voltage drop due to the supply of C.sub.21)
C.sub.22 : 2e.sub.O, (i.e., the voltage drop due to the supply of C.sub.12 and C.sub.31)
C.sub.32 : 2e.sub.O, (i.e., the voltage drop due to the supply of C.sub.22)
C.sub.23 : 3e.sub.O, (i.e. the voltage drop due to the supply of C.sub.13 and C.sub.32), and
C.sub.33 : 3e.sub.O, (i.e. the voltage drop due to the supply of C.sub.23).
The total voltage drops in the circuit are the sums of the voltage drops in the individual capacitors occuring in one cycle and are as follows:
C.sub.33 : 3e.sub.O, C.sub.23 : 6e.sub.O, C.sub.32 : 8e.sub.O,
C.sub.22 : 10e.sub.O, C.sub.31 : 11e.sub.O, and C.sub.21 : 12e.sub.O.
The output capacitor C.sub.11 is supplied by the capacitor C.sub.21 so that the voltage drop in the output capacitor C.sub.11 after the current supply to the load is 12e.sub.O.
Similarly, output capacitors C.sub.12 and C.sub.13 have voltage drops of 10e.sub.O and 6e.sub.O, respectively.
The values of the voltage drops in the output capacitors C.sub.11, C.sub.12 and C.sub.13 can be broken down as follows:
C.sub.11 : (2.times.3+2.times.2+2.times.1)e.sub.O,
C.sub.12 : (2.times.3+2.times.2)e.sub.O, and
C.sub.13 : (2.times.3)e.sub.O.
In the above three equations, the underlined numerals 3 correspond to one-half of the number of capacitors C.sub.21, C.sub.22, C.sub.23, C.sub.31, C.sub.32 and C.sub.33 connected between points a and b and nodes between rectifying elements. Therefore, if one-half of the number of capacitors connected between point a and b and nodes between rectifying elements is generally designated by n, the voltage drops in the output voltage capacitors can be expressed by the following equations:
and
The total voltage drop resulting from the flow of the load current is the sum of the voltage drops in the individual capacitors. Generally speaking, therefore, the total voltage drop E.sub.d is expressed by the following equation when there are three output capacitors:
wherein the underlined numerals 3 designate one-half of the number of capacitors connected between point a and b and nodes between rectifying elements.
If one-half of the number of capacitors connected between point a and b and nodes between rectifying elements is designated by n, the total voltage drop in the output capacitors is expressed by the following equation when the voltage drops expressed by Equations (a), (b) and (c) are extended to the case of a number n of output capacitors:
This equation can be rewritten in the following form: ##EQU1##
In the above equation (3), e.sub.O =Q/C=IT/C=1/(C.times.f).
As a result, the voltage drop E.sub.d, when the load voltage is applied at the output, is expressed by the following equation: ##EQU2## wherein: n: one-half of the number of capacitors connected between the nodes between rectifying elements and points a and b,
I: load current (A),
C: capacitance of capacitors (F), and
f: frequency of input power supply (Hz).
Therefore, the voltage drop E.sub.1d in the voltage E.sub.1 is expressed by the following equation: ##EQU3## wherein I.sub.1 =i.sub.1.
On the other hand, the voltage drop E.sub.2d in the voltage E.sub.2 is expressed by the following equation, because the voltage drop due to the current i.sub.1 is added to the voltage drop due to the current i.sub.2 : ##EQU4## wherein I.sub.2 =i.sub.1 +i.sub.2.
From the above, if the voltage at output terminal P.sub.2 (FIG. 1) under load is designated by E.sub.2, and if the voltage from output terminal P.sub.2 to output terminal P.sub.1 is designated E.sub.1, voltages E.sub.1 and E.sub.2 are expressed by the following equations: ##EQU5##
These equations (7) and (8) can be rewritten in the following form: ##EQU6##
According to the equations (9) and (10) thus far described, the capacitances of the capacitors constituting the step-up rectifier circuit are set according to the magnitudes of output currents and voltages relating to such capacitors, frequency of input power supply, the secondary voltage of the transformer and the number of voltage-multiplication steps in the sections relating to those currents. As a result, if the capacitance of each capacitor is determined on the basis of equations (9) and (10), the output voltages and currents at individual output terminals can be made constant, regardless of the load conditions.
Another embodiment of the present invention will be described in FIG. 3, where components identical to those in FIG. 1 are indicated by the same reference characters.
As shown in FIG. 3, one terminal of each of capacitors C.sub.1 and C.sub.2 is connected to the node between diodes D.sub.2 and D.sub.3 and the node between diodes D.sub.5 and D.sub.6, respectively, and the other terminals thereof are connected to terminal a of the secondary winding n.sub.2 of the transformer T. One terminal of each of capacitors C.sub.11 and C.sub.12 is connected to the node between diodes D.sub.1 and D.sub.2 and the node between diodes D.sub.4 and D.sub.5, respectively, and the other terminals thereof are connected to the other terminal b of the secondary winding n.sub.2 of the transformer T. An output which has a voltage to ground of E.sub.3 (V) and a current i.sub.3 (A) is obtained from a node P.sub.3 (which will be referred to as the "output terminal P.sub.3 ") between capacitors C.sub.6 and C.sub.7. The remainder of the circuit of FIG. 3 is constructed in the same manner as the corresponding components shown in FIG. 1.
With this structure the output terminals P.sub.1 and P.sub.2 can be handled in exactly the same way as in the foregoing embodiment of FIG. 1, and similar operations may be conducted for output terminals P.sub.2 and P.sub.3 by substituting (i.sub.1 +i.sub.2) and (i.sub.1 +i.sub.2 +i.sub.3) for I.sub.1 and I.sub.2, respectively, in formulas (9) and (10). Effects similar to those of the foregoing embodiment can be obtained by these substitutions.
By using this concept, moreover, the individual output voltages from a circuit with three or more output terminals can be stabilized.
In the embodiments thus far described, the description has concerned the case in which the secondary winding of a transformer provided with a tap is used as first to third input terminals to which an AC voltage is applied. The present invention can also be exemplified by a structure in which the first to third input terminals are connected to an AC power supply directly, i.e., not through a transformer.
Claims
What is claimed is:
1. A step-up rectifier circuit for multiplying input voltage applied to said circuit comprising first and second input terminals for supplying AC inputs of opposite polarities; a third input terminal connected between said first and second input terminals; rectifier means provided with a plurality of rectifying elements connected in series with said third input terminal and aligned in the same direction of rectification, a plurality of series-connected output capacitors, having one end connected to said third input terminal, and connected in parallel to said plurality of rectifying elements; a first output terminal connected to the other end of said series-connected output capacitors; a second output terminal connected to a node between said output capacitors; at least one additional output terminal connected to a node between said output capacitors which are located between said second output terminal and said third input terminal, a plurality of first capacitors connected between said first and second input terminals and nodes formed between those rectifying elements located between said first output terminal and said second output terminal; a plurality of second capacitors connected between said first and second input terminals and nodes formed between those rectifying elements located between said second output terminal and said additional output terminal; and a plurality of additional capacitors connected between said first and second input terminals and nodes formed between those rectifying elements located between said additional output terminal and said third input terminal; wherein each capacitance Ca in farads of said first capacitors and each capacitance Cb in farads of said second capacitors are defined by the following equations: -E.sub.1) -E.sub.2) in which I.sub.1 designates the current in amperes flowing through the first output terminal; n designates one-half of the number of said first capacitors; f designates the frequency in Hertz of the power supply; Eo designates the voltage in volts between said first and second input terminals; E.sub.1 designates output voltage in volts between first and second output terminals; I.sub.2 designates the current in amperes flowing through the second output terminal; n.sub.2 designates one-half of the number of said second capacitors; E.sub.2 designates output voltage in volts between said second output terminal and said additional output terminal.
2. The step-up rectifier circuit as defined in claim 1 wherein said first and second input terminals for applying AC outputs of opposite polarities are first and second terminals of a secondary winding of a transformer.
Patent Citations (6)
| Patent | Date | Inventor | Cited By |
|---|---|---|---|
| US2619602 | 1952-11-01 | Walker et al. | |
| US4437147 | 1984-03-01 | Takamura et al. | |
| JPX56-62069 | 1981-05-01 | ||
| CHX491526 | 1970-07-01 | ||
| GBX645630 | 1948-04-01 | ||
| GBX843736 | 1960-08-01 |
Non-Patent Literature (1)
- "Handbook of Rectifier Circuits", published by Ellis Horwood, Co., Ltd. in 1980, pp. 158-168.