Variable Size and Position Dialog Area Display System

The present invention relates to computer terminals and particularly to a method and apparatus for variably positioning and blanking alphanumeric information on the display of a computer terminal.

In computer generated displays, especially those for portraying both graphic and alphanumeric information, it is desirable to selectively position or blank part of the alphanumeric information, as normally provided, so as not to obscure the graphics on the same screen. Then, on call, the alphanumeric information can be re-displayed for the purpose of communicating with the host computer.

The management of this alphanumeric information can consume an inordinate amount of time, requiring additional firmware and memory space for providing identification relative to character rows it is desired to blank or move. With computer terminals operating at high communications rates, it would be desirable to select certain lines of alphanumeric information for display with the least amount of interference with the normal functions of the terminal.

In accordance with the present invention in a preferred embodiment thereof, an input for positioning and blanking alphanumeric information on a computer terminal comprises one data word, including a first plurality of bits for indicating the position of the top line of alphanumeric information to be displayed, and a second group of bits for indicating the bottom line of the alphanumeric information to be displayed. In particular, the top bits indicate the number of lines which will occur before the alphanumeric display turns on, and the aforesaid bottom bits indicate how many lines are portrayed before the dispaly turns off. A first state machine, termed a clocks state machine or a clocks programmable array logic means, is responsive to synchronization of the terminal's video display for clocking a second state machine, or window programmable array logic means, for counting through the number of lines which are inhibited on the display. The second state machine then counts through the number of lines which are enabled before the screen is again blanked, providing an intervening, selectably positionable number of lines of alphanumeric data that can be viewed by the operator.

It is accordingly an object of the present invention to provide an improved method and means for selectively portraying lines of alphanumeric information on a video display.

It is another object of the present invention to provide a method and apparatus for selectively enabling the portrayal of lines of alphanumeric information on a display with a minimum of communication and management by the system software or firmware.

It is a further object of the present invention to provide an improved method and apparatus for directing the portrayal of alphanumeric information on a computer terminal with the minimum of interference with communication between the computer terminal and its host computer.

The subject matter of the present invention is particularily pointed out and distinctly claimed in the concluding portion of this specification. However, both the organization and method of operation, together with further advantages and objects thereof, may best be understood by reference to the following description taken in connection with accompanying drawings wherein like reference characters refer to like elements.

FIG. 1 is a block diagram of a system for controlling the portrayal of alphanumeric information according to the present invention.

FIG. 2 is a waveform chart for illustrating the portion of a video waveform, between vertical sync pulses, during which the FIG. 1 apparatus operates to control the presentation of lines of alphanumeric information,

FIG. 3 is a schematic illustration of plural lines of alphanumeric information on a display,

FIG. 4 is a schematic portrayal of one character on a line of alphanumeric information in a display,

FIG. 5 is a waveform chart illustrating the generation of a clock input to a window state machine in the FIG. 1 apparatus,

FIG. 6 is a schematic diagram of a portion of a programmable array logic circuit employed in the present invention.

FIG. 7 is a state diagram illustrating operation of the window programmable array logic circuit in FIG. 1, and

FIG. 8 is a state diagram for a portion of the clocks programmable array logic circuit in FIG. 1.

Referring to FIG. 1, illustrating a system according to the present invention in block diagram form, 64K bytes of IO space for the computer terminal to which the present system pertains are illustrated at 10, wherein an address 12 may be generated for clocking latch 14 coupled to the data bus 16 associated with the terminal. The data word addressed includes five "top bits", the purpose of which is to indicate how many lines of alphanumeric data occur before the terminal display is turned on, and five "bottom bits" the purpose of which is to indicate how many lines of visible alphanumeric information occur before the display is turned off. These bits of information are selectively provided to a "window" PAL (Programmable Array Logic Circuit) or state machine 18. The window PAL 18 is clocked from a clocks PAL (or rather a WINCLK portion thereof) on line 22. The clocks PAL 20 essentially provides one clock on line 22 for each DRB (data row boundary) input and causes the window PAL 18 to change to a different state. The data row boundary or DRB input at 24 is provided from conventional circuitry of the terminal display and is coincident with the time of starting of each alphanumeric row of information that could be displayed on the terminal. Thus, the data row boundary or DRB input may comprise a divided down horizontal sync signal from the computer terminal, or is otherwise conventionally derived by means well understood by those skilled in the art.

The "cell" for an alphanumeric presentation of a letter or other character is indicated in FIG. 4 and is divided into fifteen horizontal lines, any one of which may present a number of "pixels", according to the presence or absence of a portion of an alphanumeric character. The alphanumeric characters acorss the screen of the display are generated by fifteen (or less) consecutive horizontal scan lines, and approximately one fifteenth of each character may be generated for each of these scan lines.

According to FIG. 3, a plurality of character lines are indicated by the letters A, B, C, and D respectively, and the occurence of DRB or the data row boundary signal is indicated by reference numeral 24. This signal will ordinarily occur at the start of a line. Assuming the character lines are each divided into fifteen parts as was illustrated in FIG. 4, there will be fifteen horizontal sync signals for each occurence of DRB. Referring to FIG. 5, the generation of the clocking signal on line 22 is indicated at 26 and occurs at the coincidence of the first horizontal sync pulse 28 after DRB commences at 30.

The clocks PAL 20 receives DRB on lead 24, receives the horizontal sync signal from the terminal display on lead 32, and generates the clocking signal for window PAL 18 on lead 22. The output of the FIG. 1 system is indicated as DIAENB-0 (or dialog enable) an output lead 34 from window PAL 18. This signal is also supplied to clocks PAL 20 on lead 36 for the detection of turnoff of dialog enable. When the clocks PAL 20 detects the cessation of output, no further clocks are presented to the window PAL on lead 22.

In general, the clocks PAL presents one clock signal, also indicated at 38 in FIG. 2, for each character row of the display which occurs between vertical sync pulses 40 as generated by the terminal display. No display occurs during the vertical blanking period which includes the vertical sync pulses 40. As illustrated in FIG. 1, each of the clocks PAL and window PAL circuits also receives the vertical sync from line 42 which operates as a load signal for the window PAL 18. Clocks PAL 20 further receives a vertical reset signal at 44 and a 25.2 megahertz clock at 26.

At every vertical sync time, when the picture isn't being displayed, the window PAL 18 is re-loaded with values written into latch 14. When the vertical sync signal concludes, the window PAL 18 goes to the state indicated by the top bits from latch 14. If the top bits indicate a zero, the entire screen will be blanked insofar as rows of alphanumeric characters are concerned.

The window PAL (or window shade PAL) 18 normally passes through a number of states which are illustrated in FIG. 7. The window PAL 18 is set to one of the top states (0 through 31 in FIG. 7), with the state number determining the number of rows of alphanumeric characters that are "skipped" before the display is presented on the screen. Thus, the window PAL 18 may be viewed as a counter that can be loaded with the top bits from latch 14 and which then counts to thirty-one. The sixth bit position generated by the window PAL 18 is the dialog enable signal on line 34 occuring when the window PAL changes from state 31 to state 32. At state 32, the bottom bits from latch 14 indicate the state to which the window PAL is loaded for setting how many lines of visible alphanumeric characters will be presented before the dialog enable signal is turned off. Dialog (alphanumerics) turnoff occurs when the window PAL changes from state 63 back to state 0. This state diagram, as well as the state diagram (FIG. 8) for clocks PAL 20, will be described subsequently in greater detail.

As the window PAL 18 changes from state 31 to state 32, the output on line 34, i.e. DIAENB-0, is produced which is employed to enable or blank the alphanumeric portion of the cathode ray tube display of the terminal in a conventional manner. It is termed the attribute control and serves to enable the desired number of circuits which pertain to the alphanumeric display.

Referring to FIG. 6, each of the PALs comprises a programmable array logic circuit illustrated in part in the figure. Each of the state outputs (six for window PAL 18, and three for the WINCLK portion of clocks PAL 20) are generated by a logic circuit of the type depicted comprising an OR gate 50 provided with a number of inputs via drivers from horizontal lines of the matrix, with the OR gate driving a D flip-flop 52. The Q ouput of the flip-flop is provided to inverter 54, and also the inverted Q output of the flip-flop is coupled through amplifier 56 to provide inverted feedback and not inverted feedback output to the matrix. A clocking input for the D flip-flop is supplied on lead 62. In order to implement the logic of the PAL, crossovers are enabled at desired interconnections of the horizontal and vertical conductors in accordance with a schedule as hereinafter set forth. Also, the array as depicted in FIG. 6 is repeated n times, where n is the number of state ouputs to be provided on successive leads 60. It will be understood that the vertical lines in FIG. 6 represent inputs from successive input amplifiers such as amplifier 58, as well as feedback from successive feedback amplifiers such as amplifier 56.

FIG. 8 is a state diagram for the WINCLK portion of clocks PAL plane. The VRESET (on lead 44 in FIG. 1) will take PAL 20 to state 1 (binary 001) from any other state. Assume there is a vertical retrace after a reset. The state machine will go from state one (WCLK1) to state three (WCLK3). While the terminal is in vertical retrace, the state will shift back and forth between state three (WCLK3) and state two (WCLK2). While this occurs, the window PAL 18 is clocked on lead 22 since the LSB (least significant bis) of the state machine is the output on lead 22. This causes the window PAL 18 to be set to its state 0 to be ready for the next screen.

When vertical retrace ends, and the PAL 20 is in state three (WCLK3), it will then go to state six (WCLK6). This again clocks the window PAL and causes the window PAL to load the top edge value, i.e. the top bits from latch 14. The window PAL will go to one of the top 31 states.

PAL 20 then goes to state one (WCLK1) which waits for data row boundary (DRB) and H sync. When this occurs, the clocks PAL proceeds to state zero (WCLK0) giving a clock to the window PAL 18. When DRB (data row boundary) is discontinued, the state machine returns to state one (WCLK1). If the dialog area (the area of the screen to be enabled) never occurs or is never enabled, the clocks PAL will remain in these two states until vertical sync occurs. If the dialog area is enabled, the clocks PAL 20 will then go to state five (WCLK5) from state one (WCLK1). While the dialog remains enabled, the clocks PAL 20 will clock at DRB and H sync, going from state five (WCLK5) to state four (WCLK4) and back. If vertical sync comes during this time, an exit from state five (WCLK5) to state one (WCLK1) is accomplished. If the dialog area is defined so that it is disabled before the end of the screen, the clocks PAL goes from state five (WCLK5) to state seven (WCLK7). The clocks PAL then remains in this state until vertical sync. At vertical sync, the clock is stopped to window PAL 18, to prevent wrap around.

In the state diagram, VS refers to vertical sync and PIPEVS refers to pipelined vertical sync or an accurately retimed or re-synced signal appropriate for the circuitry. Similarly, PIPEHS refers to pipelined horizontal sync and PDRB refers to a pipelined data row boundary signal.

Referring to the state diagram of the window PAL 18 in FIG. 7 in greater detail, it is noted this state machine generates the DIAENB-0 (dialog enable-0) signal to determine when the alphanumeric system of the terminal should be enabled. The dialog is settable to become enabled at any line upon the screen, and the dialog may be disabled after so many visible lines. The inputs to the window PAL state machine are five bits of top enable and five bits of bottom disable load information. Also, a load signal (PIPEVS-0) is provided to load the count of the top edge during vertical time. The clock signal is a derivation of DRB, H sync and V sync as presented on line 22 from the clocks PAL 20 as hereinbefore mentioned. The conditions on the clock on line 22 are as follows: There must be one clock while PIPEVS-0 is low. More clocks are possible, but at least one is required. This causes the window PAL state machine to go to state zero and stay there while PIPEVS-0 is active. The load pulse is then removed and one additional clock is given. This causes the input data for the top window edge (the top bits) to be loaded into the "counter" represented by window PAL 18. Now, the first DRB will cause the "counter" to clock to the next state, depending on the value of the top edge register. In other words, the state machine will jump to some state between 1 and 31 depending on the top bits. Then, depending upon the value jumped to, after some number of clocks occuring while lines of characters are not seen on the screen, the dialog or alphanumeric area will be enabled to the generation of DIAENB-0, when the "counter" reaches 32.

When the dialog area becomes enabled, the window PAL 18 then loads the bottom register bits. This sets the number of counts before the dialog is disabled again. When this count is reached, the clock for the window PAL will stop so that wrap around of the dialog enable signal is not possible. When PIPEVS-0 becomes active, the cycle begins again.

In this particular embodiment, because of the clocks required to load the window PAL, there is a limit to the minimum number of lines that can be displayed. An extra clock occurs when PIPEVS-0 becomes inactive and this loads the top edge value. Then, the first DRB derivation causes the state machine to clock, and this could enable the dialog. One clock is required to load the bottom edge and this displayed one line of dialog. One clock is required to disable the dialog enable signal and this displayed the second line. Consequently, the minimum size of a window in accordance with the particular embodiment is two lines. Of course, the display can be totally turned off by writing a "top" value of zero.

The logical equations setting forth the logical functions of clocks PAL 20 are given as follows. It will be observed that two additional outputs, DCARE2 and DCARE3, are also set forth, inasmuch as they provide inputs for the logical determination of WINCLK provided on lead 22.

The output WINCLK is provided on lead 22 to the window PAL. CLKTST will always cause full screen at the bottom, but its non-assertion will not affect the described procedure.

The following is a description in high level state machine language of the pertinent portion of the clocks PAL. ##SPC1##

The following is a scheduel of fuse connections for the clocks PAL, model 20R8 manufactured by Monolithic Memories, Inc. ##SPC2##

The logical equations setting forth the logical functions of the window or window shade PAL 18 are as follows:

It will be observed that five state outputs in addition to DIAENB are provided, namely WIN0, WIN1, WIN2, WIN3 and WIN4, these being used as inputs in the determination of DIAENB.

The following is a description in high level state machine language of the window or window shade PAL 14: ##SPC3##

The following is a schedule of fuse connections for the window or window shade PAL model 20R6 manufactured by Monolithic Memories, Inc. ##SPC4##

It will be noted from the foregoing that control of the number of lines of alphanumeric characters written on the screen of the terminal is accomplished with a minimum of interference with the overall operation of the terminal, being responsive to a single data word.

While a preferred embodiment of the present invention has been shown and described, it will be apparent to those skilled in the art that many changes and modifications may be made without departing from the invention in its broader aspects. The appended claims are therefore intended to cover all such changes and modifications as fall within the true spirit and scope of the invention.