Automatic Gain Control Circuit

1. Field of the Invention

The present invention relates to an automatic gain control (AGC) circuit and particularly to a video AGC circuit for use in a video unit such as a video tape recorder, a video disc player and the like.

2. Description of the Prior Art

In a video tape recorder, for example, the magnitude of a luminance signal (a composite video signal) applied from a video camera or a television tuner needs to be made equal to a certain value so that the signal may be frequency modulated and recorded. For this purpose, a video AGC circuit is generally utilized.

As such video AGC circuits, various types have been proposed. Recently, there is a growing demand for an AGC circuit of the type giving preference to keyed AGC operation in combination with peak AGC operation as indicated for example in pages 102 to 105 in "National Technical Report Vol. 25, No. 1" (published in Feb., 1979)

An AGC circuit of this type is generally constructed as shown in FIG. 1. Referring to FIG. 1, the reference numeral 20 denotes a video AGC circuit; the reference numeral 1 denotes an input terminal of a composite video signal; the reference numeral 2 denotes a gain control amplifying circuit; the reference numeral 3 denotes an output terminal of a gain controlled composite video signal; the reference numeral 4 denotes a synchronizing signal separation circuit for separating horizontal and vertical synchronizing signals from a composite video signal; the reference numeral 5 denotes a sync-tip clamp circuit for clamping to a certain potential the sync-tip level of a synchronizing signal of a video signal provided from the above stated control circuit 2; the reference numeral 6 denotes a delay circuit for delaying the above stated synchronizing signal by approximately 2 .mu.sec.; the reference numeral 7 denotes a pulse mixing circuit for mixing a reference pulse with the composite video signal from the clamp circuit 5; the reference numeral 8 denotes a detecting circuit for detecting the peak of the output signal of the pulse mixing circuit 7; the reference numeral 9 denotes a comparator for comparing a peak potential at the point B of the peak detecting circuit 8 and a reference potential at the point A preset by a variable resistor VR; and the reference numeral 10 denotes a connection line for controlling the above stated control circuit 2 according to the output of comparison.

In a conventional AGC circuit shown in FIG. 1, the level of a reference pulse applied thereto is always fixed to a certain value even if the reference voltage level for automatic gain control operation (AGC operation) is changed by a variable resistor VR. As a result, a disadvantage is involved that desired AGC operation giving preference to keyed AGC in combination with peak AGC might become impossible dependent on the state of a composite video signal.

The present invention is an AGC circuit for performing AGC operation giving preference to keyed AGC in combination with peak AGC, by which the amplitude level of a reference pulse applied to a pedestal of a composite video signal for keyed AGC operation is changed or deceased in proportion to the change of reference voltage for setting an AGC operation level.

Thus, in this invention, if the reference voltage for setting an AGC operation level is changed to vary the output gain of a video signal, the amplitude value of a reference pulse serving as a reference for keyed AGC operation is also changed according to that change. Accordingly, it is made possible to provide an AGC circuit capable of always performing AGC operation giving preference to keyed AGC in combination with peak AGC irrespective of the change in the output level.

These objects and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.

FIG. 1 is a block diagram showing an example of a conventional video AGC circuit;

FIG. 2 is a block diagram showing a video AGC circuit of an embodiment of the present invention; and

FIGS. 3, 4, 5 and 6 are signal waveform diagrams for explaining the operation of the circuit shown in FIG. 2.

FIG. 2 is a block diagram showing a video AGC circuit of an embodiment of the present invention. Referring to FIG. 2, a video AGC circuit 30 includes an input terminal 1 for a composite video signal. The input terminal 1 is connected to a gain control amplifying circuit 2. The gain control amplifying circuit 2 controls the gain of a composite video signal applied based on a control signal supplied through a connection line 10 to be described later. The gain controlled composite video signal is provided from an output terminal 3 on the output side of the circuit 2. On the output side of the gain control amplifying circuit 2, a synchronizing signal separating circuit 4 and a sync-tip clamp circuit 5 are connected. The synchronizing signal separating circuit 4 separates a horizontal synchronizing signal and a vertical synchronizing signal from the composite video signal. The synchronizing signal separating circuit 4 is connected to the sync-tip clamp circuit 5 and a delay circuit 6. Based on the synchronizing signal from the synchronizing signal separating circuit 4, the sync-tip clamp circuit 5 clamps to a fixed potential the sync-tip level of the synchronizing signals included in the composite video signal applied from the gain control amplifying circuit 2. The delay circuit 6 delays the synchronizing signals by approximately 2 .mu.sec. The sync-tip clamp circuit 5 and the delay circuit 6 are connected to a pulse mixing circuit 31.

The pulse mixing circuit 31 mixes a reference pulse in the composite video signal based on the input signals from the circuit 5 and 6. For this purpose, the pulse mixing circuit 31 is constructed so that the reference pulse is equivalently mixed in the composite video signal by shifting the level of the composite video signal applied from the sync-tip clamp circuit 5 only in a period of the low level of the delayed synchronizing signal applied from the delay circuit 6, as described below in detail.

In place of the above described construction of the pulse mixing circuit 31 of this embodiment, another construction may be adopted in which the reference pulse is mixed directly in a front porch of a pedestal of the composite video signal without level shifting of the composite video signal.

The pulse mixing circuit 31 is connected to a peak detecting circuit 8. The peak detecting circuit 8 detects peaks of the composite video signal including the mixed reference pulse (namely, a peak of the reference pulse and a peak of the video signal). To the peak detecting circuit 8, a comparator 9 is connected. The comparator 9 compares the peak potential appearing at the point B of the peak detecting circuit 8 and the reference potential at the point A set by an incorporated variable resistor VR so as to provide a gain control signal. The gain control signal is applied to the gain control amplifying circuit 2 through the connection line 10.

A circuit 32 connected between the variable resistor VR and the pulse mixing circuit 31 is a reference pulse adjusting circuit for changing the amplitude of the reference pulse mixed in the composite video signal in proportion to the reference potential at the point A set by the variable resistor VR. This embodiment is characterized by providing this reference pulse adjusting circuit 32.

The construction of the reference pulse adjusting circuit 32 will be described in detail. The reference pulse adjusting circuit 32 comprises a transistor Q.sub.11. A current mirror couple is formed by the transistor Q.sub.11 and a constant current transistor Q.sub.4 for controlling the current flowing in a differential couple of transistors Q.sub.2 and Q.sub.3 in the pulse mixing circuit 31. The collector of the transistor Q.sub.11 is connected to a power source +V.sub.CC by series connection of a resistor R.sub.4, a transistor Q.sub.12 and a resistor R.sub.5, while the emitter of the transistor Q.sub.11 is grounded through a resistor R.sub.3. The base of the transistor Q.sub.12 is connected to the reference potential setting point A set by the variable resistor VR.

FIGS. 3 to 6 are signal waveform diagrams for explaining the operation of the video AGC circuit 30 shown in FIG. 2.

First, referring to FIGS. 2, 3 and 4, a fundamental AGC operation of the circuit 30 will be described.

Assuming that the composite video signal provided at the point (a) from the synchronizing clamp circuit 5 is represented as (a) in FIG. 3 and that the delayed synchronizing signal from the delay circuit 6 is represented as (c) in FIG. 3, the transistor Q.sub.2 of the differential couple is turned off in a period of the low level of the synchronizing signal (c) and turned on in a period of the high level thereof. Accordingly, the level of the video signal (a) is shifted by a value V.sub.p only in the above described high level period and a synthesized signal appearing at the point (b) is as shown in FIG. 3(b). The peak of the synthesized signal (b) is detected by the transistor Q.sub.5 and a capacitor C1.

Now, let us consider a case where the amplitude of a synchronizing signal component S of the composite video signal (in FIG. 3(b)) provided from the sync-tip clamp circuit 5 is increased. In this case, in the waveform before detection of the peak appearing at the point B of the circuit 30, the top end of the reference pulse P exceeds the reference potential V.sub.A as shown by the solid line in FIG. 4(a). Then, in this case, the top end level of the reference pulse P is compared with the reference potential V.sub.A at the point A by a differential couple of transistors Q.sub.7 and Q.sub.8 of the comparator 9 so that the level is gain controlled to be equal to V.sub.A. Thus, as shown by the broken lines in FIG. 4(a), the amplitude of the synchronizing signal component S and the amplitude of the video signal component V are both reduced.

On the contrary, in case where the peak of the video signal component V exceeds the reference potential V.sub.A as shown by the solid line in FIG. 4(b), gain control is applied so that the peak is equal to the reference potential V.sub.A. Accordingly, in this case also, the amplitude of the video signal component V and that of the synchronizing signal component S are both reduced as shown by the broken lines in FIG. 4(b).

In other words, generally, automatic gain control operation (AGC operation) is performed such that the top end level of the reference pulse P, that is, the amplitude V.sub.S of the synchronizing signal component S, may have a fixed value, and in the case where a signal as shown in FIG. 4(b) is applied, AGC operation is performed such that the level in the peak of the video signal component V may have a fixed value. Thus, the AGC circuit performs AGC operation giving preference to keyed AGC with peak AGC as required.

Further, let us consider a case where the amplitude (output gain) of the composite video signal provided from the output terminal 3 is increased. In this case, the reference potential V.sub.A has only to be increased. Referring to FIGS. 5 and 6, it is assumed that the reference potential V.sub.A shown in FIG. 5(a) is increased by .DELTA.V.sub.A1. Then, in the conventional video AGC circuit 20 (see FIG. 1), the gain of the composite video signal is increased by the operation of the comparator 9 so that the top end of the reference pulse P may be equal to the new reference potential V.sub.A +.DELTA.V.sub.A1. In consequence, as shown in FIG. 5(b), the amplitude of the synchronizing signal component S is increased from the initial value V.sub.S0 by .DELTA.V.sub.A1 so as to be V.sub.S1. On the other hand, the amplitude of the video signal component V is also increased by a ratio V.sub.S1 /V.sub.S0, which is the same for the synchronizing signal component S, so as to be as shown by the broken line in FIG. 5(b). However, if the video signal component V exceeds the reference potential V.sub.A +.DELTA.V.sub.A1, the video AGC circuit 20 performs peak AGC operation as described above and practically, gain is controlled so that the peak of the video signal component V may be equal to V.sub.A +.DELTA.V.sub.A1. As a result, the peak of the reference pulse P becomes a little lower than V.sub.A +.DELTA.V.sub.A1.

If the reference potential V.sub.A is lowered from the state shown in FIG. 6(a) by .DELTA.V.sub.A2, the video signal component V becomes as shown in FIG. 6(b) in the conventional AGC circuit 20. In this case, since the peak of the video signal component V is considerably lower than V.sub.A, only the keyed AGC operation is performed and with respect to any change of the peak of the video signal component V, AGC operation is not at all applied.

The reason for the phenomenon in the conventional AGC circuit 20 is that the level shifted amount of the synthesized signal (b) in FIG. 3, that is, the amplitude V.sub.P of the reference pulse P is determined by the product I.sub.1 .multidot.R.sub.1 of the current I.sub.1 flowing in the constant current transistor Q.sub.4 and the resistance R.sub.1 and this value is maintained constant in the conventional circuit 20 irrespective of the change of the variable resistor VR.

Therefore, improvement is made in this embodiment to solve that problem and as shown in FIG. 2 the reference pulse adjusting circuit 31 including a current mirror circuit is provided in this embodiment.

Referring to FIG. 2, the current I.sub.1 is represented as ##EQU1## where I.sub.2 is current flowing in the mirror transistor Q.sub.11. The current I.sub.2 is obtained as (V.sub.A -2V.sub.be)/(R.sub.3 +R.sub.4) with respect to the above stated reference potential V.sub.A, that is, the base potential of the control transistor Q.sub.12 and consequently on the amplitude V.sub.P of the reference pulse P is determined by ##EQU2## As a result, according to the change of V.sub.A, the amplitude V.sub.P of the pulse P is also changed in the same direction.

By setting appropriately the respective resistance values of the resistors R.sub.1 to R.sub.4, the amplitude V.sub.p0 of the reference pulse P (that is, the level shifted amount) is set as shown in FIG. 5(a) so that the amplitude of the composite video signal may be a desired value (for example 1V.sub.p-p) in relation to a certain value of the reference potential V.sub.A and that both the keyed AGC and the peak AGC may be performed. As a result, if the reference voltage V.sub.A is increased from this state by .DELTA.V.sub.A1 by means of the variable resistor VR, the level shifted amount is increased from V.sub.p0 by .DELTA.V.sub.p1 and thus the signal waveform at the point B (the state before peak detection) is as shown in FIG. 5(c). More specifically, the synchronizing signal component S (reference pulse P) is increased by .DELTA.V.sub.A1 to be equal to V.sub.S1 and the amplitude of the video signal component V is also increased by a change amount V.sub.S1 /V.sub.S0 of the synchronizing signal component S and accordingly the amplitude (the output gain) of the composite video signal is increased and the peak of the video signal component V becomes a little lower than the changed reference potential V.sub.A +.DELTA.V.sub.A1. Thus, in the state shown in FIG. 5(c), keyed AGC operation and peak AGC operation can be performed dependent on the changes of the synchronizing signal component S (the reference pulse P) and the peak of the video signal component, respectively.

If the reference potential V.sub.A is lowered from the state shown in FIG. 6(a) (the same as in FIG. 5(a)) by .DELTA.V.sub.A2, the amplitude of the composite video signal is reduced contrary to the case in FIG. 5 and the level shifted amount is decreased from V.sub.p0 by .DELTA.V.sub.p2 to be as shown in FIG. 6(c). As a result, in this case also, keyed AGC operation and peak AGC operation can be performed dependent on the changes of the synchronizing signal component S (the reference pulse P) and the peak of the video signal component V, respectively.

Although the present invention has been described and illustrated in detail, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, the spirit and scope of the present invention being limited only by the terms of the appended claims.