Programmed Disk Controller Capable of Operating With a Variety of Data Encoding Techniques

This invention is related generally to the art of magnetic storage of computer data, and more particularly to controllers used with disk drives.

With the recent explosion in the use of disk drives in personal and business minicomputers and microcomputers, has developed a number of different techniques for recording and retrieving digital data from magnetic media, particularly disks. Various computers use different disk systems. The result is that data recorded on a floppy disk, for example, by a disk drive of one computer cannot be read by the disk drive of another.

The aspects of disk data recording that vary among the commercially available disk drives are many. The number of data circular tracks on a disk varies. The number of read/write heads, the speed at which the disk rotates, and the particular signal format required to operate the head movement stepper motor, are other aspects that vary among disk drives. Whether the sectors in the tracks are maintained in "hard" or "soft" form, and whether holes in the disk are monitored to identify the location of the start of tracks or sectors, and if so the number and placement of the holes, are among other variables that exist. Particularly, there are different techniques for encoding the computer data into magnetic transitions which are recorded on the disks.

A frequency modulation (FM) technique is a widely used data encoding technique wherein a clock signal is periodically recorded along a track of a disk with a data pulse occurring between clock signals when a "1" is to be recorded and no pulse between clock pulses when a "0" is to be recorded. A difficulty was recognized early with this technique since the recording of each clock pulse causes a large number of magnetic transitions to be recorded on the disk for a given amount of data. Since magnetic media places limitations on how densely the transitions can be spaced relative to each other, the amount of data that can be placed on a given size disk is thus limited.

Therefore, a modified frequency modulation (MFM) technique was developed wherein a clock pulse is recorded only if there has not been a data pulse recorded for a certain period of time. The reduction of the number of magnetic transitions has thus allowed increasing the density of data, thereby increasing the amount of data that can be placed on a given size disk.

Other various data encoding techniques exist as well. Another is group coded recording (GCR) wherein each data nibble (four bits) is converted into a five or six bit word that is written onto disk without any clock signals. The recorded words are chosen to have particular combinations of "1's" and "0's" that allow a maximum amount of data to be recorded for a given number of magnetic flux transitions on the disk. When the data is read off the disk, these words are reconverted to the data nibble originally recorded.

Another technique is run length limited (RLL) which is a superset of the GCR technique and used primarily in Winchester type disk drives.

The incompatibility of data encoding techniques thus makes it quite difficult to adapt one disk drive that has been built to operate with one technique to read from or write upon disks with another technique. Controllers have been provided in commercial disk copiers that have duplicate data encoding and decoding circuits that are selected by switches, but this duplicity is inappropriate, because of the complexity and cost, for use in commercial minicomputers and microcomputers.

Therefore, it is a principal object of the present invention to provide a disk controller capable of handling several different data encoding techniques that is simple and inexpensive.

This and additional objects are accomplished by the present invention, wherein, briefly, a common programmable digital state machine is utilized for translating digital data between a form used by the computer and a form recorded on the magnetic disk or other magnetic media. The state machine includes a random access memory in which a different specific code is stored depending upon whether it is desired that the controller operate with the FM, MFM, GCR, RLL, or some other data encoding technique. This sytem allows a particular piece of hardware to be usable with a selected number of different encoding and decoding techniques, simply by appropriately programming the memory of the state machine controller.

Additional objects, features and advantages of the present invention will become apparent from the following description of its preferred embodiment, which description should be taken in conjunction with the accompanying drawings.

FIG. 1 is a schematic block diagram of a computer disk controller that utilizes the present invention;

FIGS. 2A and 2B illustrate the format of two digital words used in the system of FIG. 1;

FIG. 3 is a timing diagram showing the operation of the system of FIG. 1 for FM encoding and decoding;

FIGS. 4A and 4B illustrate timing for the writing and reading, respectively, of digital data in the system of FIG. 1 when using the FM encoding and decoding technique;

FIG. 5 is a timing diagram showing the operation of the system of FIG. 1 with MFM encoding and decoding;

FIGS. 6A and 6B illustrate timing for the writing and reading, respectively, of digital data in the system of FIG. 1 when using the MFM encoding and decoding technique; and

FIG. 7 is a timing diagram showing the operation of the system of FIG. 1 with GCR encoding and decoding.

Referring to FIG. 1, a controller that utilizes the techniques of the present invention preferably has a dedicated microprocessor or microcomputer 11 connected with a host computer data and address bus 13. A microcomputer 11 has its own data and address bus 15 that is central to the controller. Data to be written onto a disk passes from the controller bus 15, through a state machine 17 and to a magnetic recording head 19. Data read from a disk by the head 19 passes back through the state machine 17 and onto the controller bus 15. The microcomputer 11 controls the communication of data between the host computer bus 13 and the controller bus 15. A single read/write head 19 is common, but the present invention can be carried out with multiple heads as well. Further, the embodiment is being described with respect to a disk drive, which can be of the floppy disk or hard disk type, but the techniques of the present invention are useful for any digital data and magnetic recording system, including tape drives and the like, wherein different data encoding and decoding techniques are desired to be selectively utilized.

The details of the operation of the system of FIG. 1 will now be described. The state machine 17 has a single input line 21. This line is the output of a digital switch 23 that selects, in response to a control signal in a line 25, the connection of the line 21 with a write data line 27 or a raw read data line 29. When the controller of FIG. 1 is in its write mode, data words on the bus 15 to be recorded are stored in a parallel-to-serial converter 31 and fed serially out, one bit at a time, on the line 27. This serial data is then passed through the state machine 17 to its output line 33. The specific operation of the state machine is described hereinafter. The signal in the output line 33 has been translated from the computer signal presented on the bus 15 into a form that will write the data in the desired format on the computer disk. This encoded write data is applied to an input of a head driving circuit 35 whose output is connected directly to the magnetic recording head 19. The head driving circuit 35 is of a common design and, in combination with a standard read/write head 19, converts the pulses applied to its input to desired north/south magnetic transitions on a magnetic disk.

When a magnetic disk is being read by the head 19, a signal proportional to the magnetic transitions is applied to standard pre-amplifying circuits 37 whose output in a line 29 is raw read data that is again translated by the state machine 17. When in the read mode, the line 29 is connected through the switch 23 to the state machine input line 21. Its output line 33 carries the translated digital data to a serial input of the parallel/serial converter 31, which forms the serially received bits into words that are applied to the controller bus 15 and thence to the host computer on the system bus 13.

The structure and operation of the state machine 17 of FIG. 1 will now be described. A random access memory 41 and a latching circuit 43 are the major components of the state machine 17. These two components are connected together by two separate paths. A first is a data bus 45 connected between a data output of the memory 41 and an input of the latch 43. The second path is a bus 47 which feeds back a portion of the output of the latch 43 to serve as a portion of an address input to the memory 41. FIG. 2B illustrates the form of the eight-bit word output of the latch 43. Seven lines, namely bits 0 through 6, form the feedback bus 47, while the eighth line, identified as carrying bit number 7, is the state machine output line 33 previously discussed.

FIG. 2A illustrates a particular form of an eleven-bit address word applied to an input of the memory 41, wherein seven bits (numbers 0-6) are applied from the output of the latch and bit number 7 is applied as part of the address of the memory 41 from the state machine input line 21 previously discussed. Three other bits (numbers 8-10) are also part of the memory address, bit number 8 provided by a write missing clock line 49 from the microcomputer 11. Bit number 9 is provided by the signal on a line 51 as to whether double density recording is desired. Finally, the last bit number 10 of the address to the memory 11 comes from a line 53 from the microcomputer 11 whose state determines whether the controller is in a mode to write onto a disk or to read from the disk.

Depending upon the particular encoding and decoding format desired, the memory 41 is conveniently loaded through its bus 45. A gate 55 operates responsive to a control signal in a line 57 from the microcomputer 11 to selectively connect the bus 45 to the controller bus 15. When so connected, the microcomputer 11 can, under software control, load the memory 41 by one eight-bit word at a time. The microcomputer 11 first puts an address on the bus 15 and renders the gate 55 conductive, that address being loaded into the latch 43. Because of the feedback bus 47, that address is then placed at the address input to the memory 41. The next step is for the microcomputer 11 to place a data word on the bus 15 that is to be stored in the memory 41 at that address. The process is repeated one data word at a time until the memory 41 is fully loaded. Besides that portion of the memory 41 address placed by the microcomputer 11 on the bus 15, it also controls the three bits in the lines 49, 51 and 53 in order to load data into all desired addresses of the memory 41.

The particular data loaded into the memory 41 for the frequency modulation (FM) encoding and decoding technique is given in Appendix A to this application. Appendix B contains data for the modified frequency modulation (MFM) technique. A five-bit type of GCR encoder and decoder will result if any one of the four versions (GCR 13, GCR 14, GCR 15 or GCR 16) given in Appendix C hereto is loaded into the memory 41. The different GCR code versions are designed for different data rate operation. The computer programs of Exhibits A, B and C are expressed in hexadecimal object code form.

Appendix D hereto gives the object code for operating the microcomputer 11 to carry out the operations being described. The computer program of Exhibit D is written for a Z8.RTM. microcomputer available from Zilog, Inc. It is preferably stored in a programmable read only memory provided as part of the Z8 microcomputer 11. The code is further designed to utilize pulses resulting from a photodetector 55 that is positioned to detect sector position marking holes that pass by it. Further, an optional buffer memory 57 is accommodated by the controller program, this buffer being utilized to temporarily hold data being read from the disk or awaiting writing on the disk. If the memory 57 is not utilized, the main memory of the host computer connected to the system bus 13 may be utilized.

Operation of the controller of FIGS. 1, 2A and 2B will now be explained for the example of FM encoding and decoding of data. A timing diagram is given in FIG. 3, showing waveforms at particular location of the system of FIG. 1 during the writing and reading of a particular data word chosen as an example. The data word 10001101 is shown in FIG. 3B in the time sequence that they are presented by the parallel/serial converter 31 onto the lines 27 and 21 to the input of the state machine 17. This data is shown in FIG. 3C as a voltage waveform extending from a low voltage corresponding to its "0" state and a higher voltage corresponding to its "1" state. A periodic, repetitive clock signal shown in FIG. 3D is generated in the state machine 17, as discussed hereinafter.

The state machine 17, operating with the program code of Appendix A to this application loaded into the memory 41, will produce an output in its line 33 that is shown in FIG. 3E. The signal of FIG. 3E is a combination of each clock pulse occurring in FIG. 3D plus a pulse intermediate thereof whenever the data bit in the input line 21 is a "1". If a "0", no intermediate pulse exists. The pattern of FIG. 3E is in accordance with the FM encoding technique. This signal is applied to a normal head driver circuit 35 whose output in the line 36 is a head driving current as shown in FIG. 3F. The result is a magnetic pattern on a track of the magnetic disk being recorded which has a flux change occurring at each of the pulses of the encoded write data of FIG. 3E.

When that data is read by the same head 19 from the same disk, a head current signal of FIG. 3F again appears, this time in a circuit 38. The raw read data of FIG. 3G, in line 29 of FIG. 1, is applied through the switch 23 to the input line 21 of the state machine 17. A drive clock signal of FIG. 3H is one output of the state machine 17, in a line 59, and the decoded read data of FIG. 3I appears on the output line 33 of the state machine 17 in a form to be applied through the converter 31 to the controller bus 15 for use by the host computer.

Obviously, the state machine 17 has to operate differently in its read and write modes. Different program code within the memory 41 is addressed in the read and write cycles since one of the bits of the address to the memory 41 is a read/write command in the line 53 from the microcomputer 11.

Operation of the state machine 17 can be illustrated in another way with respect to FIGS. 4A and 4B, which shown phase diagrams of the write and read operations, respectively. These diagrams show the timing of certain events occurring within a given bit cell. That is, with reference to FIG. 3, the phase diagrams of FIGS. 4A and 4B show one complete cycle of operation within a single bit cell. The first bit cell of FIG. 3 is between times t0 and t1, the time during which the first bit of the example word is operated upon. The state machine 17 is driven by a clock (not shown) in an ordinary manner wherein there are 64 clock cycles, in this particular example, during each bit cell time. Therefore, referring to FIG. 4A, a counter driven by the clock starts at 0 at time t0 of FIG. 3 and advances around to the count of 63 at the time t1. The counter then continues in the same cycle between the times t1 and t2, having started its count over at 0 at time t1. This counter is provided by five bits of the latch and memory 1, as indicated in FIGS. 2A and 2B, and increments one count for each cycle of the state machine clock (not shown). As shown in FIG. 4A, for the FM encoding technique, a clock pulse is generated in the output line 33 of the state machine 17 between the counter counts of 0 and 15. The program code in the memory 41 is such that a "1" exists in the output line 33 during these time periods, as also illustrated in FIGS. 3D and 3E.

As the counter reaches 31, the program code in the memory 41 will cause the output in the line 33 again to go to a "1" from the "0" state it has maintained between the counts of 16 and 31, provided that an input data bit in line 21 during that time is a "1". The code in the memory 41 will result in the state of the output data line 33 remaining a "0" if there is no such input data bit.

Referring to FIG. 4B, a phase diagram showing the operation of one bit cell cycle of the state machine 17 upon reading of data from a disk is illustrated. In the initial clock window time of each cycle, the leading edge of a clock pulse on the input data line 21 of the raw read data of FIG. 3G is looked for. That is, transition of bit number 7 of the FIG. 2A word from a "0" to a "1" during that time is looked for. Similarly, the existence of a pulse is examined during the data window portion of the cycle illustrated in FIG. 4B. If they both occur, the output in the line 33 is a "1", the desired result. If the data pulse does not occur within the window shown in FIG. 4B, then the output in the line 33 during that bit cycle will be 0. The program in the memory 41 also provides for accelerating a reset of the counter formed by the latch 43 in the memory 41 if the leading edge of the clock pulse occurs at any other counter count than 0. This synchronization function is in the nature of a phase locked loop.

A timing diagram for the MFM encoding and decoding technique is given in FIG. 5. The curves shown in FIG. 5 are for the writing and reading of the same data as discussed with respect to FIG. 3 for the FM encoding technique. The waveforms of FIG. 5 are shown for the same points of the circuit of FIG. 1 as those in FIG. 3. Phase diagrams are given in FIGS. 6A and 6B for the MFM encoding and decoding functions, respectively, and correspond to FIGS. 4A and 4B described for the FM technique. Therefore, FIGS. 5, 6A and 6B are not extensively described.

The main differences in operation will be described for the state machine 17 when its memory is loaded with the program code of Appendix B hereto for the MFM technique. A major difference is that the duration of a bit cell is one-half of that of the FM technique since the magnetic transitions are being recorded with a double density. Every clock pulse is not recorded, as it is in the FM technique, but rather the clock's pulse is only applied to the write head if there has been a duration without a data "1" pulse exceeding some threshold amount. Bit number 5 of the state machine counter, as illustrated in FIGS. 2A and 2B, serves a function of remembering whether a "1" data pulse occurred in the last predetermined period of time so that it is known whether to write a clock pulse or not. The counter of the state machine, in this MFM implementation, need only go to 31, so only five bits are required, thereby to free up the sixth counter bit for this purpose.

It will be noticed from FIG. 1 that a double density select line 51 from the microcomputer 11 is also one of the address lines to the memory 41. The purpose of this is to select between the single density FM technique and the double density MFM technique when the program code for both are stored in the memory 41 at one time. This can be done since the two technique are similar and a portion of the program code for each is the same.

Referring to FIG. 7, a timing diagram for a five-bit GCR encoding and decoding technique is shown as implemented in the controller of FIG. 1. It shows the operation of the system when utilizing the program code of Appendix C in the memory 41 for the same bit pattern as used as an example in explaining the FM and MFM techniques with respect to FIGS. 3 and 5. A translation table between data nibbles and the five-bit combinations that are recorded on the disk are given as part of the system controlling software of Appendix D.

The RAM 41 is preferably a fast RAM 2016-1. The latch 43 may be a 74LS374, the switch 23 a 74LS298 and the converter 31 a 74LS299.

Although the present invention has been described with respect to its preferred embodiment, it will be understood that the invention is entitled to protections within the full scope of the appended claims. ##SPC1##