Process of Compressing a Succession of Digital Data and Device for Carrying Out the Same

The invention concerns a process for compressing a succession of binary digital data, especially representative of the pixels or pels (picture elements) of a digitized image; the invention also concerns a device for carrying out such process.

In a digital image acquisition system, the values of the different elementary zones of the image or pixels are transcribed into words. The value of each word represents the "brightness" of the pixel involved. For example, in the field of digital radiology, the radiological image is displayed by a brightness amplifier, intercepted by a camera and the signal of this camera is sampled. The sample sequence thus elaborated represents, for example, a line by line reading by "scanning" of the different pixels of these lines. The sample sequence is digitized, i.e. transformed into a sequence of words. If, for example, each word is coded on 8 bits, which represents a graduation from 0 to 255 from black to white and if an image is defined of 512.times.512 pixels, the memory capacity is great, i.e. 2,097,152 bits to be memorized. When numerous images have to be memorized, a mass storage is indispensable. Storing or memorizing on a magnetic disk is a method that is often used. Generally, a buffer storage of limited capacity is linked up to the mass memory, for the transfer of data. The mass storage is thus "fed" with successive readings of data contained in the buffer memory. However, due to current technological limitations the transfer of the contents of the buffer memory towards the mass storage is an operation which requires time and which restricts the performances of the system to a rhythm of images which is insufficient in certain cases, for example, if it is desired to observe rapid phenomena such as the evolution of a contrast product in the blood system or the heart. It is therefore of interest to compress the representative data of an image by exploiting the spacial and/or temporal redundancies inherent therein. The compression rate defines the gain realized after processing. Therefore, a compression rate of 2 means that the buffer memory having the capacity necessary to memorize a normal complete memory, can also recover representative data of two images, after compression. Since the transfer time between the buffer memory and the mass storage is invariable, this means that the acquisition rhythm of the images can be doubled.

A known manner of compressing a succession of digital data results from the observation that two adjacent pixels are seldom very different. Consequently, it is advantageous to memorize not the pixels X.sub.i, but the differences X.sub.i -X.sub.i-1. In fact, if the pixels X.sub.i are coded on 8 bits, i.e. 256 possible values, the difference of the two adjacent pixels can in most cases be coded on a number of bits lower than 5.

However, if a coding is specified, without loss of data, it is necessary to be able to memorize the important differences between adjacent pixels, the appearance probability of which is low but which nevertheless occur, for the details with very contrasted transitions. In order to overcome this problem, codes of variable length have already been proposed, for example, Huffman codes. Such a code results in a conversion table in which each possible difference value (between -225 and +225 for the example as mentioned herein-above) receives a binary code whose length is inversely proportional to its appearance probability Thus, the difference values that appear the most often upon coding during exploration of the image, pixel by pixel, receive the shortest codes.

The invention concerns several improvements to this type of coding.

In the first instance, the invention thus concerns a process of compressing a succession of binary digital data present in the form of fixed format words representing positive integers of an interval [O,N], comprising subtracting each word from the preceding one in such a way as to obtain each time a difference of variable format comprising a sign bit, wherein the said sign bit is suppressed from the said difference for at least certain absolute values of difference,

if the absolute value of said difference is higher than the value of the preceding word when it is comprised in the first half of the said interval or unit, or

if the absolute value of the said difference is higher than the value of the difference between the number N and the value of the preceding word when it is comprised in the second half of the said interval, and wherein

the thus compressed data is transferred, for example, towards a memory.

Another important object of this invention consists in coding directly the value of the pixel once the difference exceeds, in absolute value, a predetermined number. In fact, if pixels coded on 8 bits are considered, for example, a great difference value requires 9 bits in order to be coded, due to the sign of this difference. It thus becomes advantageous to code directly the pixel on 8 bits, since it is necessarily a positive number. In the example that will be described herein-below, the pixel (of 8 bits) is coded directly once the difference exceeds 31 in absolute value.

Furthermore, another particular object of the present invention consists in defining the given intervals of difference possible and in identifying each interval by a given tag. A suffix comprising a number of bits sufficient to represents all the absolute difference values possible in the interval involved, follows directly the tag and a supplementary bit indicates the sign. This manner of identification of the difference values has the advantage of reducing the "tree structure" of the electronic decoding circuits, i.e. the number of logic tests to be carried out prior to fully recognize a word. Thus, for example, the recognition of the tag could be exploited in order to address a table (read-only memory) directly containing all the possible difference values in the interval corresponding to the tag.

The invention also concerns a device for a compression of a succession of binary digital data present in the form of fixed format words representing positive integers of the interval (O,N) comprising a word input to which are applied the said words, a register forming the memory connected to the said input in order to memorize at each instant the value of the preceding word which is applied to the said input, and a memory to receive a succession of digital data of variable length representative of the succession of the said fixed format words, wherein: means are provided for transferring to the said buffer memory

either the absolute value of difference between the word applied to the said input and the said preceding word if the absolute value of the said difference is higher than the value of the preceding word when it is comprised in the first half of the said interval or if the absolute value of the said difference is higher than the value of the difference between the number N and the value of the preceding word when it is comprised in the second half of the said interval,

or the value of this difference and of its sign in the contrary case.

The invention will be better understood and other objects, features and advantages will appear from reading through the following description of a particular embodiment of a compression device according to the principle of the invention, given by way of non-limitative example with reference to the appended drawings in which:

FIG. 1 is a block diagram of a compression device according to the invention;

FIG. 2 is a block diagram of a sequencer of the device of FIG. 1;

FIG. 3 is a block diagram of a processing circuit of FIG. 1 for the coding of data, and

FIG. 4 illustrates the principle of the decoder.

FIG. 1 represents the block diagram of a compression circuit of a succession of words representing the pixels of an image. The words of 8 bits are present in the parallel form and are applied to an input E to undergo a compression while the digital data resulting from this compression are registered in series in a buffer memory 7. This memory is linked up to a mass storage 8 (magnetic disk system, for example), and repeated readings of the buffer memory allow to supply or "feed" the mass storage 8. The purpose of the compression is to accelerate the image acquisition rhythm, despite a relatively slow transfer rhythm between memories 7 and 8.

As mentioned herein-above, the compression process consists essentially in memorizing, not the words of 8 bits representing the pixels, but the difference between the successive pixels, by using a code of variable length. The input E is thus connected to an input Xn of the processing circuit 2 which will be described herein-below and to register 1 forming a memory the output of which is connected to an input X.sub.n-1 of processing circuit 2. This latter circuit thus receives at any moment on its two inputs the value of a pixel and that of the preceding pixel. The inputs E, Xn, X.sub.n-1 are parallel inputs of 8 bits (i.e. each presenting 8 lead-in terminals) and register 1 has parallel inputs and parallel outputs, also in 8 bits. In the figures, each parallel connection is conventionally represented by a single wire cut by an oblique stroke next to which is indicated the number of bits of the said connection. Circuit 2 comprises a parallel output C (16 bits) supplying the data (the code) to be registered, coded and "formatized" as well as a parallel output L (4 bits) supplying a representative data of the length of the code appearing simultaneously at output C. Output L is applied to an input of a sequencer 4 comprising 3 clock outputs S1, S2 and S3 respectively connected to control three registers of 8 bits, 3,5 and 6. The arrangement of sequencer 4 will be described herein-below. The output of the processing circuit 2 is connected to the input of register 3 which is of the parallel input and series output type. The sequencer decodes the information length of the code C "formatized" into 16 bits, to be transferred in series towards register 5 or register 6. More specifically, the output S1 supplies each time a number of impulses equal to the length L and this clock signal applied to register 3 controls the transfer of the corresponding most significant bits (MSB) towards register 5 or 6 which is then validated by corresponding clock S2 or S3.

For example, if the word representing a difference X.sub.n -X.sub.n-1 is equal to a+2, which can be transcribed into compressed binary code: 1100 with L=4 the "formatized" code C with 16 bits will be: 0000000000001100.

But output L programs the sequencer so that it will only generate 4 clock impulses at output S1 on order that only the word 1100 is registered in one of the registers 5 or 6. The format adopted of 16 bits, for code C corresponds to the maximum length of the words to be transferred in the memory 7.

The series output S4 of the register 3 is connected to inputs E.sub.1 and E.sub.2 of the registers 5 and 6, respectively. These registers are of the series input-parallel output type. Two outputs S.sub.5, S.sub.6 of these registers are connected to a parallel input E.sub.3 of memory 7 which comprises furthermore, an addressing input Ad controlled by a sequencer 4. The presence of registers 5 and 6 is justified by the fact that the memory is disposed in a manner known per se in addressable words of 8 bits. Therefore, the available clocks at outputs S2 and S3 validate alternately registers 5 and 6. Each time that a register 5 (or 6) has received 8 bits issuing from register 3, the sequencer switches the succession of the unloading of register 3 towards the other register 6 (or 5). At the same time, it generates the address of memory 7 to which register 5 (or 6) must be unloaded.

The sequencer is represented in FIG. 2. It comprises a clock generator H that controls a down counter 9 having parallel reference input, connected at output L of circuit 2 and receiving consequently a word representative of the length of the code. The clock generator H is simultaneously connected to an input of an AND gate 10 having two inputs and the output of which constitutes the output S1 controlling register 3. Down counter 9 comprises an output S.sub.9 called "zero state" output which changes state when clock H has put the counter back to zero, i.e. when it has supplied a number of impulses corresponding to the length L displayed at the reference input. This output S.sub.9 is connected to the other input of gate 10. Its change of state blocks the gate and thus interrupts the transmission of clock impulses to output S.sub.1. The output of AND gate 10 is also connected to the input of an adder 11. This counter is an eight counter which controls a flip-flop circuit 12 and an address counter 13. The output of this latter constitutes the output Ad which controls a memory 7. The output Q of circuit 12 is connected to an input of an AND gate 14, having two inputs, while its output Q is connected to an input of an AND gate 15 having two inputs. The two other inputs of gates 14 and 15 are connected to output S.sub.1. The outputs of gates 14 and 15 constitute the outputs S.sub.2 and S.sub.3 mentioned herein-above. Therefore, each time that counter 11 has registered 8 clock impulses H transmitted by gate 10, it controls the change of state of the circuit 12, which inverses the validation for registers 5 and 6 for the loading of the data supplied by counter 3. At the same time, counter 11 increases address counter 13 by one unit, for the transfer of data contained in the register which has just been "filled" to a new address of memory 7.

Prior to setting out the description of processing circuit 2 which carries out the essential of the compression operations of the representative data of pixels X.sub.i, the processing of coding selected should be explained.

For D.sub.n, the difference between two consecutive pixels:

since X.sub.n and X.sub.n-1 are whole integers comprised within a predeterminated positive interval (0 to 255), D.sub.n is comprised within the interval (-255+255). By way of non-limitative example, the conversion of the possible values D.sub.n into binary code can be in accordance with the following table:

It is verified that D.sub.n =0, i.e. that the value of difference statistically occuring the most often in the succession of the pixels of the image, is coded with the word of minimal length, i.e. on one bit. The other fairly probable values of difference like for example .+-.1, .+-.2, only require three or four bits. The greatest values of difference (like, for example, the interval +16 to +31) require up to 12 bits but their appearance probability is very low so that this has very little effect on the compression rate obtained. In the code, the last bit S represents the sign, for example S=0 if the difference D.sub.n is positive and S=1 if D.sub.n is negative. As will be seen herein-below, the sign bit can, in certain cases, be removed.

Furthermore according to one advantageous aspect of the invention and from an absolute value of difference higher than 7, the code words are disposed with an identification tag and a suffix as well as (possibly) a sign bit S. The identification tag designates a predetermined interval of absolute values of differences. For example, for the double interval of difference (.+-.8 to .+-.15), a first tag 111110 is defined, for the double interval of differences (.+-.16 to .+-.31) a second tag 1111110 is defined, and for the double interval of differences (.+-.32 to .+-.255) a third tag 1111111 is defined. It will be noted that the suffix XYZ comprises a sufficient number of bits (three) to represent all the absolute values of differences possible in the interval (.+-.8 to .+-.15) since 3 bits allow 8 binary combinations. The same is true for the interval (.+-.16 to .+-.31), the suffix of which comprises 4 bits: XYZT. On the other hand, according to one advantageous feature of the invention, the fixed format word representing the pixel is directly transferred towards the buffer memory 7 when the absolute value of the difference between this word and the preceding one exceeds a selected number. According to the example, this selected number is 31 which means that for the double interval of differences (.+-.32 to .+-.255) the ABCDEFGH suffix represents the value itself of the pixel. In fact, beyond 31, the coding of the difference would require more bits, taking into consideration the necessity of coding the sign S, than the coding of the pixel itself (which is always positive). A third identification tag, namely 1111111 is associated to this suffix.

According to one important characteristic of the invention, the sign bit S is suppressed at the coding each time that this is possible. It should be noted that the conditions for supressing sign bit S, such as explained herein-below, can be applied theoretically on the total interval of possible values of difference (i.e. -255 to +255), but that, due to direct pixel coding in double interval (.+-.32 to .+-.255), these conditions have meaning only for complementary interval (-31 to +31) not comprising zero. The following examples allow to understand the conditions for supressing sign bit S.

0.ltoreq.X.sub.i .ltoreq.N is still relevant, according to the example 0.ltoreq.X.sub.i .ltoreq.255

(a) It is supposed that X.sub.n-1 =0 whatever the value of the pixel following X.sub.n, the difference: D.sub.n =X.sub.n -X.sub.n-1 is obligatory positive. The sign S of D.sub.n can thus be supressed in every case;

(b) it is supposed that X.sub.n-1 =1, the only possible negative difference is -1, it is thus necessary to code .+-.1 on 3 bits by maintaining the sign bit.

For all other difference values sign bit S can be removed from D.sub.n ;

(c) it is supposed that X.sub.n-1 =2, the only possible negative differences are -1 and -2. In order to remove the indetermination, it is thus necessary to code .+-.1 and .+-.2 by maintaining the sign bit S. For all other values of differences, bit sign S can be removed from D.sub.n. This reasoning can be continued for all the values of the penultimate pixel X.sub.n-1 comprised in the first half of the variation interval of the pixels X.sub.i. In other words, the sign bit S is removed if the absolute value of difference D is higher than the penultimate word when it is comprised in the first half of the interval of the X.sub.i. In fact, for the reason mentioned herein-above, this type of test will be stopped once the absolute value of difference is higher than 31;

(d) it is now supposed that X.sub.n-1 =N=255, whatever the value of the following pixel X.sub.n, the difference D.sub.n =X.sub.n -X.sub.n-1 is necessarily negative. The sign S of D.sub.n can also be supressed in every case;

(e) it is supposed that X.sub.n-1 =254, the only possible positive difference is +1 if X.sub.n =+255. In order to remove this indetermination the differences D.sub.n =.+-.1 are coded on 3 bits while maintaining the sign bit. For every other value of difference, bit S can be removed from D.sub.n ;

(f) it is supposed that X.sub.n-1 =253, the only possible positive differences are .+-.1 and .+-.2 corresponding to X.sub.n =254 or X.sub.n =255. The differences .+-.1 and .+-.2 are thus coded while maintaining the sign bit S.

For all the other values of difference, sign bit S can be removed from D.sub.n.

This reasoning can be continued for all the values of the penultimate pixel X.sub.n-1 comprised within the second half of the variation interval of the pixels X.sub.i. In other words, the sign bit is removed if the absolute value of difference D.sub.n is higher than the value of the difference between the number N (N=255) and the value of the penultimate pixel X.sub.n-1, when it is comprised in the second half of the variation interval of the pixels X.sub.i. There again, however, this type of test is abandoned once the difference becomes higher than 31.

A possible embodiment of a processing circuit will now be described with reference to FIG. 3. The inputs X.sub.n and X.sub.n-1 are directly connected to the inputs of a digital subtractor 20 the parallel output D.sub.n (on 9 bits) of which supplies at every instant the value of the difference: D.sub.n =X.sub.n -X.sub.n-1

It is possible, for example, to utilize an available integrated circuit of the ALU 4 bits type (TTL 181) proposed by the major manufacturers of semi-conductors. Since the binary representation utilized in the subtractor is a complementary representation in two, a preprogrammable read-only memory (PROM) 21 is used to extract the absolute value of difference. The absolute value appears coded on 8 bits, at a parallel output S.sub.5 of the memory 21 and the sign bit appears at an output S.sub.6 of the subtractor 20. The read-only memory 21 is addressed directly by the output D.sub.n, i.e. the parallel output D.sub.n of the subtractor 20 is connected to an addressing input of the read-only memory, each value of D.sub.n constituting an addressing of the memory 21 in which is registered the corresponding absolute value. The capacity of the memory 21 is reduced since it must contain 512 words of 8 bits. It is possible, for example, to utilize a 82S115 type integrated circuit proposed by the major manufacturers of semi-conductors; a single chip is sufficient in order to realize the memory 21. The programming of this latter memory is within the knowledge of those skilled in the art.

The output S.sub.5 and the output X.sub.n-1 are also connected to two inputs (of the parallel 8 bits type) of a digital adder 22 and to two inputs of a digital subtractor 23, so as to realize the following operations:

Circuits 22 and 23 can be realized from the same type of integrated circuit as the subtractor 20. The "carry over" output S.sub.8 of adder 22 and the "carry over" output S.sub.9 of the substractor 23 are connected respectively to the two inputs of an exclusive OR gate 25. In other words, output S.sub.8 displays the value of the report bit of the operation X.sub.n-1 +.vertline.D.sub.n .vertline. while output S.sub.9 displays the value of the report bit of the operation X.sub.n-1 -.vertline.D.sub.n .vertline.. The assembly 22,23,25 which has just been described carries out in a simple manner the whole of the tests (defined herein-above) allowing to determine that, if the sign bit can be suppressed or not. In fact, it is verified whether the two values:

X.sub.n-1 +.vertline.D.sub.n .vertline. and X.sub.n-1 -.vertline.D.sub.n .vertline. are within the interval (O,N), this means that the sign must be taken into consideration in the transmission of the code C towards the buffer memory. If, on the other hand, a value is present outside the interval (O,N), this means that it is possible to supress the sign bit. These conditions are set forth in the truth table of gate 25, since, if the output of this gate reaches 1, this means that only one of the "carry over" bits has a value 1, i.e. that the result of only one of the operations is outside the interval (O,N).

Furthermore, the output S.sub.5 is connected to a comparator 26 which allows to determine whether the absolute value of difference D.sub.n is higher or lower than 31. Practically, this comparator can be a simple OR gate having three inputs to which are connected the three last terminals of output S.sub.5 (on which appear the most significant bits). Since the number 31 is expressed in binary code as: 00011111, a higher number will necessarily have at least one of its most significant bits MSB equal to 1. The output of this gate is connected to a control input e.sub.5 of a multiplexer 27 the outputs L and C of which are the outputs represented in FIG. 2. This multiplexer comprises two inputs L.sub.1, C.sub.1 and L.sub.2, C.sub.2 respectively and its function consists simply in causing to correspond the inputs L.sub.1, C.sub.1 or L.sub.2, C.sub.2, the outputs L, C as a function of the control applied to input e.sub.5. Input L.sub.1 is fixed and expresses the number 15 in binary code, the 8 terminals corresponding to the least significant bits LSB of input C.sub.1 receive directly the word X.sub.n while the 7 terminals corresponding to the most significant bits MSB of this same input C.sub.1 are all at 1. Therefore, the double transcription Length-Code is simply carried out in the case where the value of the difference belongs to a double interval (.+-.32 to .+-.255) identified by comparator 26. The multiplexer 27 can be, for example, realized from a 74244 type integrated circuit.

Output S.sub.5 of the read-only memory 21 is itself connected to the addressing input of a read-only memory 29 in which are registered the 256 possibilities for the length L and the value of code C, without the sign S, designated respectively by L* and C* corresponding to the different possible values of the output S.sub.5. Since code C* requires 11 bits and length L* requires 4, read-only memory 29 only requires three 82S115 chips. Its addressing programming corresponds to the correspondence table described herein-above, except with respect to the double interval (.+-.32 to .+-.255) and the sign bit S which does not appear. Outputs C* and L* are connected to the corresponding inputs of a multiplexer 30 of the same type as multiplexer 27. The outputs of multiplexer 30 are connected to inputs L.sub.2, C.sub.2 of multiplexer 27. The function of multiplexer 30 is therefore to connect either the group of inputs L.sub.0 *, C.sub.0 * or the group of inputs L.sub.0 **, C.sub.0 ** to the corresponding inputs L.sub.2, C.sub.2. Control input e.sub.6 of multiplexer 30 is connected to the output of the exclusive OR type gate 25. Input L.sub.0 ** is connected to output L of read-only memory 29 through the intermediary of a binary operator 32 which carries out the following operation:

this incrementation thus allows to calculate the new length of the code when the sign S is reintroduced. Input C.sub.0 ** is connected to output C* of the memory 29 and comprises a supplementary terminal connected to the output S.sub.6 of subtractor 20. The control signal applied to input e.sub.6 thus allows to select either inputs L.sub.0 *, C.sub.0 * when the sign bit S can be suppressed, or inputs L.sub.0 **, C.sub.0 ** when it must be maintained. It is possible to provide a register 33 between multiplexer 30 and input C.sub.2 of multiplexer 27 in order to "formatize" the data code to 15 bits, the register being controlled by the length data simultaneously transmitted to input L.sub.2.

The operating of the processing circuit of FIG. 3 becomes apparent from reading its description. It can be seen that for all the pairs of pixels X.sub.n, X.sub.n-1, the difference D.sub.n (subtractor 20) is systematically determined, then the absolute value of D.sub.n is classified with reference to the said "selected numbers", i.e. 31, due to comparator 26. This classification allows to position multiplexer 27, i.e. to transmit possibly the word X and its length towards outputs L and C of multiplexer if .vertline.D.sub.n .vertline.>31. In the opposite case, the sign of the difference is suppressed whenever possible, which is made evident by the positioning of the multiplexer 30 under the control of gate 25. If the sign can be suppressed, outputs L*, C* of the memory 29 become the outputs L, C of the system. In the opposite case, they are completed so as to reintroduce the sign available at output S.sub.6.

It is well understood that circuit 2 which has just been described, is available to many variants known to those skilled in the art. Among these it is henceforth advantageous taking into consideration the read-only memories offered in the trade to replace the whole of the circuit by a single programmable read-only memory (PROM) addressed directly by the values X.sub.n and X.sub.n-1. In other words, by referring once again to FIG. 1, block 2 can be a simple read-only memory. If the inputs X.sub.n and X.sub.n-1 are each coded on 8 bits, which is assimilable to a parallel addressing input of 16 bits for the read-only memory, there are thus 65536 possible combinations, which means 64K words of 15 bits for code C and 64K words of 4 bits for code L. If for example 27128 type integrated circuits are used, which have each a memory capacity of 16K octets, it is sufficient to utilize eight chips to register once and for all the 64K values possible of code C, and four chips to register the 64K values of length L.

The programming of this read-only memory is within the knowledge of those skilled in the art. It is possible, for example, to simulate the system represented in FIG. 3 on a computer by successively generating all the possible values for X.sub.n and X.sub.n-1. It is also possible to construct the system shown in FIG. 3 so as to utilize it as a programmer for the PROM.

Consequently, the present invention also concerns all compressing processes in which the codings of the words L and C result only from a simple reading operation in a memory, once this memory has been programmed by carrying out the operations and the tests described herein-above.

The decoding will now be briefly explained. Each point of the "tree structure" of FIG. 4 symbolizes a logic test between 0 and 1. The sequence of the bits representing the data after commpression is applied to the input E.sub.0, the first pixel having been coded as such. Consequently, if the following bit is zero, it is considered that D.sub.n =0 is achieved. On the other hand, an incoming bit 1 requires a supplementary test. If the following bit is 0, thus .vertline.D.sub.n .vertline.=1. On the contrary if this bit is still 1, the process is continued in the tree structure in order to be able to recognize .vertline.D.sub.n .vertline.=2 if the following bit is zero and so on . . . . Beyond .vertline.D.sub.n .vertline.=7, the tree structure is limited, due to the use of tables (read-only memories) containing all the possible combinations of the absolute values of differences comprised in the intervals [8 to 15], [16 to 31] and [32 to 255]. Thus the recognition of five consecutive 1 followed by a zero provokes the addressing of memory M.sub.1 (corresponding to the first interval) by the three following bits. The recognition of six consecutive ones followed by a zero initiates the addressing of memory M.sub.2 (corresponding to the second interval) by the four following bits, and the recognition of seven consecutive 1 initiates the addressing of memory M.sub.3 (corresponding to the third interval) by the following eight bits.

A circuit carrying out the tree structure represented in FIG. 4 can be simply realized from flip-flop circuits and the said read-only memories M.sub.1, M.sub.2 and M.sub.3. It will be observed that the succession of the bits at input E.sub.0 thus conditions the recognition of the absolute value of the difference .vertline.D.sub.n .vertline..

If the value of the preceding pixel is memorized, it is simple to repeat the operations:

in the same manner as that described with reference to FIG. 3. Once the results R+ and R- of these two operations are available, it is sufficient to check whether R+ and/or R- fall within the interval (O,N). If one single value is within the interval (O,N) it is sufficient to take this value as X.sub.n. If, on the other hand, the two values R+ and R- are within the interval (O,N) it is necessary to call up the following bit which is present at input E.sub.0, in order to remove the indetermination and complete .vertline.D.sub.n .vertline. by its sign. The very value of the sign S allows to select the correct value of X.sub.n between R+ and R-. If S=0, this means that the difference is positive and the correct value of X.sub.n is R+. If S=1, this means that the difference D.sub.n is negative and that the correct value of X.sub.n is R-.