Graphic Processor for Color and Positional Data of an Image to Be Displayed

The present invention relates to a graphic processor for producing pattern display data for use in, for example, a CRT display device.

In a pattern display system for displaying a pattern by a group of dots, a straight line is displayed by a line of dots such as shown in FIG. 1. FIG. 1 shows the case where a display plane is divided into 1024 equal parts in each of transverse and longitudinal directions, namely, in the direction of each of X- and Y-axes. In FIG. 1, coordinates are assigned to the display plane in such a manner that divisions placed in the upper left, upper right, lower left and lower right corners have coordinates (0, 0), (1023, 0), (0, 1023) and (1023, 1023), respectively. The so-called refresh memory has memory areas which correspond to divisions on the display plane in a one-to-one relation and store display data. The refresh memory is accessed in synchronism with the scanning operation in a CRT display device.

A graphic processor shown in FIG. 2 has hitherto been used to display patterns. Referring to FIG. 2, a vector generator 1 converts a line segment to be displayed into a line of dots, and sets the X- and Y-coordinates of each dot in an X-address register 2 and a Y-address register 3, respectively. The vector generator 1 delivers not only the above-mentioned X- and Y-coordinates but also pattern data indicating the color of the line segment. The pattern data from the vector generator 1 is not supplied to a refresh memory 5 but is written in a refresh memory buffer (hereinafter simply referred to as "buffer") 4 at a position specified by the lower n bits of each of the X-address register 2 and Y-address register 3. The buffer 4 has a pattern data storing area corresponding to that partial region on the display face of the CRT which is formed of 2.sup.n .times.2.sup.n dots (for example, n=3). When the vector generator 1 generates pattern data in a different partial region in addition to pattern data in a desired partial region, an overflow detecting circuit 6 detects such a situation, and the pattern data stored in the buffer 4 (and corresponding to 2.sup.n .times.2.sup.n dots) is written in the refresh memory 5 in parallel. Thereafter, the same operation is performed for each of the other partial regions, and pattern data is successively written in the refresh memory 5. Thus, all of the pattern data to be displayed on the display face are written in the refresh memory 5. The buffer 4 is provided to eliminate the waiting time of the vector generator 1 caused by the low writing speed for the refresh memory 5. In more detail, since the operating speed of the vector generator 1 is higher than that of the refresh memory 5, the output of the vector generator 1 is temporarily stored in the buffer 4, and then the contents of the buffer 4 are written in the refresh memory 5 in parallel, thereby preventing the vector generator 1 from being stopped.

According to such a prior art device, however, when a pattern is displayed in a plurality of colors, a plurality of bits are necessary for indicating the kind of color, and a number of buffers equal to the number of colors are required.

Further, in the prior art, pattern data corresponding to 2.sup.n .times.2.sup.n dots are written in a partial area of the refresh memory 5 in parallel, and therefore pattern data having already been written in the partial area are erased by new pattern data being written.

Furthermore, when pattern data overflows the buffer 4 and the contents of the buffer 4 are transferred to the refresh memory 5 in parallel, the buffer 4 must hold the pattern data till all of the pattern data in the buffer 4 has been written in the refresh memory 5. The writing operation of the vector generator 1 for the buffer 4 is stopped for this period, and therefore an undesirable waiting time is required.

In addition, in the case where pattern data is written in only an edge portion of the buffer 5, an overflow is caused by writing the pattern data of only a few dots in the buffer, and thus a writing operation for the refresh memory 5 is required. Accordingly, the vector generator 1 must wait till the writing operation for the refresh memory 5 is completed, and is kept at the stand-by state for a longer time than the operating time thereof.

A first object of the present invention is to provide a graphic processor which can write pattern data for color display in a refresh memory by using a buffer with a smaller capacity.

A second object of the present invention is to provide a graphic processor which can write new pattern data in a refresh memory without erasing pattern data stored therein.

A third object of the present invention is to provide a graphic processor which can operate a vector generator without having any waiting time, for a period when pattern data is sent from a buffer to a refresh memory to be written therein.

A fourth object of the present invention is to provide a graphic processor which can operate a vector generator without having any waiting time, even if a writing operation for a refresh memory is required in the state that pattern data has been written in only an edge portion of a buffer.

In order to attain these objects, according to the present invention, there is provided a graphic processor in which pattern data sent out from a vector generator is stored in a data register, positions at which the pattern data is to be written in a refresh memory, are stored in a buffer, and the pattern data from the data register is written in the refresh memory at positions stored in the buffer.

FIG. 1 shows the display state of a straight line on a conventional display plane.

FIG. 2 is a block diagram showing a conventional graphic processor.

FIG. 3 is a block diagram showing an embodiment of a graphic processor according to the present invention.

FIG. 4 shows how a display plane is divided in the embodiment of FIG. 3.

FIG. 5 shows an address arrangement in each of random access memories (RAM's) making up the refresh memory shown in FIG. 3.

FIG. 6 is a circuit diagram showing the circuit configuration of one of the buffers shown in FIG. 3.

FIG. 7 is a block diagram showing the circuit configuration of the refresh memory shown in FIG. 3.

FIG. 8 shows a straight line extending over three display blocks which is displayed by the embodiment shown in FIG. 3.

FIG. 9 is a timing chart for explaining the operation of the embodiment shown in FIG. 3.

FIG. 3 shows an embodiment of a graphic processor according to the present invention. Prior to explaining the embodiment shown in FIG. 3, a display plane used in the present embodiment will be explained, with reference to FIG. 4. Referring to FIG. 4, a display plane 50 is formed of 128.times.128 display blocks 7, and each display block 7 is formed of 8.times.8 dots. That is, the display plane 50 is formed of 1,024.times.1,024 dots. In other words, 128 display blocks are arranged in each of X- and Y-directions of the display plane, respectively, and thus 16,384 display blocks are included in the display plane. These display blocks are given coordinates in such a manner that a block occupying the upper left corner of the display plane, a block occupying the upper right corner, a block occupying the lower left corner and a block occupying the lower right corner have coordinates B(0, 0), B(127, 0), B(0, 127) and B(127, 127), respectively. Further, the dots are given coordinates in such a manner that a dot 47 occupying the upper left corner of the block having the coordinate B(0, 0) and a dot 49 occupying the lower right corner of the block having the coordinate B(127, 127) have coordinates D(0, 0) and D(1,023, 1,023), respectively. As a result, a display block having a coordinate B(n, m) includes 64 dots having coordinates D(8n, 8m) to D(8n+7, 8m+7).

When a RAM of 16,384.times.one bit structure is used for forming a refresh memory having 1,024.times.1,024 bits, 64 RAM's are required. FIG. 5 shows an address arrangement in the case where a refresh memory is made up of 64 RAM's. Referring to FIG. 5, 64 RAM's are arranged to correspond to 64 dots making up one display block 7. Further, coordinates D(0, 0), D(8, 0), . . . D(1,016, 1,016) indicating the dot placed in the upper left corner of each display block are all stored in an RAM (0, 0) which is placed in the upper left corner of FIG. 5, and coordinates D(1, 0), D(9, 0) . . . and D(1,017, 1,016) indicating the second dot from the upper left corner of each display block are all stored in the second RAM(1, 0) from the upper left corner of FIG. 5. All of the addresses of 64 dots are arranged in 64 RAM's in a similar manner. Thus, the addresses of 64 dots forming a given display block are stored in the RAM's 8, and 64 dots can be written in the 64 RAMs 8 at the above addresses at one time. Such a writing operation will be explained later in detail, with reference to FIG. 7.

Referring back to FIG. 3, a clock generator 48 delivers clock pulses 41, and a write pulse 42 which will be explained later. The write pulse 42 is generated each time four clock pulses have been generated, as shown in FIG. 9. The vector generator 1 receives the clock pulses 41, and delivers a signal indicating respective positions of dots which represent a plurality of line segments forming a pattern to be displayed, in synchronism with the clock pulses 41. In more detail, 10-bit data indicating the X-coordinate of the first dot representative of the starting point of a line segment and 10-bit data indicating the Y-coordinate of the first dot are set in an X-address register 2 and a Y-address register 3, respectively. As regards the coordinates of the second, third, . . . and final dots on the same line segment, an increment (UP) signal or decrement (DN) signal indicating a difference in X-coordinate between a dot and the next dot is given to a lower X-register 2B, and a similar UP- or DN-signal with respect to Y-coordinate is given to a lower Y-register 3B. The vector generator 1 delivers the UP- or DN-signal with respect to each of the X- and Y-coordinates one after another in synchronism with the clock pulses 41. The Y-address register 3 includes an upper Y-register 3A and the lower Y-register 3B, and the X-address register 2 includes an upper X-register 2A and the lower X-register 2B. Each of the lower Y-register 3B and lower X-register 2B has 3 bits, and each of the upper Y-register 3A and upper X-register 2A has 7 bits. Each of the X-address register 2 and Y-address register 3 is formed of an up/down counter. The lower registers of the address registers 2 and 3, that is, the lower X-register 2B and the lower Y-register 3B count up or down according to whether they receive the UP-signal or DN-signal from the vector generator 1. A carry signal 13 and a borrow signal 14 each sent out from the lower Y-register 3B, are supplied to the upper Y-register 3A and a buffer control circuit 17. Similarly, a carry signal 15 and a borrow signal 16 each sent out from the lower X-register 2B are supplied to the upper X-register 2A and buffer control circuit 17. The buffer control circuit 17 controls a selector 20 for the outputs 35 and 36 of buffers 18 and 19. While, the output of the lower Y-register 3B is applied to decoders 9 and 11, and the output of the lower X-register 2B is applied to decoders 10 and 12. Data from the decoders 9 to 12 are written in the buffers 18 and 19. The decoders 9 and 11 decode a 3-bit signal from the lower Y-register 3B. An 8-bit output 28 from the decoder 9 is set in the buffer 18 or an 8-bit output 30 from the decoder 11 is set in the buffer 19, according to whether an enable input 21 or 22 is set. The decoders 10 and 12 decode a 3-bit signal from the lower X-register 2B. An 8-bit output 29 from the decoder 10 is set in the buffer 18 or an 8-bit output 31 from the decoder 12 is set in the buffer 19, according as the enable input 21 or 22 is set.

The enable inputs 21 and 22 are given by the Q- and Q-outputs of the buffer control circuit 17, respectively. The enable input 21 is also applied to the selector 20. When the enable input 21 is set, the output 36 of the buffer 19 is taken out as a selective output 37. When the enable input 21 is reset, the output 35 of the buffer 18 is used as the selective output 37. Thus, the buffers 18 and 19 are alternately put in a writing state, in other words, one and the other of the buffers 18 and 19 are put in writing and reading states, respectively.

The outputs of the upper X-register 2A and upper Y-register 3A are applied through address latches 23 and 24 to a refresh memory 5, to determine an address thereon. The address latches 23 and 24 latch the outputs of the upper X-register 2A and upper Y-register 3A, respectively, at the falling edge of the write pulse 42.

The buffer control circuit 17 is made up of an OR gate 25 and a flip-flop 26. The carry signal 13 and borrow signal 14 from the lower Y-register 3B as well as the carry signal 15 and borrow signal 16 from the lower X-register 2B are applied to the OR gate 25, the output of which is supplied to a trigger input of the flip-flop 26, to invert both the outputs Q and Q of the flip-flop 26. The buffer control circuit 17 makes it possible to detect that an X- or Y-coordinate value is outside the range of the buffer in one of the buffers 18 and 19.

An AND gate 38 is connected to receive the selective output 37 and write pulse 42, and the output of the AND gate 38 is supplied to the refresh memory 5.

While, pattern data indicating a pattern to be displayed is previously sent out from the vector generator 1 and written in a data register 27. For black-and-white display, the data register 27 stores only one bit of value one. For color display, the register 27 is required to have a plurality of bits indicating the kind of color of a pattern to be displayed. It is a matter of course that a plurality of refresh memory planes equal in number to the above-mentioned bits are required for color display. In the present embodiment, one bit is used for indicating pattern data, for brevity.

The writing and reading operations for the buffers 18 and 19, the selection of data to be written in the refresh memory 5, and the setting of positions at which data is written in the refresh memory 5, are carried out in the above-mentioned manner. The timing of this processing will be explained later, with reference to FIG. 9.

Next, the structure of each buffer and that of the refresh memory will be explained in detail.

Signals YA0 to YA7 forming the 8-bit output 28 of the decoder 9 and signals XA0 to XA7 forming the 8-bit output 29 of the decoder 10 are applied to the buffer 18. While, signals YB0 to YB7 forming the 8-bit output 30 of the decoder 11 and signals XB0 to XB7 forming the 8-bit output 31 of the decoder 12 are applied to the buffer 19.

Since the buffers 18 and 19 have the same structure, the circuit configuration of the buffer 18 is shown in FIG. 6, by way of example. Referring to FIG. 6, the buffer 18 includes 64 flip-flops 32, 64 AND gates 33, and a differentiating circuit 34. The differentiating circuit 34 is connected to the reset terminal R of each flip-flop, and resets all of 64 flip-flops at the moment the output 21 of the buffer control circuit 17 takes the level of "1", that is, the moment the writing operation for the buffer 18 is started.

Now, let us assume that the signals YA0 and XA0 are set, then, only a flip-flop occupying the upper left corner is set and the other 63 flip-flops are not set. When the vector generator 1 specifies another dot position, only a different flip-flop corresponding to the specified dot position is set. The outputs 35 of the flip-flops are designated by 64 reference symbols RMBA(0, 0) to RMBA(7, 7). For the buffer 19, the signals YB0 to YB7 are used in place of the signals YA0 to YA7, the signals XB0 to XB7 are used in place of the signals XA0 to XA7, outputs RMBB(0, 0) to RMBB(7, 7) are substituted for the outputs RMBA(0, 0) to RMBA(7, 7) of the flip-flops, and the output 22 of the buffer control circuit 17 is applied to the differentiating circuit 34 in place of the output 21.

The outputs of the flip-flops are sent to the selector 20. Either the outputs RMBA(0, 0) to RMBA(7, 7) or outputs RMBB(0, 0) to RMBB(7, 7) from one of the buffers 18 and 19 which is now subjected to a reading operation, are selectively sent from the selector 20 to the refresh memory 5.

As shown in FIG. 3, the selector 20 selects the output 35 of the buffer 18 or the output 36 of the buffer 19 according to the level of "0" or "1" at the output Q of the flip-flop 26, so as to attain selective output 37 including 64 signals SEL(0, 0) to SEL(7, 7).

FIG. 7 shows details of the refresh memory 5 and its periphery. The selective output 37 from the selector 20 acts as a write enable signal WE for each RAM (that is, each memory element) 8. The data input terminals Di of 64 memory elements are all connected to the data register 27, which holds therein data to be written in the refresh memory 5. This data is sent to all of the memory elements, but is written in only some memory elements which are specified using the write enable signals SEL (0, 0) to SEL(7, 7). The remaining memory elements are left unchanged, that is, the contents of each of the remaining memory elements are kept unchanged. Thus, data is written in memory portions corresponding to one display block 7 at one time.

In order to clarify the details of the above processing, let us consider the case where a straight line shown in FIG. 8 is written in the refresh memory 5. The straight line starts with a display block having a coordinate B(n, m), and is directed toward the upper right. Two display blocks whose X- or Y-coordinates differ by one from each other, are called adjacent display blocks for example B(n, m) and B(n+1, m). The number of dots required for expressing the straight line in the pair of adjacent display blocks is equal to or less than 8. In other words, not more than eight dots are written in such adjacent memory blocks.

That is, it is required to update eight dots or less in the buffers 18 and 19. Now, let us consider the case where an access time T.sub.2 to the refresh memory 5 is four times longer than a time T.sub.1 necessary for the vector generator 1 to determine the address of one dot, that is, T.sub.2 =4T.sub.1. It takes a time 8T.sub.2 to determine the addresses of eight dots. While, a time 2T.sub.2 is required to write 8 dot positions from the buffers 18 and 19 in the refresh memory 5. However, since the time T.sub.2 is equal to the time 4T.sub.1, the time required for determining the addresses of eight dots is equal to the time required for writing 8 dot positions in the refresh memory 5. Thus, each of the writing operation for the buffers and the writing operation for the refresh memory is duly performed. This will be depicted in the time charts shown in FIG. 9.

A waveform (a) in FIG. 9 shows reference clock pulses 41 supplied to the vector generator 1. The vector generator 1 delivers dot position signals successively in synchronism with the clock pulses 41. Now, let us consider the case where dot data in a display block having a coordinate B(n, m) is written in the buffer 18. The X- and Y-coordinates of a dot a in the above display block are outputted from the vector generator 1 in a period t.sub.1. At this time, the contents of the upper Y-register 3A are made equal to m as shown in (b) of FIG. 9, and the contents of the upper X-register 2A are made equal to n as shown in (c) of FIG. 9. A flip-flop which is included in the buffer 18 and delivers the output RMBA(2, 7), is set by the decoders 9 and 10. Similarly, contiguous dots are successively set in the buffer 18, and finally a dot b is set in a flip-flop which is included in the buffer 18 and delivers the output RMBA(7, 2), in a period t.sub.2, as shown in (e) of FIG. 9.

Immediately thereafter, a carry from the lower X-register 2B is generated. As a result, the OR gate 25 delivers a pulse as shown in (d) of FIG. 9, to invert the outputs Q and Q of the flip-flop 26. That is, dots are now written in the buffer 19, and the output 35 of the buffer 18 passes through the selector 20 to be used as the selective output 37 as shown in (i) of FIG. 9.

Next, in a period t.sub.3, a dot c in a display block having a coordinate B(n+1, m) is set in a flip-flop which is included in the buffer 19 and delivers the output RMBB(0, 1), by the decoders 11 and 12, and the contents of the upper X-register 2A are changed to (n+1) as shown in (c) of FIG. 9. Similarly, the next dot d in the display block having the coordinate B(n+1, m) is set in the buffer 19 in a period t.sub.4 as shown in (f) of FIG. 9.

The write pulse 42 is generated in a period corresponding to every fourth pulse interval of the clock pulses 41 (for example, in the latter half of the period t.sub.a), as shown in (g) of FIG. 9. The write pulse 42 is supplied to the AND gate 38, to allow the selective output 37 to be written in the refresh memory 5. In the period t.sub.a however, a zero is written in the refresh memory 5 by the write pulse 42, since the data register 27 is not yet set. The contents of each of the upper X-register 2A and upper Y-register 3A are latched at the falling edge of the write pulse 42 generated in the latter half of the period t.sub.a, as shown in (h) of FIG. 9.

The write pulse 42 is also generated in the latter half of the period t.sub.4. At this time, the data register 27 has been set. Accordingly, data on the data register, i.e. 1 is written in each of memory elements 8 which are specified by the output 35 of the buffer 18 acting as the selective output 37, at an address specified by the latches 23 and 24. Thereafter, the buffers 18 and 19 are alternately operated in the above-mentioned manner.

In the foregoing description, explanation has been made on the case where a straight line is stored in the refresh memory 5. At the final stage, data in the refresh memory 5 is sent to a CRT monitor dot by dot, to be displayed thereon. The final stage will be briefly explained below. Referring back to FIG. 7, a display counter 86 has 20 bits, and is divided into four parts, that is, a first part including the zero-th to second bits, a second part including the third to ninth bits, a third part including the tenth to twelfth bits, and a fourth part including the thirteenth to nineteenth bits. The first, second, third and fourth parts are hereinafter referred to as a counter 83, a counter 82, a counter 81 and a counter 80, respectively. The display counter 86 counts up pulses which are generated by a timing generator 79 at a fixed time interval. The counters 80, 81, 82 and 83 hold upper 7 bits of an address in the direction of Y-axis, lower 3 bits of this Y-address, upper 7 bits of an address in the direction of X-axis, and lower 3 bits of the X-address, respectively. The outputs of the counters 80 and 82 are applied to a multiplexer (hereinafter simply referred to as "MPX") 84. The MPX 84 selects the outputs of the counters 80 and 82 for its output during the time the vector generator 1 delivers no coordinates of a dot. The output of the counter 81 is applied to the select input terminal of each of the MPX's 70 to 77. Of data read out of the memory elements arranged in the form of an 8.times.8 matrix, 8-dot data in a row specified by the counter 81 is outputted from the MPX's 70 to 77. The outputted data is applied to an 8-input, 1-output MPX 78. The output of the counter 83 is applied, as a select signal, to the MPX 78. Accordingly, of eight dots supplied to the MPX 78, only a dot in a column specified by the counter 83 is sent to the CRT monitor through a signal line 85. Thus, one dot is sent from the MPX 78 to the CRT monitor each time one pulse is generated by the timing generator 79, in such a manner that a raster scan is carried out.

As mentioned previously, even when a writing operation for the refresh memory 5 is performed, the vector generator 1 continues to operate, to expedite the data processing.

As has been explained in the foregoing, according to the present embodiment, the color of a pattern is separated from data indicating the position of the pattern, and only data indicating the position of the pattern is stored in a pair of buffers. Accordingly, it is unnecessary to provide buffers, the number of which is equal to the number of colors used.

Further, according to the present embodiment, pattern data is written in the refresh memory 5 on the basis of the position signals stored in the buffers, and therefore data in that portion of the refresh memory 5 where the pattern data is not written, is kept unchanged. Accordingly, new pattern data can be written in the refresh memory 5 without erasing pattern data having been previously written therein.

Furthermore, according to the present embodiment, a pair of buffers are alternately subjected to a writing operation for storing the output of a vector generator, and one of the buffers is subjected to a reading operation during the time the other buffer is subjected to the above writing operation. Accordingly, the vector generator can operate without having any waiting time.

In addition, according to the present embodiment, a pair of adjacent display blocks are covered by two buffers. Accordingly, the previously-mentioned bad influence can be eliminated which is produced when pattern data is written in only an edge portion of a conventional buffer.

As mentioned above, according to the present invention, it is not required to provide buffers, the number of which is equal to the number of colors necessary for color display, and therefore the total capacity of buffers can be reduced.