US 4,641,286 AGrant
Auxiliary Decoder for Semiconductor Memory Device
Issue Date:1987-02-03
•1 Claims
•2 Drawing Sheets
Abstract
A semiconductor memory device in which at least a line decoder or a column decoder in multiplex form is provided to select one line selection signal or column selection signal. When the line decoder or column decoder is defective, or when the word line or bit line associated with the line decoder or column decoder involves a defective bit, the defective line decoder, column decoder, word line or bit line is inactivated. The inactivated line decoder or column decoder is replaced with an auxiliary line decoder or column decoder.
Metadata
Assignee
- Mitsubishi Denki Kabushiki Kaisha
Inventors
- Kazuhiro Shimotori
- Kazuyasu Fujishima
- Hideyuki Ozaki
- Hideshi Miyatake
Application Information
Application Number:US 5810000
Filing Date:1984-02-16
Priority Date:1983-02-17
Art Unit:233
Classifications
IPC:
G11C 800
Field of Search:
365307200;230463;468
Patent Drawings (2 sheets)
Description
Background of the Invention
The present invention relates to a semiconductor memory device with redundancy, that is, a memory device having auxiliary bits which may be substituted for defective bits.
FIGS. 1A and 1B respectively show a line decoder and an auxiliary line decoder of a conventional semiconductor memory device. By way of example, a redundancy dynamic MOS semiconductor memory device using a laser programming system will be described.
In FIG. 1A showing the line decoder, Q.sub.1 through Q.sub.5 designate insulated gate type field-effect transistors (MOS transistors), which have drains connected commonly to a node N.sub.1, sources connected to a ground terminal having a ground potential V.sub.ss and gates receiving respective address signals (RA.sub.2, RA.sub.2), through (RA.sub.6, RA.sub.6); Q.sub.6, an MOS transistor having a drain connected to a power supply terminal having a supply voltage V.sub.cc, source connected to the node N.sub.1, and a gate supplied with a prcharge signal PRD; Q.sub.7 through Q.sub.10, MOS transistors to the gates of which a separation signal CRDI is applied; Q.sub.11 through Q.sub.14, MOS transistors which have gates connected to sources of respective ones of the MOS transistors Q.sub.7 through Q.sub.10 and drains applied receiving word line drive signals CR.sub.0 through CR.sub.3 ; L.sub.1 through L.sub.4, links which are connected to the sources of corresponding ones of the MOS transistors Q.sub.11 and Q.sub.14 and which can be fused (rendered connected) by a laser; and WL.sub.n through WL.sub.n+3, word lines connected to the other ends of respective ones of the links L.sub.1 through L.sub.4.
The MOS transistors Q.sub.1 through Q.sub.10 form the line decoder and the MOS transistors Q.sub.11 through Q.sub.14 form a subdecoder and a word line drive circuit. The word line drive signals are those signals which are decoded by address signals (RA.sub.0, RA.sub.0) and (RA.sub.1, RA.sub.1) (not shown). The precharge signal PRD is used to precharge the line decoder. The separation signal CRDI is used to separate the node N.sub.1, which is the output terminal of the line decoder, from the gates of the MOS transistors Q.sub.11 through Q.sub.14.
In FIG. 1B showing the auxiliary line decoder, Q.sub.21 through Q.sub.26 designate MOS transistors which have drains connected commonly to the ground terminal at a ground voltage V.sub.ss, and gates supplies with respective one of the address signals RA.sub.0, RA.sub.1, . . . and RA.sub.5 ; Q.sub.27 through Q.sub.32, MOS transistors which have sources connected to the ground terminal at the ground potential V.sub.ss and gates supplies with respective ones of the address signals RA.sub.0, RA.sub.1 . . . and RA.sub.5 ; Q.sub.33, an MOS transistor having a drain connected to a node N.sub.2, source connected to the ground terminal at the ground voltage V.sub.ss and gate supplied with the address signal RA.sub.6 ; Q.sub.34, an MOS transistor having a drain connected to the power source terminal at the supply voltage V.sub.cc, source connected to the node N.sub.2, and gate supplied with the precharge signal PRD.
Further in FIG. 1B, Q.sub.35 designates an MOS transistor having a source connected to the node N.sub.2 and gates supplied with the separation signal CRDI; Q.sub.36, an MOS transistor having a drain supplied with a word line drive signal CR.sub.M and gate connected to the drain of the MOS transistor Q.sub.35 ; L.sub.11 through L.sub.16, links having first ends connected commonly to the node N.sub.2 and second ends connected to the sources of the MOS transistors Q.sub.21 through Q.sub.26, respectively, and which can be selectively fused by a laser; L.sub.17 through L.sub.22, links having first ends connected to the drains of the MOS transistors Q.sub.27 through Q.sub.32, respectively, and second ends connected commonly to the node N.sub.2 and which can be fused by a laser; and L.sub.23, a link which has one end connected to the source of the MOS transistor Q.sub.36 and the other end connected to an auxiliary word line SWL and which can be fused by a laser. The MOS transistor Q.sub.21 through Q.sub.35 form an auxiliary word line drive circuit. The node N.sub.2 acts as the output node of the auxiliary line decoder.
The operation of the semiconductor memory device thus constructed will be described. First, the case where no defective bits are present will be described. In this case, the links L.sub.1 through L.sub.4 are not fused. Accordingly, when the address signals (RA.sub.2, RA.sub.2), . . . (RA.sub.6, RA.sub.6) used to maintain the gates of the MOS transistors Q.sub.1 through Q.sub.5 at zero volts are applied, the MOS transistors Q.sub.1 through Q.sub.5 are nonconductive (off), and the node N.sub.1, which is the output terminal of the line decoder, is held at a high potential set thereupon by the precharge operation of the precharge signal PRD applied to the transistor Q.sub.6. On the other hand, a node connected to another line decoder (not shown) is held at the ground potential due to a discharging operation. When the high level separation signal CRDI is applied to the gates of the MOS transistors Q.sub.7 through Q.sub.10, the latter are rendered conductive. Therefore, the high potential of the node N.sub.1 is applied through the MOS transistors Q.sub.7 through Q.sub.10, which are thereby rendered conductive, to the gates of the MOS transistors Q.sub.11 through Q.sub.14, respectively. When the separation signal CRDI goes to the low level, the high gate potentials of the MOS transistors Q.sub.11 through Q.sub.14 are maintained at the respective gates. When one of the word line drive signals CR.sub.0 through CR.sub.3, for instance the signal CR.sub.1, is at a high potential, the MOS transistor Q.sub.12 is rendered conductive so that the high gate potential is transmitted through the MOS transistor Q.sub.12 and the link L.sub.2 to the word line WL.sub.n+1. As a result, data is read out of or written into a memory cell (not shown).
For instance, if a memory cell (not shown) connected to the word line WL.sub.n` includes a defective bit, the link L.sub.2 connected to the word line WL.sub.n+1 is opened (blown) by a laser so that the word line drive signal CR1 is not applied to the word line WL.sub.n+1. That is, data from the defective bit is not read nor written. In this case, one of the links forming each of the link pairs L.sub.11 and L.sub.17, L.sub.12 and L.sub.18, . . . and L.sub.16 and L.sub.22 is fused with a laser so that the MOS transistors Q.sub.21, . . . and Q.sub.35 of the auxiliary decoder are activated with combinations of signals for selecting the regular line decoder indicated in FIG. 1A. Therefore, the word line WL.sub.n+1 associated with the defective bit can be replaced by a normal auxiliary word line. In the case where no defective bit is involved, the auxiliary word line SWL will not be selected if the circuit is so designed that at least one of the MOS transistors Q.sub.21 through Q.sub.35 is rendered conductive by the signal at the node N.sub.2, which is the output terminal of the MOS transistors Q.sub.21 through Q.sub.35.
If the regular decoder of the conventional semiconductor memory device is defective, for instance, if the MOS transistor Q.sub.3 is damaged, the four word lines WN.sub.n through WN.sub.n+3 cannot be driven, and accordingly data cannot be written into or read out of the memory cells coupled to these word lines. Accordingly, if the area which the decoder occupies out of the entire area of the memory element is relatively large and the expected defective bit percentage is large, it is impossible to significantly increase the defect correction pecentage. In this point, the conventional semiconductor memory device is disadvantageous.
Summary of the Invention
Accordingly, an object of the invention is to provide a semiconductor memory device which, when a regular decoder is defective, or even when the word lines or bit lines associated with the regular decoder are defective, the defect correction percentage of the overall memory element is increased.
The foregoing object and other objects of the invention have been achieved by the provision of a semiconductor memory device which includes means for inactivating, when a line decoder or column decoder in multiplex form is defective or when a word line or bit line associated with the line decoder or column decoder involves a defective bit, the defective line decoder, column decoder, word line or bit line, and means for replacing the line decoder or column decoder thus inactivated with an auxiliary line decoder or column decoder.
Brief Description of the Drawings
FIGS. 1A and 1B are circuit diagram showing a line decoder and an auxiliary line decoder in a conventional semiconductor memory device; and
FIGS. 2A and 2B are circuit diagrams showing an example of a semiconductor memory device according to the invention.
Description of the Preferred Embodiments
FIGS. 2A and 2B are circuit diagrams showing an example of the semiconductor memory device constructed according to the invention. In this embodiment, a sub decoder is selected by two word line drive signals CR.sub.0 and CR.sub.1 by way of example.
In FIG. 2A showing a line decoder, Q.sub.15 designates an MOS transistor having a drain connected to a node N.sub.1, source connected to the ground terminal at the voltage V.sub.ss, and gate supplied with the address signals RA.sub.1 or RA.sub.1. The MOS transistor Q.sub.15 and MOS transistors Q.sub.1 through Q.sub.8 form a regular line decoder. MOS transistors Q.sub.11 and Q.sub.12 form a word line drive circuit for applying word line signals CR.sub.0 and CR.sub.1 selected by the address signals RA.sub.0 and RA.sub.0 to the word lines WL.sub.n and WL.sub.n+1 similarly to the operation of FIG. 1A.
In FIG. 2B showing an auxiliary line decoder, Q.sub.37 designates an MOS transistor having a source connected to a node N.sub.2 and gate supplied with the separation signal CRDI; Q.sub.38, an MOS transistor having a drain supplied with the word line drive signal CR.sub.1 and gate connected to the drain of the MOS transistor Q.sub.37 ; and L.sub.24, a link having one end connected to a source of the MOS transistor Q.sub.38 and the other end connected to a word line SWL.sub.2.
The operation of the semiconductor device thus constructed will be described. First, the case where no defective bit is involved will be described. In this case, the links L.sub.1 and L.sub.2 are not fused. The MOS transistors Q.sub.1 through Q.sub.5 and Q.sub.15 are nonconductive, and therefore the node N.sub.1, which is the output terminal of the line decoder, is maintained at a high potential previously impressed in the precharging. On the other hand, a node which is connected to the output terminal of another line decoder (not shown) is at the ground potential V.sub.ss due to discharging of the non-selected decoder. When the high level separation signal CRDI is applied to the MOS transistors Q.sub.7 and Q.sub.8, the MOS transistors Q.sub.7 and Q.sub.8 are rendered conductive. Therefore, the high potential of the node N.sub.1 is applied through the conductive MOS transistors Q.sub.7 and Q.sub.8 to the gates of the MOS transistors Q.sub.11 and Q.sub.12. When the separation signal CRDI goes to the low level, the high gate potential of the MOS transistors Q.sub.11 and Q.sub.12 are maintained by the gate electrodes. When one of the word line drive signals CR.sub.0 and CR.sub.1, for instance, the word line drive signal CR.sub.1, reaches the high potential, the MOS transistor Q.sub.12 passes that word line drive signal conductive. Therefore, the high gate potential is transmitted through the conductive MOS transistor Q.sub.12 and the link L.sub.2 to the word line WL.sub.n+1 so that data is read out of or written into the corresponding memory cell (not shown).
If, for instance, the memory cell connected to the word line WL.sub.n involves a defective bit, or, for instance, if the MOS transistor Q.sub.3 is damaged, the links L.sub.1 and L.sub.2 connected to the word lines WL.sub.n and WL.sub.n+1 are destroyed or opened so that the word line drives signals CR.sub.0 and CR.sub.1 are not applied to the word lines WL.sub.n and WL.sub.n+1 and data is not read out of and written into the defective bit and the defective line decoder is not selected. Then, in this case, one of the links forming each of the link pairs L.sub.11 and L.sub.17, and L.sub.12 and L.sub.18, . . . and L.sub.16 and L.sub.22 is fused with a laser and the MOS transistors Q.sub.21 through Q.sub.32, Q.sub.34 and Q.sub.35 and Q.sub.37 of the auxiliary decoder applied with combinations of signals for selecting the regular line decoder as shown in FIG. 2A. Therefore, the word lines WL.sub.n and WL.sub.n+1 are replaced by the normal auxiliary word lines SWL.sub.1 and SWL.sub.2. In the case where no defective bit is involved, the auxiliary word lines SWL.sub.1 and SWL.sub.2 will not be selected since the circuit is so designed that at least one of the MOS transistors Q.sub.21 through Q.sub.32 is reduced conductive and therefore the node N.sub.2 which is the output terminal of these MOS transistors Q.sub.21 through Q.sub.32 is at the ground potential V.sub.ss.
In the above-described embodiment, the sub decoder is selected by two word line drive signals CR.sub.0 and CR.sub.1. However, it can be similarly selected by a desired number of word line drive signals, such as four word line drive signals. Furthermore, in the above-described embodiment, defect correction of the line decoder and the word line has been described, but the technical concept of the invention can be equally applied to defect correction in a column decoder and a bit line. Furhermore, it goes without saying that the technical concept of the invention can be similarly applied to a memory having sub decode signals such as a static MOS memory or a bipolar memory.
As is apparent from the above description, the semiconductor memory device according to the invention can relieve not only the defective bits of the word lines but also a defective multiple decoder or column decoder. Thus, the device of the invention is advantageous in that it has a high defect percentage due to redundancy.
Claims
What is claimed is:
1. A semiconductor memory device comprising: a line decoder, said line decoder comprising a plurality of MOS first transistors having sources connected to a ground line, drains connected to a first node, and gates receiving respective address signals; an MOS second transistor having a source coupled to said first node, a drain coupled to a power source terminal, and a gate receiving a precharge signal; a plurality of MOS third transistors having drains connected to said first node and gates receiving a separation signal; a plurality of MOS fourth transistors, in a number equal to the number of said third transistors, having gates connected to sources of corresponding ones of said third transistors, drains receiving corresponding word line drive signals, and sources connected through corresponding fusible links to corresponding word lines; and an auxiliary line decoder comprising a plurality of MOS fifth transistors having sources connected to said ground line and drains connected through corresponding fusible links to a second node, said fifth transistors being provided in pairs of which the two transistors of each pair receive respective inverted and uninverted address signals; an MOS sixth transistor having a source connected to said second node, a drain connected to said power source terminal and a gate receiving said precharge signal; a plurality of MOS seventh transistors having drains connected to said second node and gates receiving said separation signal; a plurality of MOS eighth transistors, in a number equal to the number of said seventh transistors, having gates connected to sources of corresponding ones of said seventh transistors, drains receiving corresponding word line drive signals, and sources connected through corresponding fusible links to corresponding auxiliary word lines.