Boosting Word-Line Clock Circuit for Semiconductor Memory

1. Field of the Invention

The present invention relates to voltage boosting circuits, and more particularly to a boosting circuit for a word-line clock circuit in a semiconductor memory.

2. Description of the Prior Art

Voltage boosting circuits are described in the prior art in various configurations for a variety of purposes.

U.S. Pat. No. 4,061,929 issued Dec. 6, 1977 to Asano entitled CIRCUIT FOR OBTAINING DC VOLTAGE HIGHER THAN POWER SOURCE VOLTAGE describes a voltage boosting circuit which comprises a plurality of units connected in sequence and each composed of a condenser and a plurality of MOS-FETs without any transformer or diode.

U.S. Pat. No. 4,029,973 issued June 14, 1977 to Kobayashi et al entitled VOLTAGE BOOSTER CIRCUIT USING LEVEL SHIFTER COMPOSED OF TWO COMPLEMENTARY MIS CIRCUITS discloses an improvement for a voltage booster circuit. The improvement lies in the use of MISFETs as switching means in a level converting circuit constructed in a complementary MIS semiconductor integrated circuit and therefore the voltage loss due to the conventional switching means can be prevented.

In U.S. Pat. No. 4,216,390 issued Aug. 5, 1980 to Stewart entitled LEVEL SHIFT CIRCUIT a gating means, biased to pass current only during signal transitions, transfers binary signals from an input signal source to a latch circuit when the signal source and the latch are operated at similar voltages. Following data transfer, the operating voltage across the latch is increased. The voltage levels of the latch output signals are correspondingly increased but the state to which the latch was set is maintained and there is no steady state current conduction through the gating means.

In U.S. Pat. No. 4,045,691 issued Aug. 30, 1977 to Asano, also entitled LEVEL SHIFT CIRCUIT, a level shift circuit is disclosed including an inverter connected to a first voltage supply source and supplied with an input pulse. A condenser and a directional switching element are connected in series between the output point of the inverter and one potential point of the first voltage supply source. The input of a first MOS-FET is connected to the output of the inverter while the input of a second MOS-FET is connected to a connection point between the condenser and the directional switching element. The source of the first MOS-FET is connected to a common terminal of first and second voltage supply sources while the source of the second MOS-FET is connected to the other terminal of the second voltage supply source. An output voltage is generated between a common connecting point of the the drains of the first and second MOS-FETs and one potential point of the second voltage supply source.

Circuits for generating pulsating potentials and voltage levels outside the range of, and/or of greater magnitude than, the operating potential applied to the circuits are described in U.S. Pat. No. 4,000,412 issued Dec. 28, 1976 to Rosenthal et al entitled VOLTAGE AMPLITUDE MULTIPLYING CIRCUITS. Each circuit includes first and second transistors for applying a first voltage to one plate of a capacitor and a second voltage to the other plate of the capacitor, during one time interval. During a subsequent time interval, the first and second transistors are turned off and a third transistor applies the second potential to the one plate of the capacitor. The change in the potential at the one plate of the capacitor is coupled to the other plate of the capacitor at which is produced an output potential outside the range of the first and second voltages. The potential difference between the first voltage and the output potential difference is greater in amplitude than the potential difference between the first and second voltages. The circuit may also include means alternately applying the first voltage and then the output potential to an output point for generating pulsating signals of greater amplitude than the magnitude of the applied potential. The outputs of two or more circuits may be combined to produce direct current (d.c.) levels. Also included are circuits which operate from a pulsating source of operating potential.

Other references in the general field of voltage or level boosting include the following U.S. patents:

U.S. Pat. No. 3,999,081 by T. Nakajima entitled CLOCK-CONTROLLED GATE CIRCUIT issued Dec. 21, 1976

U.S. Pat. No. 3,982,138 by Luisi et al entitled HIGH SPEED-LOW COST, CLOCK CONTROLLED CMOS LOGIC IMPLEMENTATION issued Sept. 21, 1976

U.S. Pat. No. 3,947,829 by Y. Suzuki entitled LOGICAL CIRCUIT APPARATUS issued Mar. 30, 1976

U.S. Pat. No. 3,943,377 by Y. Suzuki entitled LOGIC CIRCUIT ARRANGEMENT EMPLOYING INSULATED GATE FIELD EFFECT TRANSISTORS issued Mar. 9, 1976

U.S. Pat. No. 3,852,625 by M. Kubo entitled SEMICONDUCTOR CIRCUIT issued Dec. 3, 1974

U.S. Pat. No. 3,801,831 by J. S. Dame entitled VOLTAGE LEVEL SHIFTING CIRCUIT issued Apr. 2, 1974.

An object of the present invention is to provide a semiconductor memory clock circuit for boosting the word-line voltage.

Another object of the present invention is to provide a semiconductor memory clock circuit wherein the word-line voltage is boosted above the supply voltage value.

A further object of the present invention is to provide a semiconductor memory clock circuit using a single supply voltage.

Still another object of the present invention is to provide a semiconductor memory CMOS clock circuit wherein no junction is forward biased.

The foregoing and other objects, features and advantages of the invention will be apparent from the following more particular description of the invention as illustrated in the accompanying drawings.

FIG. 1 is a schematic illustration of one embodiment of a semiconductor memory clock circuit according to the principles of the present invention.

FIG. 2 is a schematic illustration of a detail of a semiconductor device used in the output circuit of FIG. 1.

FIGS. 3, 4, 5 and 6 illustrate waveforms useful in explaining the operation of the circuit of FIG. 1.

In most commercial NMOS DRAM's, the word-line voltage is boosted above supply voltage VDD (which may be, for example, 5 volts) so that full signal can be stored in or read from the storage cell without threshold voltage loss. For CMOS DRAM's, PMOS transistors made in the n-well can be used as the transfer devices in the one-transistor DRAM cell. Thus, the selected word-line level changes from 5 volts to 0 volt and to negative voltage when the word-line signal is boosted. N-well CMOS technology is assumed here where the n-well is biased at 5 volts and the p-substrate is grounded. Similar principles used here can be easily adopted for p-well CMOS or other CMOS technologies. In a CMOS technology with supply voltage in the order of only 5 volts, however, a boosting word-line circuit is difficult to design. For example, a boosting level in the order of -2 volts cannot be applied to the NMOS source or drain, because it will forward-bias the N+P junctions to cause carrier injection, thus inducing malfunction of the dynamic circuits or even latch-up. Similarly PMOS sources and drains cannot tolerate a voltage much greater than 0.6 volts above VDD, however, undershoot and overshoot can easily occur in a boosting circuit. On the other hand, as the chip density increases up to one megabits and/or the supply voltage scales down below the standard 5 volts, the boosting word-line circuit is very important because the storage capacitor area has to be limited below a certain value to maintain reasonable chip size and the threshold loss cannot be tolerated. FIG. 1 illustrates a CMOS boosting word-line clock circuit, which can be used for CMOS DRAM's with a single supply voltage with no junction forward-biased.

In FIG. 1, .PHI..sub.A is a clock signal on lead 10 which functions to discharge and to charge the output between 0 volts and VDD (assuming 5 volts in the simulation). The output on lead 12 can be gated to the individual word-line by activating a decoder. Clock signal .PHI..sub.D on lead 14 functions to boost the output below 0 volts. Clock signal .PHI..sub.C on lead 16 is a clock signal to control the voltage at node 18 of the circuit. The key point in the circuit operation is to avoid any overshoot at PMOS source/drain and undershoot at NMOS source/drain. In order to fully discharge the output through device 20 and to avoid any undershoot at node 22, the waveform at node 18 is important. The operation of the circuit of FIG. 1 is described by also referring to the waveforms of FIGS. 3, 4, 5 and 6.

The circuit functions as follows. Before activation as shown in FIG. 3, clock signals .PHI..sub.A and .PHI..sub.D are low (0 volts) and clock signal .PHI..sub.C is high (5 volts). The output on lead 12 and node 26 is charged to high voltage and node 18 is set at VTP which is the threshold voltage of device 34. Activation starts by clock signal .PHI..sub.A on lead 10 pulling up and turning on device 24 to discharge the output. In order to keep sufficient overdrive on device 20, node 18 is designed to be self-boosted below 0 volts through the capacitance of device 20 by pulling down the output. The negative voltages at both node 18 and the output are sandwiched between two PMOS transistors to avoid any forward-biasing of junctions. After the output reaches 0 volts, clock signal .PHI..sub.C is pulled down, thus pulling up node 18 to turn off device 20 to protect undershoot at node 22 during boosting. As soon as node 18 reaches one VTP below the output level, clock signal .PHI..sub.D can be activated to pull down node 26, thus boosting output below 0 volts through a coupling capacitor of device 28. Before resetting the circuit, clock signal .PHI..sub.C has to be pulled up to pull down node 18 to avoid any self-boosting of node 18 above VDD during the output reset (the timing is not critical). Two different reset techniques can be used. The first technique is: Pull down clock signal .PHI..sub.D to charge node 26 up, then pull down clock signal .PHI..sub.A to reset the output. The output reset will boost up the node 26 which has been well protected between two NMOS transistors 30 and 32. This high voltage at node 26 will not affect the operation of the next cycle because node 26 will be coupled down right after activation of clock signal .PHI..sub.A. The second scheme is: Pull down clock signal .PHI..sub.A first, reset the output, which can slightly pull up node 26. Then clock signal .PHI..sub.D is pulled down to charge node 26. Since the output reset is slower due to larger capacitance and the boosting efficiency of device 28 is somewhat degraded because device 28 operates around the cut-off region, the overshoot at the output node can be avoided. The simulation shows that, in a nominal condition, a timing skew between clock signals .PHI..sub.A and .PHI..sub.D from 1 to 3 nsec causes overshoot at output from 0 to less than 200 mV. The timing is not difficult to control because both clock signals .PHI..sub.C and .PHI..sub.D can be generated locally from clock signal .PHI..sub.A. The simulation results of these two schemes are seen in FIGS. 3, 4, 5 and 6, respectively. The circuit has no dc power consumption. It should be noted that both the source and drain of device 28 (PMOS) are connected to node 26 which may have voltage higher than VDD to forward-bias the junctions. This problem is solved using a capacitor connection shown in more detail in FIG. 2. The P+ regions of device 28 are shorted to n-well through adjacent metal-bridged N+ regions.

What has been described is an improved, novel CMOS boosting word-line clock circuit which can be used for CMOS technology with a single supply voltage.

The possible junction forward-biasing is completely eliminated by putting the signal in between either two NMOS or two PMOS transistors.

A self-boosting scheme to fully overdrive the PMOS pass-gate is incorporated in the circuit, which can be also used for other similar applications. A special configuration PMOS capacitor, which can sustain voltage higher than VDD at its source and drain, is included for any boosting applications.