Sense Amplifier

The present invention relates to a sense amplifier used, for example, in a static-type semiconductor memory device, one of the functions of the sense amplifier being to select one of a plurality of input signals.

In a static-type RAM device, a very small voltage difference of, for example, about 0.5 V, output from a memory cell and transmitted to a pair of data buses, is amplified by a sense amplifier when readout operation is effected.

However, in a conventional static-type RAM device, especially a large capacity RAM device, since a bit line pair, column transfer gates, and a data bus pair are connected to a selected memory cell, the load of the memory cell becomes heavy, and the readout speed is deteriorated. Especially, in a large capacity RAM device, each bit line and data bus become long and thin, and the on-resistance of the column transfer gates becomes large. Therefore, if the driveability of each memory cell is not large, it takes a long time for the input signal of the sense amplifier to reach a steady state signal level.

It is an object of the present invention to decrease the load of each selected memory cell and to speed up the operation speed of a semiconductor memory device.

According to the present invention, there is provided a sense amplifier of a differential amplifier type having a pair of input circuit portions receiving a plurality of pairs of complementary input signals, one of the input circuit portions comprising a plurality of circuit units each generating the amplifier output of one of each of a plurality of complementary input signals in response to an address signal applied thereto, and the other input circuit portion comprising a plurality of circuit units each generating the amplified output of one of the other ones of the pairs of complementary input signals in response to the address signal applied thereto, the sense amplifier selecting one of a plurality of pairs of complementary input signals in accordance with the address signal and generating an output signal corresponding to a selected pair of complementary input signals.

FIG. 1 is a block circuit diagram illustrating a conventional static-type RAM device;

FIG. 2 is a schematic circuit diagram illustrating a circuit structure of each memory block used in the RAM device of FIG. 1; and

FIG. 3 is a circuit diagram illustrating a sense amplifier as an embodiment of the present invention.

Before describing the preferred embodiments, an explanation will be given of a static-type RAM device using conventional sense amplifiers with reference to the drawings.

FIG. 1 illustrates a general static-type RAM device in which one sense amplifier SA is provided for onememory chip, and memory cells therein are divided into a plurality of memory blocks M.sub.1, M.sub.2, --- In the memory device of FIG. 1, data bus pairs DB and DB (where DB is an inversion of DB) of each memory block M.sub.1, M.sub.2, --- are coupled together to a common sense amplifier SA via transfer gates TG.sub.1, TG.sub.2, --- , respectively. Therefore, it is possible to selectively connect the data bus pair DB and DB of each of the memory blocks M.sub.1, M.sub.2, --- to the sense amplifier SA by using address signals A.sub.1, A.sub.2, --- which are added to the transfer gates TG.sub.1, TG.sub.2, --- Each of the memory blocks M.sub.1, M.sub.2, --- comprises a matrix arrangement of a plurality of memory cells disposed at the intersections of word lines and bit lines, and it is necessary to increase the number of the memory blocks when a high operation speed and low power consumption are necessitated.

There is also known a memory device which comprises a sense amplifier for every data bus pair DB and DB, i.e., for every memory block M.sub.i, in which one of the output signals of the sense amplifiers is selected by using a selection logic circuit provided in the output portion of the sense amplifiers.

In the cases mentioned above, as illustrated in FIG. 2, the loads of a selected memory cell MC are a bit line pair BL and BL, and the data bus pair DB and DB which is connected to the bit line pair BL and BL via column transfer gates CTG, and the aforementioned transfer gates TG.sub.i in the case of the memory device of FIG. 1. Therefore, it takes a long time for the input signal of the sense amplifier to reach a steady state signal level if the drive ability of each memory cell MC, i.e., gm of the transistors constituting the memory cell MC, is small. Expecially, since each of the column transfer gates CTG and the transfer gates TG is not completely turned on even in a selected condition and has some resistance, the RC time constant of each transfer gate circuit becomes relatively large and the signal passing through the transfer gate circuit is delayed. In FIG. 2, WL designates a word line, and the input/output terminals of the memory cell MC composed of a flip-flop are connected to the bit lines BL and BL via transfer gate transistors Q.sub.a and Q.sub.b, whose gate electrodes are connected to the word line WL. These transistors Q.sub.a and Q.sub.b also become the load of the memory cell MC.

As mentioned above, the device shown in FIGS. 1 and 2 has the disadvantages of a heavy load for each memory cell and a low operation speed.

According to the present invention, there is provided a sense amplifier which overcomes these problems, as described below.

FIG. 3 is a circuit diagram illustrating a CMOS type sense amplifier as an embodiment of the present invention. The sense amplifier comprises a pair of complementary input terminals IN and IN, P-channel MOS transistors Q.sub.1 and Q.sub.2 operating as loads, an N-channel MOS transistor Q.sub.3 operating as a constant current source, and an output terminal OUT. The sense amplifier of FIG. 3 further comprises x sets of series connections of N-channel MOS transistors Q.sub.41 and Q.sub.51, Q.sub.42 and Q.sub.52, --- , Q.sub.4x and Q.sub.5x, which are mutually connected in parallel between the input terminal IN and the drain of the transistor Q.sub.3, and x sets of series connections of N-channel MOS transistors Q.sub.61 and Q.sub.71, Q.sub.62 and Q.sub.72, --- , Q.sub.6x and Q.sub.7x, which are mutually connected in parallel between the input terminal IN and the drain of the transistor Q.sub.3. The transistors Q.sub.51 and Q.sub.71, Q.sub.52 and Q.sub.72, --- , Q.sub.5x and Q.sub.7x are controlled by the outputs A.sub.1 through A.sub.x of an address decoder, respectively. The transistors Q.sub.41, Q.sub.42, --- , Q.sub.4x are controlled by input signals S.sub.1, S.sub.2, --- , S.sub.x, respectively, and the transistors Q.sub.61, Q.sub.62, --- , Q.sub.6x are controlled by inverted input signals S.sub.1, S.sub.2, --- , S.sub.x, respectively. It should be noted that a conventional CMOS type sense amplifier comprises only the load transistor Q.sub.1 and Q.sub.2, the transistor Q.sub.3, and one pair of driver transistors, such as Q.sub.41 and Q.sub.61, connected between the input terminal IN and the drain of the transistor Q.sub.3 and between the input terminal IN and the drain of the transistor Q.sub.3.

Where the sense amplifier of FIG. 3 is adapted to the memory device of FIG. 1, it is used as a substitute for the circuit portion surrounded by dot-dash line of FIG. 1. Therefore, the data buses DB and DB of the memory blocks M.sub.1, M.sub.2, --- are connected to the gates of the transistors Q.sub.41 and Q.sub.61 ; Q.sub.42 and Q.sub.62, --- , Q.sub.4x and Q.sub.6x, respectively.

As is apparent from FIG. 3, each set of the transistors Q.sub.4i and Q.sub.5i (i=1, 2, --- , x) composes an AND gate having two inputs S.sub.i and A.sub.i, and each set of the transistors Q.sub.6i and Q.sub.7i composes an AND gate having two inputs S.sub.i and A.sub.i. Therefore, when the outputs A.sub.1 through A.sub.x of the address decoder are all low, the transistors Q.sub.51, Q.sub.52, --- , Q.sub.5x, and Q.sub.71, Q.sub.72, --- , Q.sub.7x are all turned off, and the sense amplifier is in a standby status.

When an output A.sub.i of the address decoder corresponding to the inputs S.sub.i and S.sub.i becomes high, the potentials of the input terminals IN and IN become high and low, respectively, if the inputs S.sub.i and S.sub.i are low and high, respectively, and become low and high, respectively, if the inputs S.sub.i and S.sub.i are high and low, respectively. The potential of the output terminal OUT is the same as that of the input terminal IN and determined by the above relationships of the signals.

Where the sense amplifier is provided for every data bus pair DB and DB, the inputs S.sub.i and S.sub.i, S.sub.2 and S.sub.2, --- , S.sub.x and S.sub.x are signals from the bit lines in a memory block, and the circuit of FIG. 3 is used as a column sense amplifier. The transistor pairs Q.sub.51 and Q.sub.71, Q.sub.52 and Q.sub.72, --- Q.sub.5x and Q.sub.7x correspond to column transfer gates CTG. In this case, the load of each memory cell can be greatly decreased because the memory cell does not drive the data buses. It is also possible to combine the outputs of a plurality of column sense amplifiers into one circuit route by further using one stage of a sense amplifier having a similar constitution.

Although the CMOS type circuit was explained above, the present invention can be also adapted to an N-MOS type circuit and the like.

As mentioned above, according to the present invention, since each sense amplifier itself has the function of a selecting inputs, the load of each memory cell can be decreased when the sense amplifier is used as a column sense amplifier whose input terminals are connected to bit lines. When the sense amplifier is used as a sense amplifier whose input terminals are connected to data buses, it is possible to increase the readout speed because the transfer gates TG can be omitted. When the sense amplifiers are used in a two level hierarchical structure including a bit line stage and a data bus stage, it is possible to constitute a readout circuit stage having high response speed and simple connection patterns.