US 4,631,739 AGrant
High Dynamic Range Charge Amplifier
Issue Date:1986-12-23
•1 Claims
•1 Drawing Sheets
Abstract
A charge coupled device (CCD) amplifier is utilized for amplification of charge packets as small as 500 electrons into usable signals. Very little noise is injected into the signal. The charge amplifier consists of two connecting electrodes, one designated as the detector G.sub.1 and the other designated as the response G.sub.2, physically separated by any convenient distance on the same LSI chip surface on which an NMOS field effect transistor (FET) is attached. Also coupled to the FET is another electrode G.sub.3 designated as the amplifier gate. The charge amplifier structure is embedded in the silicon dioxide layer, with the detector response, and amplifier electrode being located some convenient distance above the silicon-silicon dioxide interface.
Metadata
Assignee
- Xerox Corporation
Inventor
- Roland J. Handy
Application Information
Application Number:US 6755992
Filing Date:1984-11-28
Priority Date:1984-11-28
Art Unit:254
Classifications
IPC:
H03F 304
Field of Search:
37735760-6324 R
Patent Drawings (1 sheets)
Description
This invention relates to a high dynamic range charge amplifier which permits the sensing of low quantities of charge, 500 electrons or less, in low light level imaging systems.
Background of the Invention
Charge coupled devices are well known for their use in light detection in imaging systems. Arrays of charge coupled devices (CCDs) have been utilized for scanning in a raster scan type of arrangement or in a two dimensional array for use in television scanning, for example. The limiting factor for the use of charge coupled devices in imaging system is its low level light detection capability. In order to fully utilize the capability of a charge coupled device, rather than prior art vacuum tube or other kinds of photodetectors, the device must be capable of low level light detection and amplification.
According to the present invention, a charge coupled device (CCD) amplifier is utilized for amplification of charge packets as small as 500 electrons into usable signals. The disclosed process contributes very little noise to the signal. The charge amplifier consists of two connecting electrodes, one designated as the detector and the other designated as the response, physically separated by any convenient distance on which an NMOS field effect transistor (FET) is attached. Also coupled to the FET transistor is another electrode designated as the amplifier gate. The charge amplifier structure is embedded in the silicon dioxide layer, with the detector, response, amlifier electrodes and the NMOS (FET) Transistor being located some convenient distance above the silicon-silicon dioxide interface on the same LSI chip surface and becomes an integral part of the LSI amplifier design.
Description of the Drawings
For a more complete understanding of the invention, reference may be had to the following detailed description of the invention in conjunction with the drawings wherein:
The FIGURE is a cross sectional view of an integrated circuit charge amplifier in accordance with the principles of the present invention.
Detailed Description of the Invention
A CCD amplifier is disclosed for amplification of charge packets as small as 500 electrons into usable signals. This process contributes very little noise to the process.
As set forth herein, the CCD amplifier detects and measures signal charge in one site and utilizes this information to control a larger amount of charge to be generated at another location. In its simplest (discrete) form the charge amplifier consists of two connecting electrodes, one designated the detector G.sub.1 and the other the response G.sub.2, physically separated on the same LSI chip by any convenient distance on which an NMOS field effect transistor (FET) is attached. Also attached to the FET transistor is another electrode designated the amplifier gate G.sub.3. The charge amplifier structure is embedded in the silicon dioxide layer of the LSI chip, with the detector, response and amplifier electrodes being located some convenient distance above the silicon-silicon dioxide interface.
A cross-sectional view of the charge amplifier is shown schematically in the FIGURE in which the surface depletion regions under the detector, response, and amplifier gates are shown without signal charge.
The operation of the charge amplifier is as follows. At time T.sub.o, gate voltage V.sub.G is applied to the gate electrode of the FET; its polarity turns the FET on, applying the voltage V.sub.S to the charge amplifier gates G.sub.1, G.sub.2. Gate G.sub.3 is always held at the voltage V.sub.S. At time T.sub.1, (T.sub.1,=T.sub.o +.DELTA.T), the FET is turned off by removing voltage V.sub.G. The charge amplifier gates G.sub.1 and G.sub.2 are now floating and charged to a potential V.sub.S producing the surface potentials .phi..sub.S1 and .phi..sub.S2 under the gates G.sub.1 and G.sub.2, the detector and response gates respectively. If required, .phi..sub.S1 and .phi..sub.S2 could be made equal to each other.
Since signal charge Q is only allowed to be dumped under the detector gate, the detector gate G.sub.1 will detect the presence of this signal charge Q, and transmit this information to the response gate G.sub.2 through the common connection. The surface potential .phi..sub.S2 under the response gate G.sub.2 varies its value (position) as a function of the amount of signal charge Q being dumped under the detector gate G.sub.1. This is accomplished in the following way. As signal charge Q is dumped under the detector gate G.sub.1, it changes the surface potential .phi..sub.S1 to a new level, which in turn changes the potential on the charge amplifier response gate G.sub.2 from its floating voltage V.sub.S to a value V.sub.G, which in turn varies the surface potential .phi..sub.S2 under the respnse gate G.sub.2 from .phi..sub.S2 to .phi..sub.S3 which is always void of charge. If no signal charge Q is dumped under the detector Gate G.sub.1 no change in the V.sub.S potential will occur and the surface potential .phi..sub.S2 under the response gate remains constant. The diode voltage V.sub.o >V.sub.S during this time interval is now pulsed to a new value V.sub.o <V.sub.S such that charge from the diode is injected under the G.sub.2 and G.sub.3 gates flooding this region with charge. The diode voltage is then pulsed back to the original value V.sub.o >V.sub.S. When this happens, all the charge is spilled back to the diode except that charge residing under amplifier gate G.sub.3, which is a function of the potential barrier generated under gate G.sub.2 (.phi..sub.S3 -.phi..sub.S2) and the area of gate G.sub.3. The value of the charge under gate G.sub.3 can be made n(n>1) times as large as the signal charge Q. This charge (nQ) can now be used to drive output circuits and can be made large enough so that large dynamic range sysems can be designed with low input signal constraints.
Charge Q, applied to detector gate G.sub.1, could be the signal charge generated when light is impinged upon a photosite or other photosensitive sight which creates charge as an information signal. A CCD pixel site is a typical charge Q generator, which could be in close proximity, on the same LSI chip, to the detector gate G.sub.1. If there were a plurality of CCD photosites, there could also be a plurality of the charge amplifiers, as described herein, one for each photosite. Alternatively, one charge amplifier could be used at the end of a shift register which has received charge Qs from a CCD imaging array.
While the invention has been described with reference to specific embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof without departing from the true spirit and scope of the invention. In addition, many modifications may be made without departing from the essential teachings of the invention.
Claims
What is claimed is:
1. A high dynamic range charge amplifier integrated circuit which permits the sensing and amplifying of low quantities of charge, wherein the improvement comprises: a first detector gate means (G.sub.1) on said integrated circuit, a second response gate means (G.sub.2) on said integrated circuit in spaced proximity to said first gate means (G.sub.1), means on said integrated circuit for electrically connecting said first and second gate means together, field effect transistor means coupled to a supply voltage (V.sub.S) and said electrical connecting means, said field effect transistor means applying said supply voltage (V.sub.S) to said electrical connecting means and thus said first and second gate means, when said field effect transistor means is enabled by a gate voltage (V.sub.G), and said first and second gate means floating at said supply voltage (V.sub.S) when said gate voltage (V.sub.G) is removed, a source of charge (Q) to be amplified deposited beneath said first gate means (G.sub.1), such that the supply voltage (V.sub.S) floating on said first gate means (G.sub.1) is affected by the change in surface potential (.phi..sub.S1) beneath said first gate means (G.sub.1), the voltage on said second gate means (G.sub.2) being affected, thereby varying the surface potential (.phi..sub.S2) beneath said second gate means (G.sub.2), a third amplifier gate means (G.sub.3) in close proximity to said second gate means (G.sub.2) and connected to said supply voltage (V.sub.S) and directly affected by said surface potential (.phi..sub.S2) beneath said second gate means (G.sub.2), said third gate means (G.sub.3) defining a larger area wherein additional charge can be deposited beneath both said second and third gate means (G.sub.2, G.sub.3) in direct proportion to the amount of charge (Q) deposited beneath said first gate means (G.sub.1), and diode means between said first gate means (G.sub.1) and said second gate means (G.sub.2) for injecting charge beneath said second and third gate means (G.sub.2, G.sub.3), and then to subsequently dissipate all charge over that determined by the original surface potential (.phi..sub.S2) and the affected surface potential (.phi..sub.S3).