US 4,631,522 AGrant
Method and Circuit for Compensation of a Multiplying Digital-to-Analog Converter
Issue Date:1986-12-23
•5 Claims
•1 Drawing Sheets
Abstract
A method and circuit for reducing the effect of variations in resistances within a multiplying digital-to-analog converter. A first resistor is connected at one end to the feedback resistor of the MDAC, the other end providing a compensated circuit input. A second resistor is connected from the MDAC input to the feedback resistor. The MDAC output to which the feedback resistor is internally connected is connected to the MDAC reference connection, the other output providing a compensated circuit output. The first and second resistors are chosen such that the product of their resistances is equal to the product of the feedback resistance times the MDAC input resistance.
Metadata
Assignee
- Audio Precision, Inc.
Inventor
- Richard C. Cabot
Application Information
Application Number:US 7228589
Filing Date:1985-04-12
Priority Date:1985-04-12
Art Unit:217
Classifications
IPC:
H03K 1302
Field of Search:
340347 DA;347 CC
Patent Drawings (1 sheets)
Description
Background of the Invention
This invention relates to circuits for compensating for variations in electronic component parameters with time and temperature, particularly to a circuit for reducing the effect of changes in resistances within a multiplying digital-to-analog converter.
CMOS multiplying digital-to-analog converters ("MDACs") are used for many applications requiring an adjustable gain stage. The MDAC ordinarily provides the input and feedback resistors for a conventional linear operational amplifier circuit, the MDAC permitting the input resistance to be digitally selected in response to a binary input signal. The MDAC is made of semiconductor resistance elements and CMOS FET switches in a standard ladder configuration.
The resistance of semiconductor resistors varies greatly with temperature and time. This variation is on the order of 30% of their nominal value. However, since a feedback resistor is included in an MDAC and the feedback resistor is made of the same material as the ladder network, where the MDAC is used in a conventional linear operational amplifier circuit the variation in resistance of the input resistor is cancelled out by the variation in resistance of the feedback resistor, and the gain of the amplifier is dependent only on the settings of the FET switches.
However, there are circuit applications where it is desirable to use an MDAC other than in a linear operational amplifier having a selectable input resistor and a feedback resistor provided by the MDAC. For example, it is often desirable to use an integrator having a selectable input resistor and a capacitor as a feedback element. Since the feedback resistor of an MDAC cannot be employed to provide feedback in such applications, the use of an MDAC in such applications is prone to produce large inaccuracies.
It would be desirable to have a circuit that would compensate for variations in the resistances of an MDAC without requiring that its feedback resistor be used as the feedback element of a linear operational amplifier circuit.
Summary of the Invention
The present invention provides a circuit for reducing the effect of variations in resistance of the resistance elements of an MDAC without requiring that the feedback resistor of the MDAC be used as a feedback resistor in a linear operational amplifier circuit. Rather, a first resistor is connected to the MDAC feedback resistor to form a first L-pad, and a second resistor is connected from the feedback resistor to the input of the MDAC to form a second L-pad cascaded with the first. As the MDAC input resistance varies with temperature and time, the feedback resistor varies in a like manner which, due to the cascaded L-pads, tends to maintain the input current to the MDAC constant.
The first and second compensation resistors are chosen such that the product of their resistances is equal to the product of the nominal MDAC input and feedback resistances. While there is a loss of compensated circuit gain resulting from the use of this compensation scheme, the compensated circuit gain can be maximized by setting the resistance of the first resistor equal to the quotient of the feedback resistance divided by the square root of two and the resistance of the second resistor equal to the product of the feedback resistance times the square root of two, where the input and feedback resistance are equal, as is customary.
Accordingly, it is a principal objective of the present invention to provide a novel method and circuit for reducing the effect of variations in resistances within a multiplying digital-to-analog converter.
It is another objective of the present invention to provide such a method and apparatus wherein the feedback resistor of an MDAC is used to vary the voltage applied to the input of the MDAC as internal resistances vary so as to tend to maintain a constant input current to the MDAC.
The foregoing and other objectives, features, and advantages of the invention will be more readily understood upon consideration of the following detailed description of the invention, taken in conjunction with the accompanying drawings.
Brief Description of the Drawings
FIG. 1 illustrates a typical operational amplifier circuit wherein the amplifier gain is selectively variable.
FIG. 2 shows a typical operational amplifier circuit wherein the gain is selectively variable, including a typical multiplying digital-to-analog converter circuit to select the gain.
FIG. 3 illustrates the basic topology of a circuit according to the present invention.
FIG. 4 shows an embodiment of a circuit according to the present invention employed in an integrator application.
Detailed Description of the Invention
Referring to FIG. 1, a typical operational amplifier circuit employs an operational amplifier 10 having an output, an inverting input, and a non-inverting input. The non-inverting input is connected to a reference 11. A feedback impedance Z.sub.f is connected from the output to the inverting input, and an input resistance R.sub.v is connected from the non-inverting input of the operational amplifier to the circuit input 12. Thus, the voltage transfer function of the circuit from the input 12 to the output 14 may be expressed by the following equation:
In many simple linear operational amplifier circuit applications both Z.sub.f and R.sub.v are resistors, R.sub.v being variable in order to vary the gain of the operational amplifier circuit.
Turning to FIG. 2, a common means of varying the input resistor to a linear operational amplifier circuit is to employ a CMOS multiplying digital-to-analog converter ("MDAC"). A typical MDAC is shown in FIG. 2 by the circuitry within the dashed line 16. As is commonly known in the art, the MDAC comprises a set of first semiconductor resistance elements R.sub.L1 -R.sub.Ln connected together in series, one end of the series being connected to the MDAC input connection 24 and the other to the MDAC reference connection 25. The MDAC also includes a set of second semiconductor resistance elements R.sub.S1 -R.sub.Sn connected respectively to the input end of corresponding series resistance elements. These resistance elements form a standard ladder network.
The other end of each of the second resistance elements is connected to a respective CMOS FET switch S.sub.1 -S.sub.n for selectively connecting its respective second resistance element to a first output connection 18 or a second output connection 20. The switches S.sub.1 -S.sub.n are actuated by respective inputs B.sub.1 -B.sub.n, corresponding to bits of a digital input word, as is commonly known in the art. For typical operational amplifier applications, the MDAC is also provided with a feedback resistor R.sub.f connected between output connection 18 and a feedback connection 22. (The term "feedback connection" is used hereinafter for convenience despite that the feedback resistor may not be used as part of a feedback circuit.) In such a circuit the output analog variable, i.e. output voltage, is equal to the product of a number (proportional to the number represented by an input digital code) and an analog reference value, i.e. input voltage. The digital number is represented by the bits B.sub.1 -B.sub.n. A typical example of such a device is an AD 7523 CMOS 8-Bit Multiplying D/A Converter manufactured by Analog Devices, Inc., Route 1, Industrial Park, Norwood Mass., U.S.A.
Ideally, the output current of the MDAC should not vary with temperature or time, but should solely be a function of the input current and the input digital word. In a typical application, as shown in FIG. 2, the MDAC is used to vary the effective input resistance R.sub.v of an operational amplifier circuit of the type shown in FIG. 1. Thus, the outputs 18 and 20 of the MDAC in FIG. 2 are connected to an operational amplifier 26 and R.sub.f provides the feedback resistor for that operational amplifier circuit. By changing the input digital word to the MDAC the gain of the resultant operational amplifier circuit, that is, the ratio of the voltage V.sub.out at output 28 to the voltage V.sub.IN at input 30 can be varied. At the same time, by including the feedback resistor R.sub.f as part of the MDAC, such that it has the same temperature and time characteristics as the other resistance elements in the MDAC, the gain of the operational amplifier circuit is substantially uneffected by temperature and time.
A problem results, however, where the feedback impedance needed for an operational amplifier is not purely resistive. In that case, the feedback resistor of an MDAC cannot be used as the feedback impedance. This is the case, for example, with a typical integrator where the feedback impedance of an operational amplifier is a capacitor. Under such conditions, the MDAC is not automatically temperature compensated.
A topology for solving the foregoing problem according to the present invention is shown in FIG. 3. In this figure R.sub.f represents the feedback resistor in a typical MDAC and R.sub.i represents the input resistance of the MDAC measured with respect to the reference connection 25, assuming that the two outputs 18 and 20 are connected to the reference connection. (This is ordinarily the case in the use of an operational amplifier since the reference is ordinarily connected to ground and the inputs of the operational amplifier are virtually at ground potential.) A first L-pad is formed by a resistor R.sub.1 and the feedback resistance element R.sub.f. A second L-pad, cascaded to the first, is formed by a resistor R.sub.2 and the input resistance R.sub.i of the MDAC. The object is to maintain the current in R.sub.i as nearly constant with temperature and time as possible. By employing R.sub.2 to adjust the voltage cross R.sub.i as R.sub.i changes, and by employing R.sub.1 and R.sub.f to adjust the voltage applied to R.sub.2, the effect of time and temperature on the current through R.sub.i is greatly reduced. For example, as R.sub.i decreases, the current through R.sub.i will increase, but that increase is reduced by the presence of R.sub.2 which drops the voltage across R.sub.i. Moreover, as R.sub.i decreases R.sub.f also decreases, since it is constructed of the same material in the same MDAC, which reduces the voltage applied to R.sub.2, further reducing the change of current in R.sub.i.
Although MDACs are conventional designed so that their input resistance R.sub.i is equal to their feedback resistance R.sub.f, it is conceivable that those resistances would differ. Assuming that R.sub.f =AR.sub.i, where A is a constant, it can be shown that:
Where:
V.sub.IN =the voltage applied to the input 35 in FIG. 3; and
I.sub.i =current through R.sub.i in FIG. 3, i.e., the input current to the MDAC.
It can also be shown that the change in I.sub.i /V.sub.IN will be minimized where:
In the case where R.sub.f =R.sub.i, as is conventional, it can be shown that minimum loss of gain through the MDAC as a result of the compensation resistors will occur where: ##EQU1## It is to be recognized that R.sub.f and R.sub.i have only nominal values for purposes of these computations, the actual values varying with temperature and time. However, assuming R.sub.f =R.sub.i =1 as a nominal value, but an actual variance 0.5 to 1.5 (i.e., a 50% variance), then Table 1 shows the effect of a compensation circuit constructed for minimal loss of gain.
Thus, it can be seen that a substantial increase in compensated circuit accuracy is obtained.
Turning to FIG. 4, the topology of the present invention is applied to a specific embodiment producing an integrator. In this case, output 20, rather than output 18, of the MDAC 16 is applied to the inverting input of an operational amplifier 32. The non-inverting input being connected to the reference 11. The feedback for the operational amplifier is supplied by a capacitor 34, making the circuit an integrator. Resistor R.sub.1 is connected from the circuit input 36 to the feedback connection 22 of the MDAC, and hence to the feedback resistor R.sub.f. Output 18 of the MDAC is connected to the reference, thereby connecting the other end of R.sub.f to the reference. The resistor R.sub.2 is connected from the MDAC input connection 24 to the MDAC feedback connection 22, thereby completing the topology set forth in FIG. 3. Thus, the output 38 is the integral of the input 36, the digital input word represented by bits B.sub.1 -B.sub.n serving to vary the input resistance to the operational amplifier 32 and therefore the integration time constant.
The terms and expressions which have been employed in the foregoing specification are used therein as terms of description and not of limitation, and there is no intention in the use of such terms and expressions of excluding equivalents of the features shown and described or portions thereof, it being recognized that the scope of the invention is defined and limited only by the claims which follows.
Claims
I claim:
1. A compensation circuit for reducing the effect of variations in resistance values of circuit elements within a multiplying digital-to-analog converter having a ladder resistor network comprising a plurality of first resistance elements connected together in series, with one end of said series providing a converter input connection and the other end of said series providing a reference connection, and a corresponding plurality of second resistance elements each connected at one end thereof to the input end of a respective first resistance element, a plurality of switch means, each connected to the other end of a respective second resistance element, for selectively connecting said second resistance elements to one of a first or a second output connection, and a feedback resistance element connected at one end to said first output connection and at its other end to a feedback connection, said converter having a converter input resistance defined as the resistance from said input connection to said reference connection with both said first and said second output connections connected to said reference connection, and a feedback resistance defined as the resistance from said feedback connection to said first output connection, said compensation circuit comprising: (a) a first resistor connected at one end to said feedback connection, the other end providing a compensated circuit input connection; and (b) a second resistor connected at one end to said feedback connection and at the other end to said converter input connection, said first output connection being connected to said reference connection, the product of the resistances of said first and second resistors being equal to the product of said converter input resistance and said feedback resistance, and said second output connection providing a compensated circuit output connection.
2. The compensation circuit of claim 1 wherein each said switch means includes means responsive to a binary input signal for actuating said switch means to select said first or said second output connection.
3. The compensation circuit of claim 1 wherein said converter input resistance is equal to said feedback resistance, said first resistor has a resistance equal to the quotient of said feedback resistance divided by the square root of two, and said second resistor has a resistance equal to the product of said feedback resistance times the square root of two.
4. A method for reducing the effect of variations in resistance values of circuit elements within a multiplying digital-to-analog converter having a ladder resistor network comprising a plurality of first resistance elements connected together in series, with one end of said series providing a converter input connection and the other end of said series providing a reference connection, and a corresponding plurality of second resistance elements each connected at one end thereof to the input end of a respective first resistance element, a plurality of switch means, each connected to the other end of a respective second resistance element, for selectively connecting said second resistance elements to one of a first or a second output connection, and a feedback resistance element connected at one end to said first output connection and at its other end to a feedback connection, said converter having a converter input resistance defined as the resistance from said input connection to said reference connection with both said first and said second output connections connected to said reference connection, and a feedback resistance defined as the resistance from said feedback connection to said first output connection, said method comprising: (a) connecting one end of a first resistor to said feedback connection, the other end providing a compensated circuit input connection; (b) connecting said first output connection to said reference connection; and (c) connecting one end of a second resistor to said feedback connection and the other end to said converter input connection, the product of the resistances of said first and second resistors being equal to the product of said converter input resistance and said feedback resistance, said second output connection providing a compensated circuit output connection.
5. The method of claim 4 wherein said input resistance is equal to said feedback resistance, said first resistor has a resistance equal to the quotient of said feedback resistance divided by the square root of two, and said second resistor has a resistance equal to the product of said feedback resistance times the square root of two.
Patent Citations (4)
| Patent | Date | Inventor | Cited By |
|---|---|---|---|
| US4410880 | 1983-10-01 | Zaborowski | |
| SUX702512 | 1979-12-01 | ||
| SUX822208 | 1981-04-01 | ||
| SUX1035788 | 1983-08-01 |
Non-Patent Literature (2)
- "CMOS Hybrid MDAC Serves as Replacement for Monolithic Types", Comput. Design (USA) vol. 19, No. 10, Oct. 1980.
- Sounders et al., "A 20 Bit + Sign, Relay Switched D/A Converter," National Bureau of Standards Tech. Note 1105, Washington, D.C. USA, Oct. 1979.