US 4,628,472 AGrant
Binary Multiplier Using Ternary Code
Issue Date:1986-12-09
•8 Claims
•7 Drawing Sheets
Abstract
The invention provides a high-speed binary multiplier. The binary digits x.sub.i of the multiplicand X and y.sub.j of the multiplier Y (in two complement form) are converted by respective coders into coefficients a.sub.i and b.sub.j such that where a.sub.i and b.sub.j can only assume three values 0,1 or -1 and where two consecutive coefficients a.sub.i and a.sub.i-1 and b.sub.j or b.sub.j-1 cannot both be non zero. a.sub.i and b.sub.j are each represented by a pair of binary logic signals (r.sub.i,u.sub.i) or (s.sub.j,v.sub.j). The signals (s.sub.j,v.sub.j) serve for controlling a routing circuit which further receives as signals to be routed the signals (r.sub.i,u.sub.i) for directing these signals, depending on the values of coefficients b.sub.j, to the appropriate inputs of an adder stage operating without carry-over propagation. The outputs of this adder are reconverted into binary form by a decoder.
Metadata
Assignee
- Societe pour l'Etude et la Fabrication de Circuits Integres Speciaux-Efcis.sup.2
Inventor
- Thierry Fensch
Application Information
Application Number:US 5534887
Filing Date:1983-11-18
Priority Date:1982-11-26
Art Unit:232
Classifications
IPC:
G06F 752
Field of Search:
364759;760
Patent Drawings (7 sheets)
Description
Background of the Invention
1. Field of the Invention
The present invention relates to binary digital multipliers.
2. Description of the Prior Art
The principle of binary digit multiplication is well known: the multiplicand is multiplied by the lowest weight digit of the multiplier, then by the digit with the immediately higher weight and so on up to the highest weight; the result each time is a partial product, and the different partial products are added with a lateral leftward shift by a digit between each partial product and the preceding one. The sum of all the partial products progressively shifted forms the result of the multiplication.
Concretely, a partial product can be stored in a register, the result shifted by a rank, added to the next partial product, the result stored in the same register and so on. This is a sequential procedure which is long.
So efforts have been made to design multipliers in which all the partial products are generated simultaneously and added (combinatory and not sequential logic), and, for these multipliers, attempts have been made to increase the working speed, either by reducing the time for adding the partial products or by reducing the number of these partial products.
The adding time may be reduced by using improved adders such as:
adders with carry-over safeguard in which the carry-overs of the elementary additions of the digits of a number are not propagated from one digit to the next but are kept to be added as a whole;
adders with anticipated carry-over, in which the value of the carry-over is forecast as a function of the inputs instead of waiting for propagation thereof;
adders connected together in a particular pattern such as the Wallace tree for grouping together the partial products progressively three by three.
Independently of the reduction of adding time, the number of partial products to be added may also be reduced by appropriately coding the bits of the multiplier. With Booth's algorithm and the variations thereof, only (n+1)/2 partial products are generated instead of n for a multiplier with n digits, each of these partial products having four or five possible values which are, X, -X, 2X and possibly -2X, X being the multiplicand. But this kind of manipulation increases the complexity of the circuit, so the space required thereby.
Summary of the Invention
The present invention aims at providing a multiplier presenting a better compromise between the operating speed on the one hand and the complexity and space required by the circuit on the other. It uses signal processing such that only (n+1)/2 partial products are generated, these partial products each being only able to assume three values 0, X or -X (X being the multiplicand). These partial products are added two by two by an addition without carry-over propagation, which is very important for the propagation of a carry-over between the elementary adders of an n bit adder stage is time consuming, the more so the larger n is.
The binary multiplier of the invention, intended to receive in the form of logic electric signals a first binary number, called multiplicand X, and a second binary number called multiplier Y, so as to supply their product in the form of logic electric signals, comprises a coder for converting the binary signals representing the n digits y.sub.j (y.sub.j =0 or 1) of the multiplier Y into a set of logic signals representing n coefficients b.sub.j (j=0 to n-1) multiplying successive powers of 2 of the binary number Y expressed in the form of the following algebraic sum:
where the coefficients b.sub.j may take on the values 0, 1 or -1 exclusively, and where the product of two consecutive coefficients b.sub.j and b.sub.j-1 is necessarily zero.
The multiplier also comprises, for arriving at an improvement of the speed/compactness compromise, a coder for converting similarly the binary signals representing the m digits x.sub.i (x.sub.i =0 or 1) of the multiplicand X into a set of logic siqnals representing m coefficients a.sub.i (i=0 to m-1) multiplying successive powers of 2 of the number X expressed in the form of the following algebraic sum
where the coefficients a.sub.i may take on the values 0, 1 or -1 exclusively, and where the product of two consecutive coefficients a.sub.i and a.sub.i-1 is necessarily zero.
Theory shows that this coding of coefficients x.sub.i or x.sub.j into coefficients a.sub.i and b.sub.j having the indicated properties is possible and is even unique.
Coefficients a.sub.i and b.sub.j, having three possible values 0, 1 or -1, are each preferably represented by a pair of binary logic signals, the coders then supplying, from the m or n binary digits of the multiplicand and of the multiplier m or n pairs of binary logic signals.
It is these pairs of coded logic signals which will be more particularly subjected to the adding and shifting logic operations required for accomplishing the multiplication.
The multiplier of the invention may comprise at least one adder stage formed by a series of elementary adders each receiving two pairs of coded logic signals from the coder of the multiplicand and each supplying a sum and carry-over coded in the same way as the pairs, the successive elementary adders of the series being interconnected and adapted so that they all operate simultaneously without waiting for the propagation of a carry-over between the first and last adders of the series; in other words, the elementary adders of this stage, when they comprise a carry-over input, are adapted so that the carry-over of the addition which they work out does not depend on the carry-over applied to the carry over input.
Brief Description of the Drawings
Other features and advantages of the invention will appear fromreading the following detailed description which is made with reference to the accompanying drawings in which:
FIG. 1 is a block diagram of a four by four bit multiplier in accordance with the invention;
FIG. 2 shows a circuit detail useful in the multiplier;
FIG. 3 shows an elementary pattern of the circuit for generating and shifting partial products required for accomplishing the multiplication;
FIG. 4 shows a detail of the circuit for generating and shifting partial products, this detail concerning the lowest weight bits of the partial products;
FIG. 5 shows the diagram of the partial product adder stage;
FIG. 6 shows the diagram of an elementary adder without carry-over input capable of adding two coded digits of value 0, 1 or -1, each on two logic levels, and supplying a sum and carry-over coded in the same way;
FIG. 7 shows a diagram of a coder for the multiplicand (or multiplier);
FIG. 8 is a diagram of a decoder for reconverting the result of the multiplication into binary form.
Description of the Preferred Embodiments
The multiplier of the invention will be described progessively in its different elements, essentially for multiplying a four bit multiplicand by a four bit multiplier; at the appropriate places, it will be stated how to generalize. It will be assumed that operation is with signed input binary numbers, coded with two complement, so able to be wrtten in the form:
for the multiplicand: X=-x.sub.3 .multidot.2.sup.3 +x.sub.2 .multidot.2.sup.2 +x.sub.1 .multidot.2.sup.1 +x.sub.o
for the multiplier: Y=-y.sub.3 .multidot.2.sup.3 +y.sub.2 .multidot.2.sup.2 +y.sub.1 .multidot.2.sup.1 +y.sub.o
The highest weight bit is a sign bit (0=positive number; 1=negative number).
In the preferred embodiment of the invention, whose block diagram is shown in FIG. 1, each of these two numbers, represented by binary logic signals with the same name x.sub.o to x.sub.3, y.sub.o to y.sub.3 as the digits which they represent, is applied to a respective coder, 10 for the multiplicand X, 12 for the multiplier Y.
Coder 12 receives four logic input levels corresponding to the binary digits y.sub.o, y.sub.1, y.sub.2, y.sub.3 of the multiplier Y and converts them into four pairs of logic output signals, (s.sub.o,v.sub.o), (s.sub.1,v.sub.1), (s.sub.2,v.sub.2), (s.sub.3 v.sub.3), each representing a coefficient b.sub.o, b.sub.1,b.sub.2,b.sub.3 respectively, where:
and where the coefficients b.sub.j have the above mentioned properties, namely that they can only take on three values 0, 1 and -1 and that the product of two consecutive coefficients b.sub.j and b.sub.j-1 is zero, that is to say that we cannot have two consecutive non zero coefficients.
The correspondence between the value of the coefficient and the logic levels of the pairs of output signals of the coder is the following: ##EQU1##
The combination s.sub.j =1, v.sub.j =0 is prohibited and cannot appear at the output of the coder. The correspondence coding between values 0, 1 and -1 and pairs (s.sub.j,v.sub.j) could be different from the one chosen here.
Coder 12 supplies then the multiplier Y in this coded form where v.sub.j represents an absolute value 0 or 1 of a coefficient of a power of 2 and where s.sub.j represents the sign of this coefficient.
Multiplication normally consists in taking the coefficients b.sub.j of the multiplier and in forming the product of each of these coefficients by means of the multiplicand so as to obtain partial products which will be added to each other with appropriate shifts.
If b.sub.j =0 the partial product is 0
If b.sub.j =1 the partial product is X (multiplicand)
If b.sub.j =-1 the partial product is -X
The multiplicand X is itself Coded by Coder 10 which transforms, exactly like coder 12, its four logic input levels, corresponding to the binary digits, x.sub.o, x.sub.1, x.sub.2, x.sub.3, into four pairs of logic output signals (r.sub.o,u.sub.o), (r.sub.1,u.sub.1), (r.sub.2,u.sub.2), (r.sub.3,u.sub.3) each representing a coefficient a.sub.o,a.sub.1,a.sub.2, a.sub.3, respectively, where:
and where the coefficients a.sub.i have the same properties as the coefficients b.sub.j and are coded by the signals (r.sub.i,u.sub.i) in the same way as signals b.sub.j are coded by the signals (s.sub.j,s.sub.j), namely: ##EQU2##
The combination r.sub.i =1, u.sub.i =0 is prohibited and cannot appear at the output of coder 10.
Coder 10 then supplies the multiplicand X in this coded form where u.sub.i represents an absolute value 0 or 1 of a coefficient of a power of two and r.sub.i represents the sign of this coefficient (0=positive; 1=negative).
The code of correspondence between the values 0, 1 and -1 and the two logic levels (r.sub.i,u.sub.i) could also be different.
But, in addition, as distinct from coder 12, and because coder 10 of the multiplicand is in fact intended to generate partial products and because these partial products may take the value 0, X or -X with the coding explained above, it is preferable for coder 10 to be capable of supplying at its output both X and -X, i.e. both the values a.sub.i and the opposite thereof -a.sub.i.
This is obtained very simply by providing, inside the coder 10 or outside, an inverter further supplying the complement r.sub.i * of r.sub.i, which complement is however forced to zero if u.sub.i =0 so as not to end up with the prohibited combination (r.sub.i =1,u.sub.i =0).
FIG. 1 shows then, at the output of coder 10 of the multiplicand, not pairs of output signals (r.sub.i,u.sub.i) but triplets, (r.sub.i,r.sub.i *,u.sub.i) representing in fact two possible pairs (r.sub.i,u.sub.i)=a.sub.i and (r.sub.i *,u.sub.i)=-a.sub.i.
FIG. 2 shows a very simple logic diagram with an inverter 14 and an inhibiting AND gate 16 for producing the triplets (r.sub.i,r.sub.i *,u.sub.i) from the pair (r.sub.i,u.sub.i) with inhibition of the prohibited combination r.sub.i *,u.sub.i =1,0.
Referring again to FIG. 1, the triplets (r.sub.i,r.sub.i *,u.sub.i) are applied as input signals to a logic routing circuit 18 which is controlled by the four pairs (s.sub.j,v.sub.j) of the coder 12 to direct the different input signals (r.sub.o to r.sub.3, r.sub.o * to r.sub.3 *, u.sub.o to u.sub.3) to well defined outputs as a function of the values of the four control pairs (s.sub.j,v.sub.j) from the coder 12.
In fact, the routing circuit 18 has a function of generating partial products 0, X or -X and appropriately shifting these partial products before addition thereof.
The outputs of the routing circuit 18 are applied to the different inputs of an adder stage 20 for effecting well determined partial product additions as a function of the control pairs (s.sub.j,v.sub.j) and obtaining at the output a multiplication result in coded form. A decoder 22 may be placed at the output of the adder stage 20 for reconverting the output signal pairs of the adder stage into binary code, in accordance with a code which is the inverse of the one used for passing from values x.sub.o,x.sub.1,x.sub.2,x.sub.3 to values (r.sub.o,u.sub.o), (r.sub.1,u.sub.1), (r.sub.2,u.sub.2), (r.sub.3,u.sub.3).
Indicentally, if the multiplier had more than four bits, e.g. eight or sixteen, it would be necessary to group these latter in fours and provide a routing circuit and an adder stage for each group of four. The outputs of these adders, reconverted or not into binary form, should themselves be added two by two with appropriate shifts in a second stage then possibly in a third one, etc., until an output result is obtained from a final single adder, which result is reconverted into binary code if need be. On the contrary, the structure of FIG. 1 only requires the coder 10, the routing circuit 18, and adder 20 to have a larger number of inputs and outputs, if the multiplicand has more than 4 bits.
Before describing the detail of coders 10,12 of the routing circuit 18, and of the adder 20, a numerical example will be taken to explain the formation of the partial products and their addition in the case where the multiplier Y has four bits; the multiplier X has here also four bits but this latter point is not important for understanding the operation, generalization to m bits being immediate.
The input binary numbers are taken with the convention called "2 complement"; these are then signed numbers where the highest weight bit is a sign bit.
Let X=1011 (-5 in decimal) be multiplied by Y=0110 (+6 in decimal).
It can be shown that the only way of writing X and Y by means of coefficients a.sub.i and b.sub.i having the indicated properties is here:
Coder 10 here supplies the following logic level pairs:
as well moreover as the opposite pairs:
Coder 12 supplies the following logic level pairs
Multiplication of X by Y may be written as a conventional four digit multiplication but here some digits may be negative: ##EQU3##
The result is 0,-1,0,0,0,1,0, namely -2.sup.5 +2.sup.1 =-30
The four successively written partial products are respectively 0, -X, 0, X (in the order of increasing weights). Two partial products only out of four are not zero and contribute to the final result.
This results from the properties of the particular coding used for obtaining the coefficients b.sub.j of the multiplier: we cannot have two consecutive non zero coefficients b.sub.j.
This is why, for a multiplier with more than four bits, these bits are grouped together in fours so as to produce each time only two non zero partial products which are added with an appropriate shift.
The additions are made in columns of digits, that is to say that the adder stage 20 comprises essentially as many elementary adders as there are possible columns, namely m+3 if the multiplicand has m digits, in practice m+1 adders only as will be seen.
Each elementary adder may receive at a first input (actually at a first pair of inputs) a first digit coming from the first or second partial product and at a second input (actually at a second pair of inputs) a second digit coming from the third or fourth partial product.
It is the routing circuit 18 which routs the digits a.sub.i of the multiplicand to the appropriate inputs of the elementary adders which are to receive them, depending on the values of the coefficients b.sub.j of the multiplier so on the outputs of coder 12. The routing circuit 18 also inverts the value of a.sub.i when a partial product to be formed is -X or cancels a.sub.i when the partial product is 0. Finally, it effects the appropriate shift of the digits of the partial products to be added.
Generally, an elementary adder of rank i must work out the sum:
To one input of the adder are assigned the values a.sub.i .multidot.b.sub.o and a.sub.i-1 .multidot.b.sub.1 (one of the two is necessarily zero) and to the other input the values a.sub.i-2 .multidot.b.sub.2 and a.sub.i-3 .multidot.b.sub.3 (one of the two is necessarily zero).
Thus the adder receives at its first input: ##EQU4##
It receives at its second input: ##EQU5##
The other combinations are impossible.
The coefficients of type a.sub.i -k are of course considered as zero if i-k is negative.
The preceding logic table allows the logic function of the routing circuit 18 to be completely defined, not forgetting that each coefficient a.sub.i or b.sub.j is coded in the form of two binary logic signals.
FIG. 3 shows a partial diagram of the routing circuit with an array of swtiches (MOS transistors) NOR logic gates and inverters for supplying to the inputs of an elementary adder A.sub.i of rank i the desired coefficient pairs, with the desired signs, as a function of the signals (s.sub.j,v.sub.j) representing the coefficients b.sub.j.
Adder A.sub.i has a first pair of inputs C.sub.i, C'.sub.i for receiving a pair of binary signals forming the first term of the addition (namely O or a.sub.i or -a.sub.i or a.sub.i-1 or -a.sub.i-1 depending on the case, and a second pair of inputs D.sub.i,D'.sub.i for receiving the second term (namely O or a.sub.i-2 or -a.sub.i-2 or a.sub.i-3 or -a.sub.i-3 depending on the case).
It comprises a first pair of outputs S.sub.i,S'.sub.i for supplying the sum of the two terms of the addition, with the same coding as the coefficients a.sub.i and b.sub.j, that is to say that if the sum is equal to 0,1 or -1, the first pair of outputs supplies level pairs 00, 01 or 11; the adder comprises finally a second pair of outputs R.sub.i,R'.sub.i for supplying the carry-over of the addition; in fact, this carry-over is different from zero in the case of the addition 1+1 (carry-over equals 1) or (-1)+(-1) (carry-over equals -1). This carry-over has then three possible values and is again expressed with the same coding as the coefficients a.sub.i and b.sub.j.
Without describing entirely the diagram of FIG. 3, which is sufficiently clear to be understood by a man skilled in the art, it can be seen that it provides exactly the following routing functions.
1. If v.sub.o =0, the transmission of the levels (r.sub.i,u.sub.i) or (r.sub.i *,u.sub.i) to the inputs C.sub.i,C'.sub.i is prohibited by two MOS transistors controlled by v.sub.o ; if not it is enabled, r.sub.i or r.sub.i * being transmitted depending on whether s.sub.o =0 or s.sub.o =1 by means of two MOS transistors and an inverter;
2. If v.sub.1 =0, the transmission of the levels r.sub.i-1,u.sub.i-1 or r.sub.i *.sub.-1,u.sub.i-1 to the inputs C.sub.i,c'.sub.i is prohibited by two other MOS transistors controlled by v.sub.1 ; if not it is enabled, and two MOS transistors and an inverter controlled by s.sub.1 allow r.sub.i-1 or r.sub.i *.sub.-1 to be selected for transmission depending on whether s.sub.1 =0 or s.sub.1 =1.
3. If v.sub.o and v.sub.1 are both zero, not only are the transmissions prohibited but C.sub.i and C'.sub.i are both forced to a logic level 0 by two transistors controlled by a NOR gate receiving both v.sub.o and v.sub.1.
4. The same basic circuit is used for the transmission of r.sub.i-2, r*.sub.i-2, u.sub.i-2 or r.sub.i-3, r.sub.r *.sub.-3 to the inputs D.sub.i, D'.sub.i, routing being achieved under the control of v.sub.2, v.sub.3 and s.sub.2,s.sub.3 instead of v.sub.o,v.sub.1,s.sub.o,s.sub.1 respectively.
The diagram of FIG. 3 only shows one pattern which must be repeated as many times as there are adders so theoretically m+3 times for an m bit multiplicand multiplied by a group of four bits of the multiplier. In fact, there are no adders of rank 0 and 1; the routing circuit supplies directly, for these two ranks, the sums of digits of partial products, for these sums are reduced to a single term.
FIG. 4 shows one embodiment of the portion of the routing circuit concerning the sums of digits of partial products of rank 0 and 1; this circuit portion is moreover only a simplification of the circuit of FIG. 3 taking into account that for i=1 and i=0, a.sub.i-3, a.sub.i-2 and possibly a.sub.i-1 must be considered as zero;
for rank 0, the only partial product to be transmitted, as digit of zero rank in the result of the multiplication, is a.sub.o .multidot.b.sub.o so either 0 if b.sub.o =0 (i.e. in practice if v.sub.o =0), or a.sub.o (r.sub.o,u.sub.o) if b.sub.o =1 (i.e. if s.sub.o =0 and v.sub.o =1), or finally -a.sub.o, i.e. (r.sub.o *,u.sub.o), if s.sub.o =1 and v.sub.o =1. The routing logic circuit portion shown in FIG. 4 supplies a pair of signals t.sub.o,w.sub.o, representing a.sub.o .multidot.b.sub.o with the same coding, on two logic levels, as the coefficients a.sub.i and b.sub.j ;
for rank 1, only one partial product is non zero but it may be either a.sub.o .multidot.b.sub.1 if b.sub.o =0; or a.sub.1 .multidot.b.sub.o if b.sub.1 is zero; the circuit of FIG. 4 establishes then also two signals t.sub.1,w.sub.1 representing either a.sub.o .multidot.b.sub.1 or a.sub.1 .multidot.b.sub.o depending on the case which is presented, always with the same coding.
t.sub.o,w.sub.o, and t.sub.1,w.sub.1 represent the values (0,+1 or -1) of the two lowest weight digits of the result of the multiplication by four bits.
The other digits t.sub.i,w.sub.i are established from elementary adders A.sub.2,A.sub.3 etc. receiving the outputs of the routing circuit 18.
The block diagram of FIG. 5 shows the adder stage 20 formed essentially from elementary adders A.sub.2 to A.sub.m+2 each having two pairs of inputs C.sub.i,C'.sub.i and D.sub.i, D'.sub.i and a pair of "sum" outputs S.sub.i, S'.sub.i and a pair of "carry-over" outputs R.sub.i, R'.sub.i. Sum and carry-over are coded on two logic levels like all the other coefficients capable of assuming the three values 0,1,-1.
Here, a very important remark must be made: because the multiplicand is coded by coefficients a.sub.i such that a.sub.i and a.sub.i-1 cannot be both non zero, the partial products of the multiplication, which products are transmitted to the elementary adders, present the same property.
Thus, if by chance in the same column of digits to be added there are two digits 1 or two digits -1, we can be certain that each of these digits has at its right and at its left a zero, so that:
1. The addition in question will not be disturbed by a carry-over of the lower rank addition,
2. This addition will itself give rise to a carry-over 1 or -1 which will have to be added to the result of the higher rank addition; but since this latter only comprises an addition of zeros, its result will be equal to the carry-over 1 or -1, but will not give rise to a new carry-over.
There is then no case where the carry-over may be propagated over several successsive adders as is the case in normal additions.
This is why an arrangement and interconnection of the elementary adders is provided such that all the adders may work simultaneously without having to wait for the carry-over of the preceding rank addition. This carry-over is simply added at the output of the adders by a logic gate which takes into account the different cases where a carry-over may appear.
The elementary adders A.sub.i are here "half-adders" in this sense that, though they each produce a sum and a carry-over, they do not however have an input for the carry-over from the preceding stage which would be likely to modify their own carry-over result.
It can be seen in FIG. 5 that two OR gates 24 and 26 are provided for each adder A.sub.i. Gate 24 receives the output S.sub.i of adder A.sub.i and output R.sub.i of adder A.sub.i-1. Gate 26 receives the outputs S'.sub.i and R'.sub.i-1. Gates 24 and 26 supply the logic levels t.sub.i,w.sub.i representing the overall result of the operation, namely the value of the digit of rank i of the result of the multiplication.
For adder A.sub.2, these OR gates are useless for there is no preceding carry-over.
With these OR gates it is verified that:
on the one hand, the carry-over of an adder cannot be affected by the carry-over of the preceding stage;
on the other hand, if the carry-over of adder A.sub.i-1 is 00, then the sum 00 or 01 or 11 supplied by the adder A.sub.i is not modified by passing through the OR gates; finally, if the carry-over of adder A.sub.i-1 is 01 or 11, it is because adder A.sub.i must only receive zeros and supply at its "sum" outputs a pair of levels 00 which do not modify the passage through the OR gate of the carry-over 01 or 11.
FIG. 6 shows a detailed diagram of an elementary adder A.sub.i. This adder must supply a result, sum and carry-over, corresponding to the addition of two digits which may assume only the values 0, 1 and -1. It must respect the following equalities: ##EQU6##
These equalities define the logic functions to be provided, when numbers 0, 1 and -1 are represented by pairs of logic levels 00, 01 or 11 not only at the inputs but also at the outputs of the adder.
A corresponding logic diagram is shown in FIG. 6. The names of the inputs and outputs are those of FIGS. 4 and 5.
The elementary adder A.sub.i comprises:
four inverters 28,30,32,34 for producing the logic complements C.sub.i *, C'.sub.i *, D.sub.i *, D'.sub.i * of the levels of the inputs C.sub.i, C'.sub.i, D.sub.i, D'.sub.i,
a four input OR gate 36 receiving the signals C.sub.i *, C'.sub.i *, D.sub.i *, D'.sub.i * and followed by an inverter supplying at the output R.sub.i the sign of the carry-over of the addition
an OR gate 40 receiving C.sub.i, C'.sub.i, D.sub.i, D'.sub.i and an AND gate 42 receiving the outputs of the OR gates 36, and 40; the output of the AND gate 42 supplies to the output R'.sub.i the absolute value of the carry-over;
an OR gate 44 receiving C.sub.i, C'.sub.i, D.sub.i *, D'.sub.i *, an OR gate 46 receiving C.sub.i *, C'.sub.i *, D.sub.i, D'.sub.i and a NAND gate 48 receiving the outputs of the OR gates 44 and 46 and supplying at the output S.sub.i the sign of the sum effected;
an exclusive OR gate 50 receiving C'.sub.i and D'.sub.i and supplying at the output S'.sub.i the absolute value of the sum.
The detail of one of the coders 10 or 12 will now be described whose role is to find, from the number X or Y applied in binary form to an input of the multiplier, coefficients a.sub.i, b.sub.j with three values 0, 1, -1, the 1 or -1 being necessarily separated by zeros, and coding these coefficients on two logic levels 00, 01 and 11 while prohibiting the combination 10.
Coding of the binary coefficients x.sub.i (i=0 to m-1) into ternary coefficients a.sub.i takes place in the following way, the number X being written in the so-called "two complement" form where the highest weight bit is a sign bit.
Intermediate logic signals p.sub.i and q.sub.i are established such that:
p.sub.i is the result of the exclusive OR of x.sub.i and x.sub.i-1 with p.sub.o =x.sub.o,
q.sub.i is the logic product of p.sub.i and of the complement of q.sub.i-1 with q.sub.o =x.sub.o,
Then is written:
(the number x only having m digits x.sub.o to x.sub.m-1).
Such is the algorithm used here for calculating the coefficients a.sub.i.
We have then
a.sub.i =q.sub.i if x.sub.i+1 =0 and
a.sub.i =-q.sub.i if x.sub.i+1 =1.
q.sub.i is a logic signal with two possible levels 0 or 1; a.sub.i may take three values 0, 1 or -1 and is represented by two binary signals r.sub.i and u.sub.i.
r.sub.i represents the sign of a.sub.i. If r.sub.i =0 is chosen for a positive sign and r.sub.i =1 for a negative sign, we may assume r.sub.i =x.sub.i+1 since it is for x.sub.i+1 =1 that a.sub.i =-q.sub.i and for x.sub.i +1=0 that a.sub.i =q.sub.i.
In fact, it will be assumed that r.sub.i =x.sub.i+1 .multidot.q.sub.i so as to have even so a positive sign if q.sub.i =0 (prohibition of the combination 1,0 for r.sub.i,u.sub.i).
u.sub.i represents the absolute value of a.sub.i ; u.sub.i is then equal to q.sub.i.
From the above is derived the structure of the logic coding circuit shown in FIG. 7 for four input binary coefficients x.sub.o to x.sub.3; three exclusive OR gates 52,54,56 establishing the levels p.sub.3, p.sub.2, p.sub.1 ; p.sub.o is equal to x.sub.o and to q.sub.o and u.sub.o. Three inverters 58,60,62 establish from q.sub.2, q.sub.1, q.sub.o the complements q.sub.2 *, q.sub.1 *, q.sub.o * of these levels.
Three two-input AND gates 64,66,68 whose outputs establish levels q.sub.3, q.sub.2, q.sub.1, which are also the levels u.sub.3, u.sub.2, u.sub.1, each receive respectively p.sub.3 and q.sub.2 *, p.sub.2 and q.sub.1 *, p.sub.1 and q.sub.o *.
Finally, four AND gates 70,72,74,76 receive respectively q.sub.3 and x.sub.3, q.sub.2 and x.sub.3, q.sub.1 and x.sub.2, q.sub.o and x.sub.1 and establish respectively the levels r.sub.3, r.sub.2, r.sub.1, r.sub.o.
The coder of the multiplier is exactly the same: it is sufficient to replace above the x.sub.i by y.sub.j and the signals r.sub.i,u.sub.i by signals s.sub.j,v.sub.j.
Finally, once the result of the multiplication is obtained in the form of m+n-1 coefficients c.sub.i, each represented by two binary levels t.sub.i,w.sub.i so that if t.sub.i,w.sub.i equals 0, 0 then c.sub.i =0 if t.sub.i,w.sub.i =0,1, then c.sub.i =1 if t.sub.i,w.sub.i =1,1, then c.sub.i =-1, the result of the multiplication is:
It is desirable to reconvert coefficients c.sub.i with three possible values into binary coefficients z.sub.i with two values 0,1 with:
(expression of number Z in so-called "two complement" binary code).
Decoding is in fact very simple: the positive or zero coefficients c.sub.i (t.sub.i =0) are separated from the negative or zero coefficients c.sub.i (t.sub.i =1 or w.sub.i =0).
The series of positive coefficients corresponds to a first positive number in binary form.
The series of the negative coefficients corresponds to the opposite of a second positive number.
The number Z is then written in the form of a subtraction of two positive binary numbers. Each of these numbers may then be written in "two complement" form by adding a high weight sign bit and adding them; for the first number, the added sign bit is 0, for the second the sign bit is 1 and the corresponding two complement number is established by complementing the bits of the second number and adding a lowest weight unit.
The two numbers written "in two complement" form are then added so as to give the number Z in two complement form.
FIG. 8 shows the corresponding decoding circuit.
From each coefficient c.sub.i a binary coefficient d.sub.i is established for the positive number (d.sub.i =0 if c.sub.i is equal to 0 or -1, d.sub.i =1 if c.sub.i =1); d.sub.i is obtained at the output of an exclusive OR gate 78 receiving t.sub.i and w.sub.i, that is to say the sign and the absolute value of the coefficient c.sub.i.
A coefficient e.sub.i is also established for the negative number (e.sub.i =0 if c.sub.i =0 or 1; e.sub.i =1 if c.sub.i =-1); e.sub.i is quite simply identical to the sign bit t.sub.i of the coefficient c.sub.i.
A sign bit 0 is added to the positive number and a sign bit 1 to the negative number.
The sum of the positive number and of the negative number is provided by bit by bit addition of the coefficient d.sub.i and of the complement of the coefficient e.sub.i (established by an inverter 80) and by adding a lightest weight unit.
This addition is effected in a conventional binary adder 82 with m+n bits, having a carry-over input forced to 1 (for adding a lightest weight unit), inputs receiving the levels t.sub.i and inputs receiving the complements of the levels e.sub.i. Moreover, the pair of heaviest weight inputs receive 0,1, i.e. the respective sign bits of the positive number and of the negative number.
The result of the addition is a series of logic levels z.sub.o to z.sub.m+n-1 representing the binary coefficients (in two complement form) of the result of the multiplication.
In fact, it may be shown that, considering the numbers of bits m and n of the multiplier and of the multiplicand, expressed in two complement form, the result of the multiplication expressed in the same convention should only comprise m+n-1 coefficients z.sub.o to z.sub.m+n-2, including a sign bit which would be z.sub.m+n-2.
It may be concluded that in reality it is sufficient to provide an adder 82 with m+n-1 bits by suppressing the inputs of signs 0 and 1 and the output z.sub.m+n-1 which are useless because:
(a) z.sub.m+n-1 is normally equal to z.sub.m+n-2
(b) and, in two complement form, if the two highest weight bits are identical, they may be replaced by a single sign bit having the same value.
To finish this description of the multipliers of the invention, it may be pointed out that in the case of the multiplier having more than four bits, for example sixteen bits, these bits are grouped in fours and coefficients c.sub.i (logic levels t.sub.i,W.sub.i) are obtained as a result of the four multiplications. These levels ray be introduced into adders such as the adder stage 20, except that it will then be
an adder with carry-over propagation and so each elementary adder will in fact be formed of two half-adders of the type shown in FIG. 6. It is also possible for the results of the multiplications by four bits to be converted into binary form (two complement form) and added to each other in conventional binary adders.
In the whole of the preceding description, it should be considered that the choice of code 00, 01, or 11 for representing a value 0, 1 or -1 respectively with a prohibited combination 10, is one possible choice among several and that if this code is changed, it is necessary to effect slight adaptations of the logic structure which results therefrom in the logic circuits which have been described.
Finally, the preferred embodiment which has been described comprises a coder for the multiplier and a coder for the multiplicand. If only the first were used, an advantage would be gained essentially on the number of partial products to be added, but the adder stage 20 would be a binary adder (so with carry-over propagation) and there would be no decoder 22.
Claims
What is claimed is:
1. A binary multiplier circuit for receiving in the form of logic electric signal a first binary number X and a second binary number Y, so as to supply in the form of logic electric signal the product of these two numbers, said multiplier circuit comprising a coder for converting n binary signals y.sub.j (j=0 to n-1) representing number Y into n pairs of binary signals (s.sub.j,v.sub.j), each pair representing one coefficient b.sub.j (j=0 to n=1), where b.sub.j can be 0, 1 or -1 and where one signal (s.sub.j) of the pair represents the sign of b.sub.j and the other signal (v.sub.j) of the pair represents the module of b.sub.j, where the product of two consecutive coefficients b.sub.j and b.sub.j-1 is zero, and where the coefficients b.sub.j are such that +b.sub.o, said coder comprising, for each integer value of indicia j between 1 and n, an EXCLUSIVE-OR gate receiving y.sub.i and y.sub.1-1, an AND gate receiving on a first input an output p.sub.j of the EXCLUSIVE-OR gate, and receiving on a second input the logical complement of v.sub.j-1, said AND gate having an output supplying the binary signal v.sub.j, a further AND gate having a first input receiving signal v.sub.j and a second input receiving signal y.sub.j+1, except that for j=n-1 the second input of said further AND gate receives y.sub.n-1, said further AND gate having an output supplying signal s.sub.j, said coder having outputs for supplying binary signals s.sub.j and v.sub.j (j=1 to n-1) and further comprising two outputs for supplying respectively a signal v.sub.o which is equal to y.sub.o and a signal s.sub.o which is the logical AND of y.sub.o and y.sub.1.
2. A binary multiplier circuit according to claim 1 wherein said number X is the multiplicand and said number Y is the multiplier, the multiplier circuit comprising a routing circuit receiving binary signals representing number X and a binary adder stage, said routing circuit being controlled by the outputs s.sub.j, v.sub.j of the coder, and said adder receiving outputs from the routing circuit.
3. A binary multiplier circuit for receiving in the form of logic electric signal a first binary number X and a second binary number Y, so as to supply in the form of logic electric signal the product of these two numbers, said multiplier circuit comprising a coder for converting n binary signals y.sub.j (j=0 to n-1) representing number Y into n pairs of binary signals (s.sub.j,v.sub.j), each pair representing one coefficient b.sub.j (j=0 to n-1), where b.sub.j can be 0, 1 or -1 and where one signal (s.sub.j) of the pair represents the sign of b.sub.j and the other signal (v.sub.j) of the pair represents the module of b.sub.j, where the product of two consecutive coefficients b.sub.j and b.sub.j-1 is zero, and where the coefficients b.sub.j are such that +b.sub.o, said multiplier circuit further comprising a second coder for converting m binary signals x.sub.i representing number X into m pairs of binary sigals (r.sub.i,u.sub.i), each pair representing one coefficient a.sub.i (i=0 to m-1), where a.sub.i can be 0, 1 or -1 and where one signal r.sub.i of the pair represents the sign of a.sub.i and the other signal u.sub.i of the pair represents the module of a.sub.i, where the product of two consecutive coefficients a.sub.i and a.sub.i-1 is zero, and where the coefficient a.sub.i are such that said multiplier further comprising a routing circuit and a binary adder stage, said routing circuit receiving the outputs of said second coder and the routing circuit being controlled by the outputs of said first coder, and said adder stage receiving outputs from the routing circuit.
4. A binary multiplier circuit according to claim 3, wherein said second coder further supplies m binary logic signal r.sub.i * where r.sub.i * is the complement of r.sub.i if u.sub.i =1 and is zero if u.sub.i =0.
5. The multiplier as claimed in claim 4 wherein said routing circuit transmits to elementary adders of said adder stage having a first and a second pair of inputs the following signals depending on the four pairs of control signals: on the first pair of inputs (C.sub.i,C'.sub.i) ##EQU7## at the second pair of inputs (D.sub.i,D'.sub.i) ##EQU8## the signals of the type u.sub.i-k or r.sub.i-k being logic levels 0 if i-k is negative and r.sub.i * being the complement of r.sub.i if u.sub.i =1 or 0 if u.sub.i =0.
6. The multiplier as claimed in claim 5 wherein said elementary adders supply at their outputs output sum and carry-over pairs according to coding having the same significance as the coding of coefficient a.sub.i or b.sub.j into signals (r.sub.i,u.sub.i) or (s.sub.j,v.sub.j), and the "sum" outputs of an adder are each applied to an input of a respective OR gate, these gates further receiving the carry-over outputs from the elementary adder of immediately lower rank.
7. The multiplier as claimed in one of claim 1 to 6 further comprising a decoder receiving pairs of logic signals (t.sub.i w.sub.i) each representing a coefficient c.sub.i with three values o,1 or -1, for converting the number Z represented by these pairs, Z=c.sub.m+n-1 2.sup.m+n-2 + . . . c.sub.1 2.sup.1 +c.sub.o into a binary number represented by binary logic outputs z.sub.i with: +z.sub.o
8. A multiplier as claimed in claim 7 wherein said decoder comprises an exclusive OR gate receiving the signals t.sub.i and w.sub.i and supplying a signal d.sub.i, an inverter receiving the signal t.sub.i and a binary adder having a carry-over input forced to the logic level 1 and pairs of inputs for signals to be added, each pair of inputs receiving the output of the exclusive OR gate and the output of the inverter.
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