US 4,621,204 AGrant
Sensor Integrator System
Issue Date:1986-11-04
•4 Claims
•2 Drawing Sheets
Abstract
A sensor-integrator circuit having a sensor for producing a current varying in accordance with the sensed parameter or a reference current source, a comparator having inverting and noninverting inputs and an output and charge storage device coupled to the inverting input. The circuit is energized to obtain a given positive steady state reset voltage, a reference voltage is applied to the noninverting input of a comparator which is less positive than the steady state voltage and integration is initiated solely by alternately applying the current from the sensor and the reference current to the inverting input of the comparator.
Metadata
Assignee
- Miles Laboratories, Inc.
Inventors
- Mark C. Loessel
- Randall W. Miller
- Robert W. Myers
Application Information
Application Number:US 6345743
Filing Date:1984-07-26
Priority Date:1984-07-26
Art Unit:254
Classifications
IPC:
H03K 1914H03K 522H03K 500
Field of Search:
307328311;228;494127;128
Patent Drawings (2 sheets)
Description
Background of the Invention
The present invention relates generally to a sensor integrator circuit and a method for converting a sensed parameter to a digital value with a dual slope integrator.
In particular, the present invention is directed to a system for converting sensed light to a digital value.
Prior art systems of this type are known and in particular a system of this type is described in U.S. Pat. No. 4,313,067, the contents of which are incorporated herein by reference.
While the system described therein is operable to obtain a time interval which corresponds to the light intensity sensed by a photo diode whereupon a digital value can be obtained from the time interval, the circuitry shown therein necessitates two or more control lines for carrying out this process.
Summary of the Invention
The main object of the present invention is to provide an improvement over the prior art system wherein the sensor integrator system and the method of conversion can be carried out with a single control line.
Other objects and advantages of the present invention will become more apparent from the following detailed description of the invention when read in conjunction with the attached drawings which illustrate preferred embodiments thereof, wherein:
Brief Description of the Drawings
FIG. 1A is a schematic of a classical integrator circuit;
FIG. 1B is a wave form diagram of the operation of a classical dual slope analog to digital converter utilizing the classical integrator;
FIG. 2A is a schematic of the sensor-integrator circuit in accordance with the present invention; and
FIG. 2B is a wave form diagram of the operation of the circuit of FIG. 2A.
Detailed Description of the Invention
Referring to FIG. 1A, in a classical integrator of the type shown therein, the integrator transfer function is ##EQU1## To reset the integrator, switch SW3 is closed and the capacitor is shorted to 0 voltage. Therefore, E.sub.o goes to 0 volts. Assuming E1 is the sample voltage to be integrated, when switch SW1 is the only switch closed, the capacitor charges negatively. If the reference voltage E2 is to be integrated, than only switch SW2 is closed and the capacitor voltage increases in a positive direction.
FIG. 1B shows the results when a classical integrator of this type is used for the conventional type of dual slope A/D conversion. At time T0, the integrator is reset by closing SW3, whereupon E.sub.o is reset to the known condition of 0 volts. The starting voltage can be anywhere within the shaded area at T0 to T1. Since the switch shorts the capacitor (C), reset occurs quickly.
At T1, the sample is integrated by closing only switch SW1 and E.sub.o is determined in accordance with the aforementioned integrator transfer function. The sample voltage E1 is the unknown that is to be measured and the time interval T1-T2 is preset to be constant.
At time T2, switch SW2 is the only switch closed and the reference voltage E2 is integrated until the reset voltage is reached. The time interval from T2 until the reset voltage is reached is T3 and is a function of the sample voltage E1 in accordance with the following equations: ##EQU2##
The circuits shown in the aforementioned U.S. Pat. No. 4,313,067 utilizes two of the three switches noted above to obtain this result and thus necessitates the use of two control lines to carry out the integration for A/D conversion.
The circuit in accordance with the present invention is a departure from the conventional dual slope integrator A/D converter in that it necessitates only a single control line and does not require a separate reset control in order to carry out successive A/D conversions.
The analog regulator is turned on for A/D conversions. Initially the analog regulator is off, and the capacitor is discharged. Since the voltage across a capacitor cannot change instantaneously, the voltage at both capacitor leads follows the analog regulator voltage, and the comparator is reset within the rise time of the regulator. The reset is accomplished in one millisecond. Selecting I.sub.ref maintains the reset state.
At time T1, the reference current is turned off and the sample current Is is selected. The sample current is then integrated for a fixed time interval during T1 to T2 and this time has been preselected as one second.
At time T2, the select control line is reversed and the reference current I.sub.ref is selected. The reference current is reverse integrated to the reset voltage at a constant slope. The time at which the reset steady state voltage is reached is signified by time T3 and the A/D conversion is carried out by taking the ratio of (T3-T2)/(T2-T1) which is the ratio of the sample current to the reference current. By using a crystal oscillator as the time reference, the number of pulses counted during time T3-T2 will be a digital representation of the sample current as all of the other elements in that ratio are known parameters.
At time T4 (FIG. 2B), power can optionally be turned off for the circuitry to conserve the power consumption of the instrument. Thus the starting condition will be the same as at T0. Alternatively, if a delay to the reset condition is undesirable, the powering down can be eliminated. Thus at time T4 the circuit will be at its reset condition and ready for the next conversion corresponding to time T1.
If the initial state of the circuitry is unknown, reset can always be accomplished by selecting I.sub.ref for the time necessary to reverse integrate the maximum I.sub.sp. ##EQU3##
It will be appreciated that the instant specification and claims are set forth by way of illustration and not limitation, and that various modifications and changes may be made without departing from the spirit and scope of the present invention.
Claims
What is claimed is:
1. A sensor-integrator circuit comprising: sensing means for producing a sample current to be integrated and which varies in accordance with a sensed parameter; a comparator having inverting and noninverting inputs, an output and a positive voltage supply input; charge storage means connected between the inverting input and the voltage supply input; means for applying a voltage to the voltage supply input and a reference current to the inverting input to produce a steady state positive voltage across the charge storage device; means for applying a reference voltage to the noninverting input of the comparator having a positive value less than and approximately equal to the steady state voltage; and control means for applying the sample current to the inverting input of the comparator instead of the reference current for a preselected known time period and thereafter applying the reference current to the inverting input.
2. The sensor integrator circuit according to claim 1, wherein the sensing means comprises a photodiode.
3. The sensor integrator circuit according to claim 2, wherein the charge storage means comprises a capacitor.
4. A method for converting a sensed parameter to a digital value comprising the steps of: converting the sensed parameter to a sample current varying in accordance with the sensed parameter; providing a comparator having inverting and noninverting inputs, an output and a positive voltage supply input; connecting a charge storage device between the inverting input and the voltage supply input; applying a voltage to the voltage supply input and a reference current to the inverting input until a steady state positive voltage is produced across the capacitor; applying a reference voltage to the noninverting input of the comparator having a value less than and approximately equal to the steady state voltage; applying the sample current instead of the reference current to the inverting input of the comparator for a preselected time interval whereby the voltage across the charge storage device drops below the reference voltage and the comparator output changes state and thereafter applying the reference current to the inverting input until the voltage across the change storage device reaches the steady state voltage and the comparator again changes state; and converting the time interval, from the end of the preselected time until the comparator again changes state, to a digital value.