Power-Off Detection Circuit for an Electronic Apparatus

The present invention relates to a power-off detection circuit for generating a power-off signal before a supply voltage completely changes to 0 V in the power-off state of an electronic apparatus.

A conventional typical power-off detection circuit is shown in FIG. 1 and comprises resistors R1 and R2, and a comparison circuit CMP. A supply voltage VP is divided by the resistors R1 and R2 to obtain a power source proportional voltage a, and the power source proportional voltage a is inputted in the comparison circuit CMP. Also, the comparison circuit CMP receives a reference voltage Vref showing a level somewhat lower than the supply voltage VP.

The power source proportional voltage a is compared with the reference voltage Vref by the comparison circuit CMP. When the power source proportional voltage a is lower than the reference voltage Vref, a power-off signal P is generated and outputted.

Recently, due to the miniaturization and lightening of the typical electronic apparatus, the power source capacity of many typical apparatus is reduced.

However, in the case where the power source capacity is reduced, it is possible that the above power-off detection circuit may generate and output the power-off signal P even when the power is set ON. For example, in the case where the power source capacity is not sufficiently great and when a control signal S is generated and outputted toward a comparatively heavy load in the electronic apparatus as shown in FIG. 2, the supply voltage VP decreases temporarily.

The level of the power source proportional voltage a divided by the decreased supply voltage VP is lower than that of the reference voltage Vref, and the power-off signal P is generated and outputted.

Accordingly, when the above power-off detection circuit is used in an electronic apparatus having a heavy load such as solenoid of the like, the power source capacity must be made larger than necessary.

In view of the above disadvantages of the conventional device, an object of the present invention is to provide a power-off detection circuit which correctly operates even when a heavy load is driven by a source having a small power capacity.

Another object of the present invention is to provide a power-off detection circuit which prohibits the generation of a power-off signal by detecting the start of the driving of a heavy load.

Other objects and further scope of the applicability of the present invention will become apparent from the detailed description given hereinafter. It should be understood, however, that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.

According to an embodiment of the present invention, an electronic apparatus having means for generating a control signal activating at least one heavy load comprises a voltage comparison means for comparing a power source proportional voltage with a reference voltage and outputting a power-off signal when the level of the power source proportional voltage is smaller than that of the reference voltage, and a power-off detection means responsive to the power-off signal of the commparison circuit for detecting the level of the control signal for the at least one heavy load and detecting a power-off condition of the electronic apparatus. The electronic apparatus further comprises voltage output means for outputting the power source proportional voltage derived by dividing the supply voltage by a ratio. Also, the power-off detection means for inhibiting further comprises prohibiting means the output of the power-off signal when the level of the control signal is high. When the output of the power-off signal is prohibited by the prohibiting means, the ratio is increased, or the level of the reference voltage is decreased.

In the above embodiment, when a plurality of heavy loads are provided and a plurality of control signals are generated, the power-off detection means comprises an OR circuit mens for calculating the logical sum of the levels of each of the plurality of control signals for the plurality of heavy loads, and a prohibition means for prohibiting the output of the power-off signal when the OR circuit means outputs a high level signal.

According to the present invention, a power-off detection circuit comprises a comparison circuit for comparing a power source proportional voltage with a reference voltage, an OR circuit means for calculating the logical sum of control signals of all heavy loads in an electronic apparatus, a comparison voltage level changing circuit for prohibiting the output of a power-off signal from the comparison circuit by increasing a division ratio of the power source proportional voltage to a supply voltage, or by decreasing the level of reference voltage only by a predetermined level. That is, when the heavy load is driven, the division ratio of the power source proportional voltage to the supply voltage is increased, or the reference voltage is decreased with the predetermined level, so that the level of the power source proportional voltage does not become smaller than that of the reference voltage.

The present invention will be better understood from the detailed description given hereinbelow and the accompanying drawings which are given by way of illustration only, and thus are not limitative of the present invention and wherein:

FIG. 1 shows a circuit diagram of the conventional typical power-off detection circuit;

FIG. 2 shows a wave form chart of FIG. 1;

FIG. 3 shows a circuit diagram of a power-off detection circuit according to an embodiment of the present invention; and

FIG. 4 shows a wave form chart of FIG. 3.

Referring now to FIG. 3, there is illustrated a circuit diagram of a power-off detection circuit of the present invention utilizing in an electronic apparatus having a heavy load such as a solenoid or the like.

Solenoids P1-Pn are connected with a supply voltage VP, and driven and controlled by transistors Tr1-Trn.

The ON-OFF control of the transistors Tr1-Trn are enabled by control signals S1-Sn, respectively. Further, the control signals S1-Sn are inputted to an OR circuit, so that the OR circuit calculates the logical sum of the control signals S1-Sn. The output of the OR circuit is introduced into a delay circuit R, so that the delay circuit R generates and outputs an off control signal E for the transistor Trp.

A dividing circuit A comprising resistors R1, R2, and R3 connected in series is connected to the terminal of the supply voltage VP. The transistor Trp is connected at the junction between the resistors R2 and R3. The transistor Trp is usually set in a ON-state (conductive) in relation with resistors R4 and R5, so that the resistor R3 become short-circuited. When the off control signal E from the delay circuit R is applied to the transistor Trp, the transistor Trp is set OFF (nonconductive), so that the resistor R3 is returned from the short-state to the operative condition.

The non-reverse (positive) input terminal of the comparison circuit CMP is connected between the resistors R1 and R2 of the dividing circuit A.

A reference voltage Vref which is generated and outputted from a reference voltage generator not shown in FIG. 3 is applied to the reverse (negative) input terminal of the comparison circuit CMP. Accordingly, the dividing circuit A and the transistor Trp form a comparison voltage level changing circuit.

The division ratio of the power source proportional voltage a, which is inputted into the comparison circuit CMP, to the supply voltage is changed in relation to the ON and OFF states of the transistor Trp.

According to the above power-off detection circuit, when all the plungers P1-Pn are not driven, the transistor Trp is set ON. Accordingly, a voltage developed by dividing a supply voltage VP with a division ratio R2/(R1+R2) is set as the power source proportional voltage a, and this power source proportional voltage a is applied to the non-reverse input terminal of the comparison circuit CMP.

Because the reference voltage Vref is much smaller than a power source proportional voltage a produced by the division of the above division ratio, the output terminal of the comparison circuit CMP is set and remains in a high level.

In this condition, if any of the control signals S1-Sn applied to the transistor Tr1-Tr2 are generated and outputted, the supply voltage VP decreases immediately by L, the (inductance)-component of the solenoids P1-Pn, and after a certain point, the supply voltage VP increases. In this time, if the division ratio of the dividing circuit A remains unchanged, the following operation occurs although the reference voltage Vref is constant.

In the event the power source proportional voltage a is decreased in accordance with the variation of the supply voltage VP the following occurs. Accordingly, when the level of the power source proportional voltage a become lower than that of the reference voltage Vref, the output terminal level of the comparison circuit CMP is set in the low level. But, when any one control signal S1-Sn is generated, the signal E for turning off the transistor Trp is generated and outputted through the OR circuit, the inverter IN, and the delay circuit R. Also, when the control signals S1-Sn are developed the transistor Trp is set after a short delay into off-state, so that the short-circuiting of the transistor R3 is released and the division ratio is set to (R2+R3)/(R1+R2+R3).

In the event the ratio of the power source proportional voltage a to the supply voltage VP is increased the following occurs. Accordingly, although the level of the power source proportional voltage a varies in accordance with the level variation of the supply voltage VP as shown in FIG. 4, the total level of the power source proportional voltage a is increased to a point t at which the level of the off control signal E is reduced. Thus, the power source proportional voltage a may not now be lower than the reference voltage Vref.

Thus, when any one control signals S1-Sn is set a high level, the division ratio of the division circuit A for preparing the power source proportional voltage a from the supply voltage is set larger, so that the level of the power source proportional voltage a is not lower than the reference voltage Vref.

In above embodiment, when the OR circuit outputs a high level signal, the division ratio of the power source proportional voltage a to the supply voltage VP is set higher. According to another embodiment of the present invention, when the OR circuit outputs a high level signal, the power source remains as it is, and the reference voltage Vref may be decreased only by a predetermined level.

According to above embodiment of the present invention, the output of the power-off signal produced by the variation of the supply voltage can be prevented, so that the power source capacity can be reduced. Also, the miniaturization and the lightening of the electronic apparatus may be accomplished as a power source capacity needed to operate the electronic apparatus can be reduced.

The invention being thus described, it will be obvious that the same may be varied in many ways. Such variations are not to be regarded as a departure from the spirit and scope of the invention, and all such modifications are intended to be included within the scope of the following claims.