Memory Circuit

1. Field of the Invention

The present invention relates to memory circuits composed of semiconductor elements and, more particularly, to a memory circuit using field effect transistors.

2. Description of the Prior Art

In a dynamic type random access memory (DRAM) composed of MOS field-effect transistors (MOSTs), the so-called "multi-strobe addressing" technique is frequently used. According to this technique, the DRAM receives row address signals through address input terminals in response to a row address strobe signal (RAS) and column address signals through the same address input terminals in response to a column address strobe signal (CAS). The multi-strobe addressing technique is disclosed in detail in U.S. Pat. No. 3,969,706. Such a memory has a row timing signal generator which generates a control signal for controlling a peripheral circuit for the row selection such as a row decoder and controlling a sense amplifier in response to the row address strobe signal, a column timing signal generator which responds to the column address strobe signal and the output from the row timing signal generator to generate a control signal controlling a column decoder, a column selector, a data input-output circuit, and a read-write control signal generator which responds to the column address strobe signal and a read-write signal (WE) to generate the read-write control signal controlling the data input-output circuit between read and write modes. Since the read-write control signal is generated in response to the column strobe signal, it has been difficult to bring the state of the memory immediately into the write mode even when the read-write signal is turned to a write level designating the write operation, and therefore the speed of the write operation is inevitally slow.

An object of the present invention is to provide a memory circuit which can conduct high-speed writing with a simple circuit construction.

The memory circuit according to the present invention is featured in that a first-stage input inverter receiving a read-write signal, which comes from the outside, is controlled directly by an external chip control signal such as the address strobe signal (e.g., CAS) or a chip enable signal.

In the present invention, the output of a first-stage input inverter is directly controlled by a chip control signal (e.g., CAS) so that the write operation can be conducted without any delay immediately after the chip comes into addressable state.

FIG. 1 is a block diagram of a dynamic memory circuit according to the prior art;

FIG. 2 is a circuit diagram of WE signal and the CAS signal input circuits and clock generator in the prior art;

FIG. 3 is a timing chart which serves to illustrate the input timings used by the circuits of FIG. 3;

FIG. 4 is a circuit diagram of write clock generators according to one embodiment of the present invention; and

FIG. 5 is a timing chart which serves to illustrate the input timings used by the circuits of FIG. 4.

A prior-art dynamic memory circuit will be described in the following with reference to FIG. 1.

Address input terminals A.sub.1 to A.sub.n are connected to a row address decoder 12 and a column address decoder 14 in common. In response to a row address strobe signal RAS incorporated through a buffer 16, a row timing clock generator G00 generates a clock .phi..sub.A for controlling the row decoder 12 and a clock .phi..sub.B for controlling a memory cell array 11.

A column address selection circuit 13 is controlled by the column decoder 14 so as to connect a column line to be accessed of the memory cell array 11 to a data inputoutput circuit 15. In response to a column strobe signal CAS incorporated through a buffer 18, a column clock generator G02 generates a clock .phi..sub.D for controlling the column decoder 14 and a clock .phi..sub.E for controlling the data input-output circuit 15. In response to an external readwrite signal WE received by a NOR gate 17 which also receives the output of the buffer 18, the write clock generator G02 generates a read-write control signal .phi..sub.C when the column strobe signal is in its active level. This control signal .phi..sub.C controls the input-output circuit 15 between read and write modes.

The construction and operation of a circuit block 20 formed of the buffer 18 which receives the column strobe signal CAS and the gate 17 which receives the write control signal WE will now be described in detail, with reference to FIGS. 2 and 3.

As shown in FIG. 2, the NOR gate 17 is composed of an enhancement MOST (EMOST) T10 having drain and gate connected to a power voltage V.sub.DD and a source connected to a node N10, an EMOST T11 having a drain connected to a node N10, a gate receiving the external signal WE, and a a source connected to the ground voltage, and an EMOST T12 having a drain connected to the mode N10, a source connected to the ground, and a gate fed with the output of the buffer 18. The buffer 18 is composed of an EMOST T20 having a drain and a gate connected to V.sub.DD and a source connected to a node N20, an EMOST T21 having a drain connected to the node N20, a gate receiving the external signal CAS and a source connected to the ground, an EMOST T22 having a drain and a gate connected to V.sub.DD and a source connected to a node N21, and an EMOST T23 having a drain connected to the node N21, a gate connected to the node N20, and a source connected to the ground.

A write operation called "Early Write" made by the circuit shown in FIG. 2 will be explained, by the timing chart illustrated in FIG. 3.

Row address signals are incorporated through the address input terminals A.sub.1 to A.sub.n into the row address decoder 12 (FIG. 1) when the row address strobe signal RAS controlling the reception of row address signals falls from a high level voltage sufficiently higher than a threshold voltage (hereinafter abbreviated to "V.sub.T ") of the EMOST to a low level voltage which is lower than the V.sub.T, and then column address signals are taken via the address input terminals into the column decoder 14 when the signal CAS falls from the high level to the low level. At this instance if the write signal WE is low, external data is input to the bit location selected by the row address and the column address. In Early Write operation in which both the CAS and WE are simultaneously made fallen from high to low in level, as shown in FIG. 3, the impedance of EMOST T21 receiving the signal CAS becomes high (i.e., turned off). Then, the output node N20 of the inverter composed of EMOSTs T20 and T21 becomes high to make the impedance of EMOST T23 low (turned on) so that the potential at the output node N21 of the inverter composed of EMOSTs T22 and T23 becomes low. From this instance, the CAS clock generator G02 is enabled. When the EMOST T11 receiving the low level signal WE is turned off, a portential at the output node N10 of the NOR gate 17 composed of EMOSTs T10 and T11 is still low because of EMOST T12 and becomes high only after EMOST T12 is turned off by the output N21 of the buffer 18. Therefore, the timing when the write clock generator G01 is enabled is delayed. Since this input circuit 17 for WE controls the start of operation of the write clock generator G01 by the output signal of the CAS buffer 18, a stand-by time b controlling that start by the signal CAS is required during the write in addition to an operation-completing time a of the write clock generator G01. As a result, the minimum time required for completing the write is the sum of (a+b). This makes it difficult to conduct the write operation at a high speed.

The circuits controlling the signal generators G01 and G02 according to the embodiment of the present invention will now be described with reference to FIG. 4.

In FIG. 4, an input circuit 17' for WE is composed of an EMOST T30 having a drain and a gate connected to V.sub.DD and a source connected to a node N30, an EMOST T31 having a drain connected to node N30, a gate receiving the external signal WE, and a source connected to GND, and an EMOST T32 having a drain connected to the node N30, a gate which is directly connected to the terminal receiving the signal CAS, and a source connected to GND. The buffer 18 is composed of an EMOST T40 having a drain and a gate connected to V.sub.DD and a source connected to a node N40, an EMOST T41 having a drain connected to the node N40, a gate receiving the external signal CAS, and a source connected to GND, an EMOST T42 having a drain and a gate connected to V.sub.DD and a source connected to a node N.sub.41, and an EMOST T43 having a drain connected to the node N41, a gate connected the node N40, and a source connected to GND. Then node N30 is connected to the write clock generator G01, and the node N41 to the CAS clock generator G02.

In an Early Write operation, the signals CAS and WE are simultaneously made fallen from high to low in level, as shown in FIG. 5. Both EMOST T31 receiving the signal WE at its gate and EMOST T32 receiving the signal CAS at its gate are turned off simultaneously, so that a potential at the node N30 becomes high immediately without taking the stand-by time b described with reference to FIG. 3. This is due to the direct connection of the gate of EMOST T32 to the CAS terminal. As a result, the minimum write-completing time is achieved, which is just the operation-completing time a of the write clock generator G01.

As has been described above, the circuit of FIG. 4 embodying the present invention can execute a write mode cycle in a time not containing the standby time b, when compared with the circuit of FIG. 2 according to the prior art.

As has been described above, according to the present invention, by controlling the output of the first-stage input inverter of an external read-write signal directly by an external chip control signal, the memory circuit can operate with a shorter write mode cycle than the prior art, thereby realizing a high-speed write operation. In a DRAM which can receive addresses in a multiplexed manner and which is adapted to be driven by RAS and CAS signals, a nibble mode which is conducted by repeating change in level of the CAS signal along to sequentially access consecutive columns is required to operate at a speed of at least three times that of a page mode. The present invention is especially effective to the nibble mode because a high-speed write can be realized with ease.