Differential Pair With Compensation for Effects of Parasitic Capacitance

This invention relates to a differential pair with compensation for effects of parasitic capacitance.

FIG. 1 of the drawings shows a conventional circuit arrangement comprising a differential pair of transistors Q1 and Q2. A circuit arrangement such as that shown in FIG. 1 may be used in an amplifier or a digital-to-analog converter (DAC). The transistors Q1 and Q2 receive complementary input voltages V and V at their bases, the voltages V and V swinging about a reference potential level V.sub.0. The collectors of the transistors Q1 and Q2 are connected through a load network to a reference potential level V.sub.CC, and the emitters of the transistors Q1 and Q2 are connected to the collector of a current source transistor Q3, which has its emitter connected to a reference potential level V.sub.EE. The base of the transistor Q3 is connected to a high gain feedback bias amplifier and draws a constant current or a desired value, dependent on the ratio of the resistance values of the resistors R.sub.E and R.sub.3, from the emitters of the transistors Q1 and Q2. The reference potential level V.sub.0 lies between the potential levels V.sub.CC and V.sub.EE. The output of the differential pair may be taken from the collectors of the transistors Q1 and Q2 and applied to a differential amplifier A, or alternatively a single-ended output may be taken from the collector of one of the transistors Q1 and Q2. Parasitic capacitances are associated with the collector of the transistor Q3. Therefore, when the differential input voltage changes, and brings about a change in the voltage V.sub.1 at the emitters of the transistors Q1 and Q2, a displacement current proportional to dV.sub.1 /dt is drawn from the emitters of the transistors Q1 and Q2. The displacement current is distributed between Q1 and Q2 in dependence upon the values of V and V. This capacitive displacement current causes perturbations in the output signal and increases settling time. This is particularly disadvantageous in the case of a DAC, because it increases the duration of the conversion cycle.

Moreover, when the voltage at the base of the transistor Q1 changes, charge is injected into the load network through the parasitic base/collector capacitance C.sub.jcl, and this causes a transient at the collector of the transistor. The voltage transients at the collectors of the transistors Q1 and Q2 are in opposite senses, and therefore they are added when the collector voltages are combined by the differential amplifier A.

In a preferred embodiment of the invention, first and second bipolar transistors are connected as a differential pair, and a third, current source transistor has its collector connected to the emitters of the first and second transistors and draws a first constant current. Fourth and fifth bipolar transistors are connected as a second differential pair with the collectors of the fourth and fifth transistors connected to the collectors of the first and second transistors respectively and with the bases of the fourth and fifth transistors connected to the bases of the second and first transistors respectively. A sixth, current source transistor has its collector connected to the emitters of the fourth and fifth transistors and draws a second constant current that is much smaller than the first constant current. All four transistors of the two differential pairs are essentially identical, and the two current source transistors have the same parasitic capacitances. Consequently, the displacement currents associated with the parasitic capacitance at the collector of the third transistor is replicated at the sixth transistor. The contributions of the two displacement currents to the collector currents of the differential pairs are common mode, and are substantially cancelled. Feedthrough at the base/collector junctions of the first and second transistors is at least partially cancelled by feedthrough at the base/collector junctions of the fourth and fifth transistors respectively.

For a better understanding of the invention, and to show how the same may be carried into effect, reference will now be made, by way of example, to the accompanying drawings in which:

FIG. 1 is a schematic diagram of a conventional differential amplifier, and

FIG. 2 is a schematic diagram of a differential amplifier embodying the present invention.

The differential amplifier shown in FIG. 2 is identical to that shown in FIG. 1 except that it includes a second differential pair Q4, Q5 and a second current source transistor Q6. The transistors Q3 and Q6 have the same collector/substrate and base/collector junction areas. Consequently, the collector/substrate capacitances C.sub.cs of the transistors Q3 and Q6 are the same, and the collector/base capacitances C.sub.jc of the transistors Q3 and Q6 are also the same. However, the emitter resistance R.sub.6 associated with the transistor Q6 is much larger than the emitter resistance R.sub.3 associated with the transistor Q3, and consequently the current I.sub.6 drawn by the transistor Q6 is much less than the current I.sub.3 drawn by the transistor Q3. In fact, the current I.sub.6 may approach zero.

The transistors Q4 and Q5 are identical to the transistors Q1 and Q2 (which are themselves identical). The collectors of the transistors Q4 and Q5 are connected to the collectors of the transistors Q1 and Q2, while the bases of the transistors Q4 and Q5 are connected to the bases of the transistors Q2 and Q1 respectively.

Because the transistors Q4 and Q5 are identical to the transistors Q1 and Q2, the voltage V.sub.1 at the emitters of the transistors Q4 and Q5 is nearly equal to the voltage at the emitters of the transistors Q1 and Q2. Consequently, the displacement current that flows in the emitter of the transistor Q5 is nearly equal to that which flows in the emitter of the transistor Q1, and the displacement current that flows in the emitter of the transistor Q4 is the same as that which flows in the emitter of the transistor Q2. Consequently, when a differential output is taken from the collectors of the transistors Q1 and Q2, the displacement currents are substantially cancelled.

A single-ended output may be taken, e.g. from the collector of the transistor Q1, and the transients caused by charge injected through the parasitic base/collector capacitances of the transistors Q1 and Q4 tend to cancel, since they are in opposite senses. It is, however, preferred that a full differential output be taken, as shown in FIG. 2, so as to achieve not merely cancellation of the transients due to the parasitic capacitances of the base/collector junctions of the transistors Q1 and Q2 but also cancellation of the displacement currents.

It will be understood that since the operation of the described circuit relies on matching of the transistors, the invention is particularly attractive for monolithic integration.

It will be appreciated that the present invention is not restricted to the particular embodiment that has been described and illustrated, and that variations may be made therein without departing from the scope of the invention as defined in the appended claims, and equivalents thereof. For example, the invention has been described with reference to bipolar transistors, it is equally applicable to field effect transistors, and may be implemented with, e.g., MOSFETs, JFETs or MESFETs or both bipolar transistors and FETs.