Emitter Coupled Logic Having Enhanced Speed Characteristic for Turn-on and Turn-Off

1. Field of the Invention

This invention relates to emitter coupled logic (ECL) and in particular relates to an emitter coupled logic gate having enhanced speed characteristics.

Emitter coupled logic gates are among the fastest types of digital circuit gates. However, ECL gates have not been able to capitalize on the full speed potential of ECL in inverter gates. Moreover, ECL gates do not handle capacitive loads particularly well. What is needed is a new type of logic circuit which takes better advantage of the potential speed of bipolar technology.

2. Description of the Prior Art

Referring to FIG. 1, there is shown a conventional ECL primitive inverter gate 10 with emitter follower output. The primitive gate 10 comprises a first input transistor Q.sub.A, a second input transistor Q.sub.B a reference transistor Q.sub.R, a current source transistor Q.sub.CS, a first load transistor Q.sub.L1, and a second load transistor Q.sub.L2. The inverter gate 10 operates between an input A and an input B to produce at an output at node 1 between the emitter of transistor Q.sub.L1 and the collector of transistor Q.sub.L2 an output A+B. The emitters of transistors Q.sub.A, Q.sub.B and Q.sub.R are coupled at a common node 3 to the collector of current source transistor Q.sub.CS. A current source bias voltage V.sub.CS is maintained at the base of transistors Q.sub.CS and Q.sub.L2. The load of transistor Q.sub.CS is through the emitter at a resistor R.sub.CS to the lowest reference voltage, herein a ground voltage. The load of transistor Q.sub.L2 is through a resistor R.sub.L in the emitter-to-ground circuit thereof. The collectors of transistors Q.sub.A and Q.sub.B are coupled in common to a node 2 and to the base of transistor Q.sub.L1. A collector load resistor R.sub.CL is coupled between the source voltage reference V.sub.CC and node 2. The collector of transistor Q.sub.L1 is connected to the V.sub.CC voltage. The collector of transistor Q.sub.R is connected to the V.sub.CC voltage. Finally, a reference voltage V.sub.BB is provided to the base of transistor Q.sub.R. Transistors Q.sub.L1 and Q.sub.L2 form the emitter follower circuit for the voltage on node 2.

Referring to FIG. 2, there is shown a conventional current mode logic (CML) primitive inverter gate 12. Current mode logic is similar to emitter coupled logic except that there is no emitter follower circuitry. One paper describing CML logic is "A 1500 Gate, Random Logic Large Scale Integrated (LSI) Masterslice", R. J. Blumberg and S. Brenner, IEEE Journal of Solid State Circuits, Volume SC-14 No. 5, page 818 (October 1979). In both of the circuits of FIGS. 1 and 2, there is an emitter dynamic resistance and a diffusion capacitance associated with the reference transistor Q.sub.R. The emitter dynamic resistance of Q.sub.R and the diffusion capacitance of Q.sub.R are in parallel and define an impedance effectively in series with the emitter of the input transistors Q.sub.A and Q.sub.B.

In accordance with the invention, the reference portion of a primitive current switch used in emitter coupled logic or current mode logic is modified by introducing means for filtering high frequency voltage changes, or transients, thereby slowing voltage change, at the common emitter node as the reference element in order to enhance the speed of turn on and turn off of the input elements. In particular, the reference transistor of a conventional ECL inverter gate or conventional CML inverter gate is replaced with a slow transistor, slow diode or a large capacitor in order to bypass the emitter dynamic resistance. The emitter time constant of the reference element Q.sub.R is thereby increased so that the voltage on the common current source node (node 3) does not change substantially when the base of the input elements change transiently. As a consequence, the collector output of the input element, such as transistor Q.sub.A, which is on or off switches significantly faster.

In a specific embodiment, the reference element Q.sub.R is constructed as a conventional transistor with the collector and emitter terminals reversed in a so-called inverted transistor configuration. The inverted transistor configuration has been found to be significantly slower in operation than in the conventional figuration. Alternatively, however, a slow diode, such as a PN type diode, may be placed between the reference voltage V.sub.BB and node 3.

The invention will be better understood by reference to the following detailed description taken in conjunction with the accompanying drawings.

FIG. 1 is a schematic diagram of a prior art ECL primitive inverter gate.

FIG. 2 is a schematic diagram of a prior art primitive CML inverter gate.

FIG. 3 is a schematic diagram of a first embodiment of a emitter collector coupled primitive inverter gate according to the invention.

FIG. 4 is a schematic diagram of a modified current mode logic (NCML) primitive inverter gate according to the invention.

FIG. 5 is a schematic diagram of a second embodiment of an ECCL gate according to the invention.

FIG. 6 is a second embodiment of an NCML primitive gate according to the invention.

FIGS. 1 and 2 have been described previously as prior art structures. Referring to FIG. 3, there is shown an emitter collector coupled logic primitive inverter gate 14 in accordance with the invention. For the sake of consistency, the labels of corresponding elements of each embodiment are the same. Reference is made to FIG. 1 for comparison with FIG. 3. In accordance with the invention, a reference transistor Q.sub.RR is provided at node 3. The reference transistor Q.sub.RR comprises a first electrode 16, a second electrode 18 and a third electrode 20. The first electrode 16 is comparable to the emitter electrode of a conventional fast transistor. The second electrode 18 is comparable to the base electrode of a conventional transistor, and the third electrode 20 corresponds to the collector electrode of a conventional transistor. However, in this configuration, the first electrode 16 and the third electrode 20 are inverted, that is, the first electrode 16 is coupled as a collector and the third electrode 20 is coupled as an emitter between the voltage source V.sub.CC and the node 3. The second electrode 18 is coupled to a bias voltage V.sub.BB.

The use of a structure such as the reference transistor Q.sub.RR of FIG. 3 effectively increases the time constant of the RC combination of the dynamic resistance and the diffusion capacitance of the reference transistor Q.sub.RR. The increase in the time constant provides filtering of high frequency voltage changes, or transients, and thereby a larger delay at the collector of the reference transistor Q.sub.RR on node 3. With the emitter time constant of Q.sub.RR (now inverted) increased at node 3, the voltage at node 3 will not change substantially when the voltage to the base of the input transistor Q.sub.A is moved high or low transiently. As a consequence, the transistor Q.sub.A can be turned on or off much faster, and the transistor Q.sub.A will have a correspondingly faster collector output.

Referring to FIG. 4, there is shown an NCML primitive gate 22 in accordance with the invention having a reference transistor Q.sub.RR similar to that of the embodiment of FIG. 3. In other words, the reference transistor Q.sub.RR is also a slow transistor, generally on the order of one order of magnitude or more slower than the input transistors Q.sub.A and QB. In addition, a diode D.sub.1 is provided between the collector voltage source and node 2 to which the collectors of input transistors Q.sub.A and Q.sub.B are coupled. Diode D.sub.1 is provided for limiting the possible saturation of the input transistors Q.sub.A or Q.sub.B in current mode logic operation. Separation would normally be caused by the transient current flowing in the reference transistor Q.sub.A during transition in the input signal from low to high voltage (presuming NPN transistor convention). While saturation is only temporary, the use of a saturation controlling diode minimizes the likelihood that saturation might even occur.

Tests of an emitter collector coupled logic gate 14 in accordance with the invention have shown the limiting delay of an ECCL gate to be on the order of 40% less than for a conventional ECL gate at the same power level. It is believed that the gain in speed is a result of greater available current for switching due to the longer time constant in the reference transistor. Moreover, it has been found that NCML logic gates in accordance with the invention switch even faster. NCML gates according to the invention also have superior capacitive load handling capability in comparison with conventional current mode logic. It is believed this is because the elements of an NCML gate have greater capacity for current drain so that external loads can be discharged faster.

FIGS. 5 and 6 illustrate alternative embodiments of an ECCL gate and NCML gate 26 which use a reference diode Q.sub.RR. There is the trade-off between the use of a reference diode and a slow reference transistor in accordance with the invention. A slow reference transistor has the advantage of less required space in integrated circuit design. The reference supply must have a good current capacity if the gain of the transistor is low. Alternatively a slow diode may be used instead of slow transistors as shown in FIGS. 5 and 6.

The invention thus described may be used in all inverting logic circuitry and can be mixed with conventional non-inverting logic circuits where necessary. A faster inverting output is therefore available for design of high-speed circuitry.

The invention has been explained with reference to specific embodiments. Other embodiments will be apparent to those of ordinary skill in the art. For example, a capacitor could be substituted for the reference elements to store charge and thus increase the time constant as desired. It is therefore not intended that this invention be limited except as indicated by the appended claims.