Low Forward-Voltage Drop SCR

The present invention relates to SCR devices, and in particular to integrated circuits including a self-commutating low forward-voltage drop SCR.

The usefulness of silicon controlled rectifier (SCR) devices is frequently related to the forward-voltage drop which occurs when the SCR is turned on. Typically, the SCR includes a four-layer structure wherein the forward-voltage drop is usually at least the sum of V.sub.be and V.sub.sat voltages of the transistor elements comprising the SCR device. It is therefore advantageous to reduce the forward-voltage drop of the SCR to enhance its performance. For instance, the reduction of forward-voltage drop will reduce the power dissipation of the SCR device when turned on, or reduce the voltage to which an associated capacitor may be discharged. Moreover, the SCR is required to be self-commutating, that is, to have the ability to turn off when the current flow ceases, and any reduction in forward-voltage drop may not inhibit SCR self-commutation.

The SCR according to the present invention has a reduced forward voltage drop by eliminating the SCR V.sub.be component. The SCR structure includes a separately powered latch circuit which controls an output transistor. The output transistor is saturated when the SCR latch is on, ensuring a minimum forward-voltage drop. An additional turn-off transistor is included to provide self-commutation. The turn-off transistor conducts only after the output transistor saturates, and which generates a turn-off signal to the latch circuit, which then turns the entire SCR device off. Furthermore, the SCR latch circuit, or the output transistor and turn-off transistor combination, can be implemented either separately or together with other circuit portions in an integrated circuit.

These and other features of the present invention will be further understood by reading the following, solely exemplary, detailed description of the invention, together with the drawing, wherein:

FIG. 1 is a schematic circuit diagram of the SCR in accordance with the invention, illustrated in association with typical external components;

FIG. 1A is a plot of the voltage across the SCR of FIG. 1; and

FIG. 2 is an exaggerated cross-sectional view of an integrated circuit embodiment of transistors Q.sub.2 and Q.sub.3 of FIG. 1.

The schematic circuit diagram 50 of the SCR is shown in FIG. 1. Also included in FIG. 1 are external components connected to form a typical circuit. A signal across the SCR is represented by a plot 64 in FIG. 1A demonstrating the operation of the SCR according to the present invention. The SCR includes a gate lead 52, an anode lead 54, and a cathode lead 56. In addition, a fourth lead 58 is included to separately power the SCR latch circuit.

The schematic circuit diagram 50 of the SCR includes an SCR latch circuit including transistor Q.sub.1 and Q.sub.4 connected to form a positive feedback structure. When one of the transistors Q.sub.1 or Q.sub.4 becomes conductive from a signal at the base of Q.sub.4, the other transistor also becomes conductive, maintaining the state. The current flowing through the latch is limited only by resistor R.sub.1, and is selected to provide only the current necessary to saturate the connected output transistor Q.sub.3. The gain of the loop including transistors Q.sub.1 and Q.sub.4 is reduced to less than 1 when additional current is drawn from the collector of transistor Q.sub.1 by transistor Q.sub.2, discussed below.

The SCR is on when the output transistor Q.sub.3 is driven into saturation by a current flow into the base region from the SCR latch circuit, provided by the current from Q.sub.1. When the SCR is on, Q.sub.3 provides the conduction path to the external elements having a forward voltage drop for the SCR including only the Q.sub.3 saturation voltage. Simultaneously, upon saturation of Q.sub.3, excess minority carriers are received by an additional turn-off transistor Q.sub.2, formed as a parasitic PNP transistor within a substrate of Q.sub.3, as discussed below. When the minority carriers are received by Q.sub.2, a current flow is drawn from the collector of transistor Q.sub.1 of the latch circuit, causing the loop gain to drop below unity, enabling the latch circuit to turn off if there is no signal at the base of Q.sub.4. The latch circuit, when in the off state, ceases to provide a current flow in the base region of transistor Q.sub.3, allowing the SCR to self-commutate and turn off.

According to the schematic circuit of FIG. 1, the collector, the emitter, and the base of Q.sub.3 corresponds to the SCR anode, cathode, and trigger, respectively. A representative external circuit includes a load resistor R.sub.2 connecting the anode to the V+ supply, and a capacitor C.sub.1 connecting the anode to the cathode, which is in turn connected to the power supply ground return. The quiescent or "off" state of the SCR allows the capacitor C.sub.1 to charge to the V+ supply voltage. The gate lead 52 receives a pulse signal, causing the SCR 50 to turn on, discharging the capacitor C.sub.1 at a high current rate. A plot 64 of the discharge of the capacitor C.sub.1 shows the minimal forward-voltage drop is shown at point 66, comprising only the V.sub.sat or saturation voltage of the output transistor Q.sub.3, discussed below. The self-commutating characteristic of the present invention permits the SCR to turn off at point 66 by substantially discharging the capacitor C.sub.1, wherein all remaining current flows through the gate resistor R.sub.3 to ground.

An exaggerated cross-section 80 of an integrated circuit implementation of transistors Q.sub.2 and Q.sub.3 is shown in FIG. 2. The transistors Q.sub.1 and Q.sub.4 typically exist on the same integrated circuit along with other functional elements, adjacent to and out of view of the structure shown in FIG. 2. However, the latch circuit may be implemented with other elements, such as discrete transistors. The structure 80 includes a substrate 82 comprising a P material and an epitaxial N.sup.- layer 84 disposed thereon. Transistor Q.sub.3 is shown in FIG. 2 and includes the emitter region 86, base region 88, and collector region 90, comprising N.sup.+, P.sup.+, and N.sup.+ type material deposition according to techniques known in the art. A P.sup.+ isolation region 92 is diffused through the N.sup.- epitaxial layer. The flow of minority carriers provided by the emitter region 86 to the collector 90 is controlled by the base region 88. When the transistor Q.sub.3 is initially turned on, all minority carriers are received by the collector 90. However, upon saturation, carriers begin to flow through the N.sup.- epitaxial layer to an isolation region 92, forming the collector of transistor Q.sub.2. A schematic representation of transistor Q.sub.2 is shown in FIG. 2. Thus according to the present invention, when transistor Q.sub.3 is saturated, minority carriers emerge from the base region 88, thereby creating the functional equivalent of an emitter region of transistor Q.sub.2 shown in FIG. 1, drawing current from Q.sub.1 and turning off the SCR latch circuit. The base junction of transistor Q.sub.2 corresponds to the collector region 90 of the structure 80 shown in FIG. 2. The supply of current produced from the receipt of minority carriers in the isolation region 92 is returned to the cathode circuit element connection by a connection external to the semiconductor element.

Other implementations, modifications, or substitutions by one skilled in the art are considered to be within the scope of the present invention, which is not to be limited except by the claims which follow.