Method of Dicing a Semiconductor Wafer

This invention relates to a method of dicing a semiconductor wafer.

With most semiconductor products, for example, transistors, diodes, light emitting diodes, and integrated circuits, a large number of elements are manufactured simultaneously on a large semiconductor wafer of Si, GaP, GaAs, saphire, etc. The semiconductor industry employs the term "dicing technologies" to refer to those techniques for obtaining a large number of high quality pellets from each semiconductor wafer. Two dicing methods are particularly well known in the art. These are the grinding-cutting method, using a blade or wire saw, and the scribing method, using a diamond point. When laying out the pattern of pellets on the surface of the semiconductor wafer, the distance between adjacent pellets has been minimized to maximize efficiency.

However, three restrictions exist with respect to the minimum distance permissible between adjacent pellets. The first restriction is the actual dicing width, the second restriction is the degree of precision to which the cutting machine can be adjusted, and the third restriction is the cracks and chips extending horizontally from the dicing line. Of these restrictions, the third, namely the generation of cracks and chips, creates the most significant limitation with respect to minimizing the distance between adjacent pellets.

FIG. 1(a) illustrates the product of the traditional grinding-cutting method, and FIG. 1(b) illustrates the product of the traditional scribing method. Similar elements in these FIGURES are assigned the same reference numbers. A semiconductor substrate 11 carries many active element areas such as 12, 13 (not shown in detail), and dicing occurs in the space between the adjacent active element areas 12, 13. Many cracks and chips 14 are generated horizontally from a dicing line 15. Therefore, the distance between active element areas 12, 13 (shown in FIGS. 1(a) and 1(b) as distance A--A) has to be 100-200 .mu.m to prevent the active element areas 12, 13 from being influenced by cracks and chips 14.

An object of this invention is to provide an improved method of dicing the semiconductor wafer to prevent cracks and chips along the dicing line from spreading to the active areas.

The method of dicing the semiconductor wafer according to this invention includes the step of forming a physical discontinuity on the surface of the wafer on both sides of a predetermined dicing line. The semiconductor wafer is then diced into pellets.

This and other objects and advantages of the invention will become more apparent and more readily appreciated from the following detailed description of the presently preferred exemplary embodiment of the invention taken in conjunction with the accompanying drawings, of which:

FIGS. 1(a) and (b) are perspective, expanded, partly sectional views of a device manufactured by conventional techniques;

FIGS. 2(a) and (b) are perspective, expanded, partly sectional views of devices manufactured by two embodiments of this invention;

FIGS. 3 to 5, inclusive, are expanded, sectional views, respectively, showing the principles of this invention and devices manufactured by other embodiments of this invention; and

FIGS. 6 to 10, inclusive, are expanded, partly sectional views of devices manufactured by still other embodiments of this invention.

This invention is based on the discovery that cracks and chips which are generated during dicing are transmitted in a direction perpendicular to the direction of maximum stress in the wafer. Thus, typically, cracks spread away from the dicing line into the wafer. However, in this invention, this transmission is restrained by the formation of a stress concentration in the path of the crack. Namely, the transmission of the cracks and chips is restrained by the formation of a physical discontinuity on the surface of the wafer on both sides of a predetermined dicing line.

Referring now to the drawing wherein like reference characters designate like or corresponding parts throughout the several views, FIGS. 2(a) and 2(b) illustrate products of this invention, with FIG. 2(a) illustrating the product of the grinding-cutting method and FIG. 2(b) illustrating the product of the scribing method. Active element areas 21, 22 are formed on a substrate 23 and many circuit elements (not shown) are manufactured in these areas. A change in the level of the surface of substrate 23, specifically a groove defined by walls 24, 25, is formed over a predetermined cutting line on the surface of substrate 23. The distance between walls 24, 25 (shown in FIGS. 2(a) and 2(b) as distance B--B) is 60 .mu.m, and the height of walls 24, 25 is 3 .mu.m. The groove defined by walls 24, 25 should not be made mechanically, but by chemical photo-etching or any other non-mechanical method. Thereafter substrate 23 is ground or scribed along the predetermined line to form deep separation 40 in FIG. 2(a) or shallow separation 41 in FIG. 2(b), respectively. As the result of this invention, the transmission of cracks and chips 26 is stopped at walls 24, 25. Therefore, it is possible to reduce the distance between the active element areas to 80-100 .mu.m (shown as distance C--C in FIGS. 2(a), 2(b)).

FIG. 3 illustrates the path of cracks and chips into substrate 23 with respect to the cutting-grinding embodiment of this invention. A crack generated at point A spreads via point B to point C where wall 24 stops the spreading. If wall 24 had not been there, the crack would have extended to point D along dotted line 27. The reason the crack stops at point C is as follows. The crack generated at the point A will tend to spread perpendicular to the direction of the main stress, that is into the substrate, roughly parallel to the surface. When the front of the crack reaches point B, wall 24 causes the concentration of stress to occur between point B and point C. Thus the crack tends to change direction and proceed to the surface, stopping at point C.

In another embodiment of this invention, as shown in FIG. 4, a surface level change, specifically a groove 28 is created to concentrate the stress. Cracks generated at the point E and H spread to points F and I, respectively, and stop. Groove 28 may have a depth of 3 or 4 .mu.m. FIG. 5 shows another embodiment of this invention, which includes the step of forming a semiconductor oxide film 29 on and partially into the substrate to create a surface level change. For cracks generated at points J and L, the stress concentrations happen between points K and M, respectively, so that the cracks are restrained at points K and M.

FIGS. 6 to 10 illustrate the product of other embodiments of this invention. Referring to FIG. 6, a surface level change, specifically a protuberance 30 is formed on the surface along and extending beyond the predetermined dicing line. Cracks are restrained at walls 31. In FIG. 7, a V-shaped notch 32 is formed over the predetermined dicing line, and cracks are restrained at edges 33 of notch 32, which edges are a surface level change. In FIG. 8, oxide films 34,35 are formed on the surface, on both sides of the dicing line. Cracks are restrained at the edges of these oxide filxs. FIG. 9 illustrates the product of another embodiment of this invention, which combines the embodiments shown in FIGS. 6 and 8. Oxide films 36, 37 are formed beside protuberance 38, and cracks are restrained more certainly by these stress concentration portions. In FIG. 10, a uniform thermal oxide film 39 is formed on the surface of the substrate including the predetermined dicing line and adjacent thereto. Almost all of the cracks from the dicing operation are transmitted into oxide film 39, so that the substrate is not influenced. The thickness of oxide film 39 is preferably 200-600 Angstroms to ensure that the substrate is not disturbed.

In the above-mentioned embodiments of this invention, the physical discontinuities must be formed on both sides of the predetermined dicing line. Therefore, cracks and chips are restrained and stopped by the above-mentioned physical discontinuities. The different materials used as the physical discontinuities are suitable films having good adhesion and affinity characteristics, for example, thermal oxide film, nitride film and metal film.

Many changes and modifications in the above-described embodiments can, of course, be carried out without departing from the scope of the present invention, that scope being defined only by the scope of the appended claims.