Digital Voice Transmission Having Improved Echo Suppression

This application is related to application Ser. No. 471,038, filed Mar. 1, 1983, for DIGITAL VOICE COMPRESSION HAVING A DIGITALLY CONTOLLED AGC CIRCUIT AND MEANS FOR INCLUDING THE TRUE GAIN IN THE COMPRESSED DATA; application Ser. No. 471,137, filed Mar. 1, 1983, for DIGITAL VOICE TRANSMISSION HAVING IMPROVED ECHO SUPRESSION; and application Ser. No. 471,139, filed Mar. 1, 1983, for DIGITAL VOICE COMPRESSION HAVING A DIGITALLY CONTROLLED AGC CIRCUIT AND MEANS FOR INCLUDING THE TRUE GAIN IN THE COMPRESSED DATA.

The present invention relates to digital voice transmission over telephone lines and is particularly useful in digital voice transmission in which a digitized voice signal of, e.g., 64,000 bits per second (bps) is compressed to, e.g., 2,400 bps for transmission over the telephone bandwidth, with improved echo suppression being used to improve system operation.

It is well known in the prior art to digitize the analog signal output of, e.g., a telephone microphone, representing a voice signal, in order to transmit the digital data over a telephone line. The digitized signal, which may be converted back to an analog representation of the digital data for the purpose of transmission over the telephone lines, as is also well known in the art, is less susceptible to noise on the telephone line, is capable of multiplexed channel operation in the telephone bandwidth, reduces crosstalk and enables relatively easy digital encryption for secure transmission.

The digitized voice signal, which typically is at, e.g., 64,000 bps, cannot be readily sent within the available approximately 3,000 Hz bandwidth of the telephone lines or be readily sent multichannel at that bit rate within the available telephone line bandwidth. To enable more convenient transmission and/or multiplexed transmission, compression of the 64,000 bps digitized voice signal is employed, as is known in the art. One method of compressing the 64,000 bps to, e.g., 2,400 bps is to use a linear predictive coding technique known in the art, a discussion of which is found, for example, in Markel, Gray, Jr. & Wakita, "Linear Prediction of Speech Theory and Practice," Speech Communication Research Laboratory, Inc. Monograph No. 10 (1978), the disclosure of which is hereby incorporated by reference. With compression to 2,400 bps, four simultaneous channels of 2,400 bps each can be multiplexed via a modem onto a 9,600 bps data stream transmitted over the bandwidth of the analog telephone lines.

The linear predictive coding technique employs digital filtering of the 64,000 bps digitized voice in digital resonating filters. Only digits representative of fundamental frequencies within the analog voice signal are selected in the compression to 2,400 bps. Speech is made up of pitch (voiced and unvoiced) and amplitude components, with the pitch being derived from the action of the human vocal cords. Pitch ranges vary from adult males, 50-150 Hz, adult females, 90-450 Hz and children, 125-575 Hz. Thus, much of the fundamental frequencies in the voice of a telephone talker is eliminated from the approximately 300-3000 Hz telephone bandwidth. However, fundamental pitch frequencies can be determined from, e.g., second or third harmonics. Thus, e.g., 360 Hz is the second harmonic of 180 Hz and the third harmonic of 120 Hz. It is thus possible in the linear predictive compression technique to transmit a compressed form of digitized speech representing the fundamental pitch frequencies, the voiced speech component, and the unvoiced speech component to synthesize these at the receiver end to simulate actual speech, as is all well known in the art. In synthesizing speech at the receiver end, the unvoiced components are represented by white noise, i.e., random binary bits, which, when synthesized with the voiced components in the proper proportion, result in simulating actual speech, when the resulting synthesized digital signals at the receiver end, now expanded to 64,000 bps, are passed through a digital-to-analog converter, as is also known in the art. The linear predictive coding technique uses a linear prediction algorithm, e.g., LPC-10.

Fundamentally what the linear predictive coding does is to generate a set of, e.g., 10 numbers (envelope prediction factors) per frame at the transmitter, based upon the actual data taken from the analog-to-digital conversion of the analog speech signal, at 64,000 bps. These 10 numbers enable the receiver end to generate by use of the linear predictive algorithm a full set of, e.g., 180 points per frame, e.g., 64,000 bps digitized voice. The 10 numbers per frame, plus six bits representing pitch, six bits representing RMS gain and a sync bit are transmitted every frame, which amounts to 2400 bps. A frame in the example of the present invention is 22.5 milliseconds. The 10 numbers are generated in the transmitter from an analysis of the envelope of the digitized voice signal in the frequency domain, and enable the reconstruction of the envelope at the receiver end. Those skilled in the arts of speech synthesis and compression will recognize the terms "gain" and "RMS gain" as used herein refer to a digitally coded speech synthesis parameter used in LPC and other speech synthesis techniques. In the speech synthesis and compression arts, these terms generally relate to the energy, power or signal level averaged over a short sample of speech. A more precise mathematical definition of the term may be found in numerous references related to speech analysis and synthesis using Linear prediction techniques, e.g. "Digital Processing of Speech Signals, " by Radner and Schaefer, Prentice-Hall, Inc. 1978, pp. 396-455.

There are presently in use both two-wire and four-wire telephone transmission links. In the two-wire system, analog speech or data signals are transmitted in both directions with two wires. In the four-wire system there are two wires, each with an associated ground wire, e.g., one for transmitting and one for receiving.

Because of processing delays inherent in the compression/expansion of digitized voice, echo suppression is of crucial importance. The prior art has not adequately solved this problem.

The present invention relates to echo suppression, which includes software implementation in the present invention enabling suppression of the same echo signal at its originating end of the transmission link and at the receiver end, and also includes use of, e.g., an operational amplifier hybrid circuit.

The problems enumerated in the foregoing have not been intended to be exhaustive, but rather are representative of problems which have tended to impair the effectiveness of limited bandwidth, e.g., telephone bandwidth, digital voice transmission apparatus used in the prior art, particularly those using multichannel transmission within the telephone bandwidth. Other noteworthy problems may also exist; however, those presented above should be sufficient to demonstrate that limited bandwidth, e.g., telephone bandwidth digital voice transmission apparatus appearing in the prior art have not been altogether satisfactory.

Similarly, the foregoing examples of the more important features of the present invention have been given rather broadly in order that the detailed description thereof which follows may be better understood and the contribution to the art better appreciated. There are, of course, additional features of this invention that will be described hereinafter and which will form the subject matter of the appended claims.

These other features of the present invention will become apparent with reference to the following detailed description of a preferred embodiment of the invention in connection with the accompanying drawings, wherein like reference numerals have been applied to like elements, in which:

FIG. 1 shows a block diagram of an analog input/output circuit for digitized voice compression/expansion and employing the automatic gain control and echo suppression features of the present invention;

FIGS. 2 and 2A are a more detailed schematic diagram of the circuit of FIG. 1;

FIG. 3 shows a block diagram of a digital voice synthesizer employed in the receiver of a voice transmission link using the present invention;

FIG. 4 shows a flow chart for software implementation of automatic gain control in accordance with the present invention;

FIGS. 5 and 5A show a flow chart for software implementation of echo suppression in accordance with the present invention.

FIG. 6 shows a further detail of the automatic gain control circuit according to the present invention; and,

FIG. 7 shows the timing of an analog-digital/digital-analog converter in accordance with the present invention.

Shown in FIG. 1 is a block diagram of an analog input/output circuit 10 for digitized voice compression and expansion in accordance with the present invention. The circuit 10 is adapted for connection either to a two-wire or four-wire telephone transmission link and thus has a two-wire to four-wire interface 12 and a four-wire interface 18. The two-wire to four-wire interface 12 is connected to two-wire telephone transmission lines 14 and 16. The four-wire interface 18 is connected to a telephone receive link 20, having an associated ground connection 22, and a telephone transmission link 24, having an associated ground connection 26.

Each of the two-wire to four-wire interface 12 and four-wire interface 18 is connected to a spectrum shaping amplifier 32. The spectrum shaping amplifier 32 is connected through a suitcase strap or a selector switch 34 to an automatic gain control (AGC) section 36, with the switch 34 also having a position selecting an AGC 36 bypass through a 47 Kohm bypass resistor 38. The outputs of the AGC 36 section and the bypass resistor 38 are connected to the input filter half 46 of the bandpass filter 44 which passes only energy in the telephone line bandwidth from about 300-3000 Hz. The output filter half 48 of the same bandpass filter 44 is connected to the telephone handset speaker input 49 of the two-wire to four-wire interface 12 and to the telephone handset speaker input 51 of the four-wire interface 18.

The input filter 46 is connected to an analog-to-digital converter half 52 of an analog-to-digital/digital-to-analog converter 50 (A/D/A converter), the output of which is serialized digital data at 64,000 bps, representative of the analog input to the analog-to-digital half 52. This serialized data at 64,000 bps is passed to a serial-to-parallel converter 58 which provides an 8-bit word on output line 62 to an RMS linear prediction analyzer portion of a linear prediction processor 41. The linear prediction analyzer portion of the processor 41 performs the compression of the 64,000 bps output of the serial-to-parallel converter 58 to 2,400 bps for transmission and a linear prediction synthesizer portion of the processor 41 performs an expanding conversion of 2,400 bps received data to eight-bit words at 64,000 bps, which is an input on line 64 to a parallel-to-serial converter 60. The 2,400 bits as compressed by the processor 41 is transmitted via output 43 to, e.g., a modem (not shown) to a remote location, and the 2,400 bps as expanded by the synthesizer portion of the processor 41 is that which has been received on input 45 from a remote location, e.g., through a modem, (not shown) and the expanded 64,000 bps is used locally to drive, e.g., a telephone handset speaker (not shown). The parallel-to-serial converter 60 is connected through a digital-to-analog converter 54 half of the A/D/A converter 50 and a suitcase strap 56 to the output filter half 48.

The RMS analyzer portion of the processor 41 has a PDI section which provides an eight-bit control signal on line 42 to the AGC section 36, depending upon the value of the root mean square (RMS) determined in the processor 41 during the compression function, as will be more fully explained below.

Shown in FIGS. 2 and 2A is a more detailed schematic view of the circuitry of FIG. 1. The two-wire to four-wire interface contained within phantom lines 12 is shown to have an off-hook detector amplifier 66, the negative input 68 of which is connected to RING line 16 through a 160 Kohm resistor 72. The RING line is connected to system ground, through a 47 ohm resistor 70. The negative input 68 of the amplifier 66 is connected to system ground through a 1 microfared capacitor 74.

The positive input 76 of the amplifier 66 is connected to system supply voltge V.sub.cc through a 10 Kohm resistor 78 and is connected to system ground through the parallel connection of a 1.6 Kohm resistor 80 and a 0.01 microfarad capacitor 82. The output of amplifier 66 is connected to an OFF HOOK line, which gives an OFF HOOK enabling signal to the analyzer 41 software.

The two-wire to four-wire interface 12 is also shown to have a high voltage ringing circuit connected to 180 V through a diode 84. The diode 84 is a 1N4004 rectifier diode. The high voltage ringing circuit includes transistors 86, 88 and 90. Transistor 86 is a PNP transistor, e.g., a 2N5415, having its base connected through a 4.7 Kohm resistor 92 to the diode 84 and through a 27 Kohm resistor 94 to the collector of an NPN transistor 90, e.g., a 2N3439 the emitter of which is connected to ground. The emitter of the transistor 86 is connected to the diode 84 through a 47 ohm resistor 98 and the collector of the transistor 86 is connected through a 47 ohm resistor 100 to the collector of an NPN transistor 88, e.g., a 2N3439, the emitter of which is connected to ground.

The bases of transistors 88 and 90 are connected to TTL level signals Q1.0.NH and Q2.0.NH through, respectively, an 82 Kohm resistor 91 and a 360 ohm resistor 93.

A node 102 between the collector of the transistor 86 and the resistor 100 is connected to a node 104 between the anode of a diode 106 and cathode of a diode 108. The cathode of the diode 106 is connected to the cathode of the diode 84 and the anode of diode 108 is connected to ground. The node 104 is connected to the TIP line and to the cathode of a diode 110, the anode of which is connected to a node 112. Each of the diodes 106, 108 and 110 are IN4004 diodes.

Node 112 is connected to a +12 V bias supply through an 82 ohm resistor 114 and an 82 ohm resistor 116, a node 118 between which is connected to ground through a 0.01 micro-farad capacitor 120. Node 112 is connected to the positive input 122 of an impedance matching hybrid operational amplifier 124 (hereinafter "the hybrid operational amplifier"). The negative input 125 of the hybrid operational amplifier 124 is connected to node 112 through a 1.2 Kohm resistor 128 and a 1.2 Kohm resistor 126. The hybrid operational amplifier 124 has a negative feedback loop consisting of a 27 ohm resistor 130, a 100 ohm variable resistor 132, a second 100 ohm variable resistor 134 and a second 27 ohm resistor 136, with a 55 millihenry inductor 138 connected between the variable resistors 132, 134 and the output of the hybrid operational amplifier 124. The output of the hybrid operational amplifier 124 is connected to a node 144 through a 0.068 microfarad capacitor 146 and a 9.1 Kohm resistor 148. Node 144 is the output 28 of two-wire-to-four-wire interface 12 and is connected to the output 30 of the four-wire interface 18, described in further detail below, through a 0.033 microfarad capacitor 140 and an 18 Kohm resistor 142.

Node 144 is connected to the negative input 150 of the spectrum shaping operational amplifier 152 contained within section 32, the positive input 151 of amplifier 152 is connected to ground. The operational amplifier 152 has a negative feedback loop to the negative input 150 through a 39.2 Kohm resistor 154. The output of the operational amplifier 152 is connected to switch 34, shown in FIG. 2A, through a 0.068 microfarad capacitor 153.

One position of switch 34 directs the output of operational amplifier 152 to the AGC circuit 36 and a 47 Kohm AGC input resistor 156 connected to ground. The AGC circuit 36 is, e.g., an AD7524 made by Analog Devices of Norwood, Mass. The AGC circuit 36 has inputs D7-D0 from PDI pins PDI07-00 from the analyzer 41 (shown in FIG. 1) and CS and CW inputs from PDICS3 and PDI WRTL from the analyzer 41, with the CS and CW inputs also connected to V.sub.CC through 1 Kohm resistors 155 and 157, respectively.

The output, OUT 1, of the AGC circuit 36 is connected to the VF.sub.x I.sup.- input of an Intel 2912 filter 44, which VF.sub.x I.sup.- input is also connected to a second position of switch 34 through the 47 Kohm AGC bypass resistor 38. The output, OUT 1 of the AGC 36 is also connected to ground through a zener diode 158, e.g., a 1N5711 diode made by Hewlett-Packard. The VF.sub.x I.sup.+ input to the filter 44 is grounded. The GS.sub.x pin of the filter 44 is connected to RFB in the AGC circuit 36 through a 39 Kohm resistor 160. The V.sub.cc pin of the filter 44 is connected to V.sub.cc and also is connected to ground through a 0.01 microfarad capacitor 162. The CLKO pin of the filter 44 is connected to V.sub.cc through a 1 Kohm resistor 166. The VF.sub.x output pin VF.sub.x 0 of the filter 44 is connected to the VF.sub.x input of the analog-to-digital half 52 of the A/D/A converter 50 through a 0.3 microfarad capacitor 164 and to the AUTO input pin of the A/D converter through voltage dividing resistors 170, a 150 Kohm resistor, and 172, a 332 ohm resistor, and through a 475 Kohm resistor 176, connected to the node 174 between the resistors 170 and 172. The A/D/A converter 50 is an Intel 2911.

The VFRI input pin of the output half 48 of the filter 44 is connected through a switchcase strap or a switch 56 to either the VF.sub.x pin or the VFR pin of the A/D/A converter 50. The C1X and C2X pins of the A/D/A converter are connected through a 2200 picofarad capacitor 178.

The CLKC pin of the filter 44 is connected to the IOCLK line. The CLKC pin on the A/D converter 50 is connected to V.sub.cc through a 1 Kohm resistor 180. The TS.sub.x pin on the A/D/A converter 50 is connected to the RE pin on the serial-to-parallel converter 58 and the CI pin on the parallel-to-serial converter 60, and also is connected to a +5 v source through a 1 Kohm resistor 186.

The CLK.sub. x pin on the A/D/A converter 50 is connected through an inverter 182 to the CP pin on the serial-to-parallel converter 58 and to the CLK .sub.R pin of the A/D/A converter 50. The QH pin of the parallel-to-serial converter 60 is connected to the DR pin of the A/D/A converter 50. V.sub.cc of the A/D/A converter 50 is connected to V.sub.cc across a 0.01 microfarad capacitor 184. The D.sub.x pin of the A/D/A converter 50 is connected to the DA pin of the serial-to-parallel converter 58.

The DE pin of the serial-to-parallel converter 58 is connected to the AD and NL line. The S/P, SE and CLR pins of the serial-to-parallel converter 58 are connected to the PULLUP 2 line. A pair of flip-flops 188 and 190 serve to generate an interrupt signal on the ADINT line and a reset signal on the ADRST line in response to a clock signal on the SRCLK line. This is a timing function to inform the analyzer 41 when data is ready to be sent from the serial-to-parallel converter 58 and data is ready to be received by the parallel-to-serial 60. Also the flip-flops 188 and 190 control the timing of transfer of data from the A/D/A converter 50 to or from the converters 58 and 60. The flip-flops 188 and 190 are connected to V.sub.cc through a 1 Kohm resistor 191.

Negative voltage of -5 v is supplied to V.sub.BB of the filter 44 across a 1 microfarad capacitor 192, and to V.sub.BB of the A/D/A converter 50, from an A79M05 voltage regulator 194 (shown in FIG. 2) made, for example, by Fairchild of Mountain View, Calif., which is supplied with -12 v across a 2 microfarad capacitor 196.

As shown in FIG. 2 the output VF.sub.R 0 of filter 44 for driving the speaker in the telephone handset is connected through a 10 Kohm variable resistor 198 and a 10 Kohm resistor 200 to the negative input 202 of an operational amplifier 204, the positive input 206 of which is connected to ground through an 8.2 Kohm resistor 208. The operational amplifier 204 has a feedback loop to the negative input 202 thereof through a 27 Kohm resistor 210.

The output of the operational amplifier 202 is connected to a node 212, which is connected to a node 214 between the resistors 126 and 128, and forms the output for the signal to be passed through the two-wire to four-wire interface to the TIP line 14 for driving the telephone speaker in the full duplex system on the tip line 14. Node 212 is also connected to the four-wire interface 18 through an 18 Kohm resistor 216.

The telephone speaker drive line 24 is connected through a 619 ohm resistor 230 to the output of an operational amplifier 220, a negative input 218 of which is connected to the resistor 216 and a positive input 221 of which is connected to ground through a 13 Kohm resistor 222. The operational amplifier 220 has a feedback loop connected to the negative input 218, including the parallel connection of a 9.1 Kohm resistor 228.

FIG. 3 shows a block diagram of a synthesizer 249 contained in the processor 41 in the present invention. During each frame of 54 bits contained within the 2,400 bps received from the remote location via, e.g., a modem (not shown), the synthesizer portion of the processor 41 receives through a processor 240 six bits of decoded data representing pitch, six bits of data representing gain, 1 sync bit, and 10 words of variable bit length from 5 to 2, totalling 40 bits of data from which the synthesizer 249 contained in the processor 41 software, using the linear predictive algorithm, generates 180 points defining the frequency spectrum envelope of the analog speech to be synthesized. The pitch data is employed to drive an oscillator 250 at the proper pitch. If pitch for that frame is 0, then an electronic switch 252 in the synthesizer 249 is in the position to be supplied with random digital numbers, i.e., noise, from a random number generator 254. The oscillator 250 is connected to the switch 252 through a filter 256 which spreads the spectrum of the oscillator 250 about its oscillating frequency for better approximation of speech by the synthesizer 249. When the switch 252 is the position shown in FIG. 3, the voicing decision is a voiced decision and when it is in the position to receive noise, it is an unvoiced decision.

A filter 258 is an adjustable digital filter, the output of which is controlled by the 10 numbers defining the frequency spectrum envelope for that frame, as generated by the synthesizer portion of the processor 41. This results in an output of the filter 58 which corresponds quite closely to the analog speech signal in the time domain originally digitized and compressed for transmission. This signal is amplified in a gain amplifier 260 according to the value of the gain (RMS) for that frame. This value is equal to the measured RMS, which the analyzer 41 at a remote location computed in performing the linear prediction coding, adjusted for the gain or attenuation, if any, introduced in the AGC section 32 at the remote location to ensure proper operation of the analyzer 41 at the remote location in compressing the digitized voice at 64,000 bps to 2,400 bps by use of the linear prediction algorithm. Therefore it is the true gain necessary to duplicate the original analog speech in volume.

The software implementation of automatic gain control at the speaker's end of the transmission link provided by the analyzer 41 at that end during voice compression is shown in the flow chart of FIG. 4. Modification of the gain in the AGC 36 is dependent upon the RMS value in the analyzer 41. A programmed data processor or hard wired large scale integrated circuit, e.g., a microprocessor controller in the analyzer 41 starting at start 300 (AGAINC) first sets the values for VMAX=85, RANGE=0.63096, IDEAL=512 and VINC=4 in block 302. A decision is then made in block 304 between whether the voicing decision in a given frame is a voiced decision or unvoiced decision, i.e., is there a pitch value or is pitch=0. If it is unvoiced the count VCNT in an AGC accumulator within the microprocessor in the analyzer 41 is decremented by 1 in block 305. The count VCNT in the accumulator is then checked in block 306 to see if it is greater than or equal to zero. If it is not greater than or equal to zero the count VCNT is set at zero in block 308.

Returning to block 304, if the decision is a voiced decision the AGC1 loop is started at 310. The VCNT is incremented in block 312 by VINC which equals 4. The present value of RMS in the analyzer 41, ARMS, is then compared in block 314 to see if it is greater than the most recent peak value AVENG of ARMS. If it is greater, then AVENG is set to equal present ARMS in block 316 representing now the most recent peak. Regardless of whether AVENG needs to be reset, the accumulated value of the AGC accumulator VCNT is then compared in decision block 318 to see if it is less than the preselected value of VMAX, in this case 85. If it is, the no change NOCHNG instruction is initiated in block 320. The result of the unvoiced instructions in blocks 305, 306 and 308 is also to ultimately initiate NOCHNG, as shown in FIG. 4.

Returning now to block 318, if VCNT is not less than VMAX, VCNT is set to zero in block 320 and a decision is made whether to adjust the gain of the AGC 36. The most recent peak ARMS, AVENG, is compared in block 322 to see if it is greater than or equal to generally a midpoint selected value, IDEAL, in this case 512, and also if the difference between AVENG and IDEAL is less than or equal to some value, RANGE. If it is not .gtoreq. to IDEAL and the difference is not .ltoreq. RANGE then value GCNT in the gain accumulator is incremented in block 324 to GCNT +1. After this, or if the decision in block 322 is a yes decision, then the DNTST instruction is started in block 326. In block 328 IDEAL is compared to see if it is greater than or equal to AVENG and if the difference between the AVENG and IDEAL is less than or equal to RANGE. If IDEAL is not less than or equal to AVENG, and the difference is not less than RANGE, the count GCNT is decremented by 1 in block 330. Regardless of whether GCNT is decremented, the next instruction executed is to start NOCHNG at block 331. If the count in the gain accumulator GCNT is less than 0 it is reset to 0 by the combination of the steps in blocks 332 and 334. If GCNT is not less than 16 it is reset to 15 by the combination of the steps in blocks 336 and 338. The next instruction in block 339 provides for a look up in a memory table in the analyzer 41 of a gain control signal to be provided to the AGC 36 on lines PDI07-00 from the analyzer 41, based upon the value of GCNT.

Thus the AGC controller in the analyzer 41 microprocessor assigns a value of -1 to unvoiced decisions and +4 to voiced decisions. These are accumulated from frame to frame during the processing by the analyzer 41 for making gain adjustment decisions for use in the AGC 36 and correspond to whether there was data in the respective frame indicating that pitch was present in the frame, as transmitted to the remote location in the frame data. Only if VCNT exceeds VMAX is a gain change permitted. This ensures that a speech-like signal is present and that enough intervals have occurred on which to base a gain decision. Thus the AGC 36 in the apparatus of the present invention is adjusted only in response to speech signals and only to keep these signals within the range necessary for proper processing by the analyzer 41 in accordance with the linear predictive algorithm.

Once VCNT exceeds VMAX, an AGC 36 gain decision is made and VCNT is then set to zero to prevent rapid gain changes in the AGC 36. The parameter used during voiced intervals is the most recent peak ARMS in the analyzer 41 (AVENG) which is compared with the value representative of the desired RMS. The sign of the difference, as determined in the software, determines the direction of the gain change. No change is made if the magnitude of the difference is less than a preselected value, RANGE, since no change is needed if the magnitude of the difference is such that the measured ARMS energy is close to the selected IDEAL. If the difference is greater than the selected RANGE then a one-step change of .+-.2 db is made in the AGC 36, and AVENG is reset to zero so that the next measured ARMS will become AVENG.

The gain change is made by incrementing or decrementing by one a four-bit counter GCNT within the microprocessor in the analyzer 41. The count GCNT in this counter is used within the software in the analyzer 41, used for controlling the AGC 36, to address a corresponding memory location and the new gain setting contained therein is written to the AGC 36 on lines PDI07-00.

IDEAL is set at 512, which is half scale for the RMS parameter. RANGE is a multiplier 0.63096 which corresponds to 4 db (4=20 log (1/0.63096). VMAX is empirically set at 85.

The analyzer 41 receives data at 64,000 bps from the serial-to-parallel converter 58 and compresses this data according to the linear predictive algorithm. In the process it computes RMS on a frame-by-frame basis and performs the decision-making process of whether to adjust the gain of the AGC 36. The gain of the AGC 36 is thus available data for the analyzer 41, which transmits, via, e.g., a modem (not shown), the true gain (i.e., the ARMS adjusted by whatever value the AGC 36 gain has been adjusted to maintain the analyzer 41 in the proper range for accurately performing the linear prediction algorithm) as part of the frame data, to an analyzer 41 at a remote location. Using the actual data for a frame, the analyzer 41 computes the best set of, e.g., 10 linear prediction algorithm factors, from which the remote analyzer 41 can reconstruct the full 180 points of digital data representing the frequency domain spectrum envelope for synthesis by a synthesizer 249 contained in the remote analyzer 41 to simulate a voice signal which is an analog signal.

The analyzer 41 also receives compressed 2,400 bps data from a remote analyzer 41 via, e.g., a modem (not shown). Using this data, and the linear predictive algorithm, it generates a frequency domain spectrum envelope for each frame. It also receives pitch and gain data for each frame and from the pitch, gain and envelope data it synthesizes in its synthesizer portion 249 a 64,000 bps digital voice signal which is converted in the A/D/A converter 50 to drive the speaker in the local telephone handset.

Echo suppression of the present invention is partially software implemented and includes also circuitry within the two-wire-to-four-wire interface 12 which functions as an echo suppressor in the manner of balancing network couplers in the prior art. These employ transformers to accomplish echo suppression by balancing impedances. The echo suppressor of the present invention is particularly suited to the present system employing digitized voice. In the interface circuitry of the present invention the hybrid coupler of the prior art is replaced with a hybrid coupling operational amplifier 124.

The source of echo in the interface circuitry of the present invention is the two-wire to four-wire load balancing circuit including operational amplifier 124. As the impedance of the two-wire load, i.e., the telephone, varies from the impedance the balancing circuit expects to see, a larger amount of the synthesizer 249 output signal at node 214 is reflected into the analog input to the analyzer 41 through the spectrum shaping amplifier 32.

Because of the processing delay inherent in digital voice transmission, especially employing data compression and expansion, even small amounts of echo are annoying to the talker. The echo suppression employed in the present invention effectively eliminates this residual echo, and the flow chart for the software implementation is shown in FIG. 5.

Echo suppression is carried out by a combination of the use of the balancing hybrid operational amplifier 124 and software analysis of the near talker RMS in the analyzer 41, ARMS, and the far talker RMS in the synthesizer, 249, SRMS. This determines whether the user at the respective end of the transmission link is talking or listening during each frame and accordingly attenuates ARMS or SRMS. This process begins in software, e.g., in the analyzer 41, at START 350. In decision block 352 the ARMS is compared to see if it is greater than the most recent peak ARMS, i.e., ARMSP. If it is then the ARMSP value is set to the present ARMS value in block 354. Since decisions are made each frame regarding which signal to suppress in order to suppress echo effectively during pauses and at the end of talking, two delay functions are employed. The first is to hold ARMSP at its most recent value for a selected time. This is done in block 354 by setting the count CACNT in an accumulator in the analyzer 41 to DCNT, equal to 16, and which CACNT is decremented by 1 each frame for a total of 16 frames, as long as ARMS is less than or equal to ARMSP.

In decision block 356 SRMS is compared to SRMSP, the most recent peak SRMS. If it is greater, then SRMSP is set to equal the present SRMS in block 358. Also for the reasons explained above a delay counter accumulator count CSCNT in an accumulator in the analyzer 41 is set to equal DCNT and is decremented by 1 once each frame for 16 frames as long as SRMS is less than or equal to SRMSP.

In decision block 360 CACNT is compared to 0 and if less than or equal to 0 ARMSP is set at the present value of ARMS in block 362. This same function is performed in decision block 364 and block 366 with respect to CSCNT and SRMSP equal to the present SRMS.

A decision whether to attenuate SRMS is made in decision block 368 by comparing ARMSP to a value THRONE set at two-fifths scale, and also comparing to see if ARMSP is greater than or equal to SRMSP plus a fraction of the hybrid loss HLOSS. The first condition makes certain that a reasonable volume of speech is being transmitted/received and the second condition makes certain that the received energy is smaller, even when a correction is made for hybrid impedance mismatch. If these conditions are met an attenuating counter for the synthesizer CNTA is set in block 370 at MAXCNT, e.g., 16 and an attenuating counter for the analyzer CNTS is set to zero. This results in SRMS attenuation at, e.g., 12 db each frame for as long as CNTA is greater than 0.

Similarly if SRMSP is greater than THRONE and SRMSP is greater than ARMSP+HLOSS a decision is made in decision block 372 which results in block 374 in the setting of an attenuating counter CNTS for the analyzer at MAXCNT and the attenuating counter CNTA for the synthesizer at 0, to attenuate ARMS for a selected number of frames as CNTS decrements each frame from MAXCNT which may be, e.g., 16.

Moving on to FIG. 5A it is seen that ARMSP and SRMSP are then compared in decision blocks 376 and 380, respectively, with a second threshold value THRTWO, equal to four-fifths scale. If either is greater than this value then, respectively, the far talker or near talker is interrupting and attenuation must be accordingly removed. This is done in blocks 378 and 382 by setting, respectively, CNTS or CNTA equal to 0.

Decision blocks 384 and 386 control the actual attenuation so long as, respectively, CNTA is greater than 0 or CNTS is greater than 0. In the former event SRMS is set in block 386 to equal SRMS minus, e.g., 12 db and in the latter event ARMS is set in block 390 to equal ARMS minus, e.g., 12 db.

The decrementing function is performed in block 392 by setting CNTA, CNTS, CACNT and CSCNT each equal to their respective values minus 1. The program then returns to START from RETURN 394, to begin processing the data for the next frame.

Thus it can be seen that the software at each end of the transmission link functions to attenuate the proper value, either SRMS or ARMS depending on whether the near talker or far talker, as perceived by each respective end of the transmission link, is the actual talker, the other signal, either SRMS or ARMS, being thereby determined to be echo and being attenuated to suppress the echo.

Echo suppression also occurs in the four-wire interface section of the two-wire to four-wire converter. The voltage at node 112, V.sub.112 is given by equation 1. ##EQU1## where: V.sub.T =telephone MIC output voltage

Z.sub.T =telephone impedance

V.sub.S =voltage at the output of operational amplifier 204 (the synthesizer output).

Since the operational amplifier 124 is operating with negative feedback, its negative input will track the positive input. A second node equation at the output of the amplifier 124 yields: ##EQU2## where: V.sub.0 is the voltage at the output of the operational amplifier 124 (the analyzer input)

R.sub.f is the equivalent resistance of the feedback resistance inductance network of the operation amplifier 124.

Substituting for V.sub.112 from equation 1 yields: ##EQU3##

For proper operation there should be no V.sub.S signal component in V.sub.0. For this to occur, the first term on the right side of equation 3 must equal zero. That term equals zero when: ##EQU4##

In the design of the present invention, this requirement is satisfied using R.sub.f =Z.sub.T and R.sub.128 =R.sub.126. Substituting these values into equation 3 yields V.sub.0 as a function of the microphone signal:

In order to empirically match Z.sub.T, measurements were taken of the telephone impedance over the range of about 100 to 4000 Hz at a bias current of 16 ma. From this data a matching network according to the present invention was synthesized. Since telephone impedances vary from unit to unit, two adjustments are included in the network by way of the variable resistors 132 and 134 and 198 in order to improve the nominal matching.

The performance of the two-wire to four-wire converter 12 is more critical in the present invention than in a normal telephone channel since the processing delay inherent in the use of digitized voice will produce sufficient delay in the echo path of the converter 12 (synthesizer out to analyzer in) to disturb the normal cadence of the talker.

Once adjusted, the circuit yields approximately 40 dB of loss in the echo path across the 100 to 4000 Hz spectrum. To null the circuit a signal (1000 Hz, sinusoidal, 0.814 VRMS) is inserted at the center post of suitcase strap 56 (with the strap removed). Variable resistor 198 is adjusted (Rx Gain Pot) to produce 1.1.+-.0.2 VRMS at the output of amplifier 204. This adjusts the receive gain and provides a reference signal for the two-wire to four-wire balance adjustment. The balance adjustment must be made with the telephone connected to the RING and TIP lines and with OFF HOOK activated. Monitoring the output of the amplifier 152, variable resistor 132 and 134 are adjusted to null the signal at that point. The signal level at that point should be at least 35 dB lower than at the output of amplifier 204.

The principal features of the operation of the present invention will be now described with reference to FIGS. 2 and 2A. Bias current for the telephone is produced using a series resistor network 116 and 114 to +12 volts with a decoupling capacitor 120 to ground.

The ring driver 15 consists of a totem pole driver circuit which includes transistors 86, 88 and 90 and associated discrete components. The circuit uses the TTL level signals Q10NH and Q20NH to alternately switch the TIP line between 180 V and ground. The design of the TTL drive signals includes a "dead time" between state changes in which both transistor 88 and transistor 86 are off.

Diodes 108 and 106 limit the spiking which occurs when the current in the bell coil of the telephone (not shown) tries to change rapidly. Diode 110 isolates the ringing voltage from the two-wire to four-wire converter 12. When the ring driver 15 is active the voltage at node 112 will swing from 0 to +12 V, at which point diode 110 turns off, while the cathode side of diode 110 continues toward 180 V.

When the ring driver 15 is inactive both halves of the totem pole driver circuit are off, thereby presenting a very high impedance to the TIP line and having no effect on the two-wire to four-wire converter 12 balance.

The hookswitch status detection is accomplished by the amplifier 66 and its associated discrete components. Resistor 70 is a DC current sense resistor. The voltage across resistor 70 is low pass filtered at 1 Hz by resistor 72 and capacitor 74 and compared (via amplifier 66) to a fixed threshold at the junction of resistors 78 and 80. In operation there are four combinations of ring state and hookswitch status which the status detection circuitry must recognize. Each combination is described below.

1. Ring Active, ON HOOK--for this state (which occurs when a call is received) the TIP and RING leads are AC coupled through the telephone bell circuit. The voltage across the sense resistor 70 is therefore an AC signal (f approximately 20 Hz). The 1 Hz LPF (resistor 72 and capacitor 74) prevents excursions of this signal from exceeding the threshold and the ONHOOK status does not change.

2. Ring Active, OFF HOOK--in this state (which occurs when a call is answered) the TIP and RING lines are DC coupled through the telephone. The LPF capacitor 82 charges to the average value of the ring signal, which exceeds the preselected threshold and generates the OFFHOOK status, which should then be sensed by software to turn off the ring signal.

3. Ring Inactive ON HOOK--in this state (which occurs when the telephone is no longer being used) the TIP and RING lines are again AC coupled. No bias current can flow through the TIP and RING lines and the voltage across resistor 70 drops below the threshold (to 0 V) producing the ON HOOK indication.

4. Ring Inactive, OFF HOOK--in this state (which occurs when a call is initiated or in-progress) the TIP and RING lines are DC coupled. Bias current flows through resistor 70 producing a voltage approximately twice the threshold voltage at the LPF capacitor 82 output which produces the OFF HOOK status.

The spectrum shaping amplifier 32 provides any analog pre/de-emphasis which may be desirable for the transmit audio. It also sums the transmit analog signals from both the two-wire and four-wire inputs. The circuit is AC coupled, via capacitors 146 and 140 to, respectively, the interfaces 12 and 18 to remove the DC voltage resulting from the telephone bias currents. The gains of the two-wire and four-wire transmit paths can be set independently using resistor 148 and resistor 142 respectively. The nominal gain of the interfaces are 14.3 dB for the two-wire path in interface 12 and 3 dB for the four-wire path in interface 18. The gains are set so that the signal peaks between capacitor 153 and switch 34 reach approximately 3 volts when speaking at a normal level. The output of the spectrum shaping amplifier 152 is AC coupled through capacitor 153 to the AGC circuit 36 to prevent a DC offset voltage from causing unnecessary transitions in the AGC 36 output signal as the gain is changed.

The AGC circuit 36 and input filter 46 portion of the filter 44 are described together in further detail here, as shown in FIG. 6, because a ladder network contained in the AGC 36 circuit and an input operational amplifier 375 contained in the filter 44 are interconnected to form a composite gain block. The equivalent circuit for the AGC 36 and a portion of the input filter 46 circuit within the filter 44 is shown in FIG. 6.

Within the AGC circuit 36 is a feedback resistor 376 which, together with feedback resistor 160 acts as a negative feedback loop for operational amplifier 375. The AGC circuit 36 and the operational amplifier 375 also have an input resistor 378.

The gain of this AGC 36 and filter 44 circuit from E.sub.IN at switch 34 to E.sub.O at VF.sub.x at the output of the operational amplifier 375 in the filter circuit 44 VF.sub.x 0 is ##EQU5## where D is the digital code loaded into the AGC 36 (0.ltoreq.D.ltoreq.255) on pins PDI07-00 and resistors 376 and 378 are nominally 10 Kohms. A digital-to-analog converter 380 in the AGC 36 circuit is connected to a precision reference voltage V.sub.ref and provides a current output representative of the value D/256-1 where D is the digital input to the AGC 36 on PDI07-00 from the analyzer 41.

In operation the AGC 36 and input filter 46 circuits cover a gain range of 30 dB (+14 dB to -16 dB), in 2 dB steps, although the hardware is capable of greater range and finer resolution. Table 1 lists the values of D stored in the memory in the analyzer 41 corresponding to respective four-bit counts (0-15 decimal) from the AGC controller accumulator GCNT in the analyzer 41, along with the corresponding gains based on the component values used in the AGC 36 and the input filter 46 circuits.

The remainder of the input filter 46 integrated circuit actually performs the low pass filter function in filter 380 and introduces +3 dB gain in the passband. The input filter 46 output on pin 16 (VF.sub.x 0) of filter 44 is therefore 3 dB higher than the values shown in Table 1.

The AGC circuit 36 bypass strap 34 permits the AGC 36 to be bypassed for specific applications or for test purposes. When the strap 34 is in the bypass position, the gain from the strap to the input (transmit) filter 46 portion of filter 44 output VF.sub.x 0 is +3.36 dB, which is close to mid-range AGC 36 setting.

The A/D-D/A function is performed using the INTEL 2911A A-Law CODEC 50. The CODEC 50 and an INTEL 2912 filter 44 form a functional block which is interconnected as is well known in the art.

A suitcase strap is provided on the VFRI input of the output (receive) filter 48 portion of the filter 44 at 56 to allow the audio input to be looped back to the output for test purposes.

The serial output of the A/D converter 50 which is at 64,000 bps and represents the digitized voice is converted to 8 bit parallel word in serial-to-parallel converter 58. The TS.sub.x output of the CODEC 50 is used for several functions in the A/D-D/A operation. During its active time the TS.sub.x output enables the shift clocks on serial-to-parallel converter 58 and parallel-to-serial converter 60 so that the CODEC 50 can output its A/D word. It also enables inputing a new D/A word from the parallel-to-serial converter 60, which is the synthesized digital voice from the synthesizer 249 in the analyzer 41 at 64,000 bps. The trailing edge of TS.sub.x (data transfer is complete) is used to generate an interrupt request for the A/D and D/A portions of the A/D/A converter 50 (ADINT) in flip-flop 88. The actual A/D and D/A conversions are started when the FS(X,R) signal is generated for the CODEC A/D/A converter 50. FS signal is generated using retimed SRCLK from flip-flop 190 on pin Q . The timing sequence for the CODEC 50 is shown in FIG. 7. When an ADINT pulse is generated, e.g., every eight bits in time the data (eight bits) in the serial-to-parallel converter 58 is loaded to the processor 41 and the data (eight bits) in the parallel-to-serial converter 60 is loaded to the A/D/A converter 50.

The Rx low pass filter output VFRO drives the inverting amplifier 204. The gain of this amplifier 204 is adjustable via variable resistor 198 to set the receive signal level. The output of amplifier 204 drives both the two-wire and four-wire audio output circuits, which drive the speaker in the telephone handset (not shown).

It will be seen that the present invention provides for echo suppression at both the talker end and the receiver end, in accordance with detection, at each end of the transmission link, of which signal (talk or listen) is stronger. This dual echo suppression is incorporated along with a hybrid operational amplifier echo suppression circuit at each end, which particularly is suited for echo suppression in a transmission and receiver system employing digitized voice data and especially compressed digitized voice data.

The foregoing description of the present invention has been directed to a particular embodiment of the invention in accordance with the requirements of the patent statutes and for purposes of illustrating and explaining the invention. It will be apparent, however, to those skilled in this art that many modifications and changes in both the method and apparatus of the present invention may be made without departing from the scope and spirit of the present invention. For example, the analyzer/synthesizer can be microprocessor implemented or implemented by, e.g., a minicomputer or by suitable hard-wired large-scale integrated circuitry dedicated to performance of the functions described herein. The particular values for the logic decisions deseribed herein may be varied as desired from the preferred embodiment described herein. Further, the echo suppression technique described herein is not limited to transmission and receipt of compressed digital voice, and can be useful in any system which transmits and receives digital voice data, especially wherein processing delays heighten the echo problem. It will be further apparent that the invention may also be utilized, with suitable modifications within the state of the art which will be apparent to those skilled in the art. It is the applicants' intention in the following claims to cover all such equivalent modifications and variations as fall within the true scope and spirit of the invention.