Static-Type Semiconductor Memory Device

(1) Field of the Invention

The present invention relates to a semiconductor memory device, more particularly, to a static-type semiconductor memory device in which the danger of destruction of the stored data due to alpha particles or power supply noise is reduced.

(2) Description of the Prior Art

Generally, a static-type semiconductor memory device comprises a memory cell array consisting of a plurality of memory cells, a peripheral circuit for the memory cell array, and a holding-current supplying circuit. The static-type memory cell comprises cross-coupled transistors which constitute a flip-flop. The data storing capacity of the memory cell is expressed by 1/2CV, where C is the amount of the stored charges, and V is the base-base voltage when the above-mentioned transistors, are bipolar transistors or the gate-gate voltage when the above-mentioned transistors are metal-insulator semiconductor (MIS) transistors. The data stored in each memory cell can theoretically be held by continuously supplying a holding current to each memory cell.

However, it is known that, when a semiconductor memory device is assembled into a package, the data stored in the semiconductor memory device are often destroyed due to alpha particles radiated from the package. The stored data may also be destroyed due to power supply noise, i.e., fluctuations of the power supply voltage. Therefore, countermeasures for alpha particles and power supply noise are required.

To obtain a semiconductor memory device resistant to alpha particles and power supply noise, it may be considered to increase the data storing capacity of each memory cell by increasing the above-mentioned C and V. Increase of the C and V of all the memory cells, however, would reduce the switching speed, resulting in an undesirably slower writing speed or reading speed. It may also be considered to increase the data storing capacity by increasing the holding current. Conventionally, however, the same holding currents are supplied to both unselected-state memory IC's and selected-state memory IC's. Therefore, the unselected-state memory cells and the selected-state memory cells have the same C and V. If the holding currents are increased in the conventional device, the C and V for all the memory cells are also increased, resulting in the reduced writing or reading speed.

An object of the present invention is to provide a static-type semiconductor memory device in which the danger of destruction of the stored data by alpha particles or power supply noise is reduced.

Another object of the present invention is to provide a static-type semiconductor memory device in which the C and V in each memory cell in unselected memory IC's are made greater than those in each memory cell in selected memory IC's.

Still another object of the present invention is to provide a static-type semiconductor memory device in which the holding current flowing through the memory cells in selected-state memory IC's is greater than the holding current flowing through the memory cells in unselected-state memory IC's.

To attain the above object, there is provided, according to the present invention, a static-type semiconductor memory device comprising a plurality of memory blocks arranged in a row direction and in a column direction to form a matrix. Any one row of the memory blocks is operatively selected to carry out a reading or writing operation in the selected memory blocks. Each of the memory blocks comprises a memory cell array including memory cells, and a peripheral circuit associated with the memory cell array. The peripheral circuit comprises a holding-current supplying circuit for supplying, to the memory blocks, a current for holding data stored in the memory cells, a first current-source circuit for supplying currents through bit lines to the memory cells, a sense amplifier circuit for detecting potential differences between the bit lines, and a second current-source circuit for supplying currents to the sense amplifier circuit. According to the present invention, each of the memory blocks further comprises a holding-current controlling circuit for controlling the holding-current supplying circuit such that the holding current supplied to an unselected-state memory block is greater than the holding current supplied to a selected-state memory block. The current supplied to the first current-source circuit, the sense amplifier, and the second current-source circuit, associated with an unselected-state memory block is smaller than the current supplied to the first current-source circuit, the sense amplifier, and the second current-source circuit, associated with a selected-state memory block.

According to one aspect of the present invention, the holding-current controlling circuit comprises a differential amplifier for determining whether the memory block is selected or not. The differential amplifier operatively outputs a holding-current determining signal. The holding-current determining signal has a first potential when the memory block is selected and a second potential when the memory block is unselected. The holding-current determining signal is operatively applied to the holding-current supplying circuit so as to activate the holding-current supplying circuit in response to only the first potential.

According to a further aspect of the invention, the differential amplifier operatively outputs a current-source current determining signal having the first potential or the second potential when the holding-current determining signal has the second potential or the first potential, respectively. The current-source current determining signal is applied to the first current source and the second current source so as to activate the current sources in response to the potential of the current-source current determining signal.

According to a still further aspect of the invention, each of the memory cells is connected between a word line and a hold line. The word line and the hold line are extended in the row direction. The holding current is conducted from the word line through the memory cell to the hold line. Each of the memory cells is connected between a pair of bit lines extending in the column direction. The holding-current supplying circuit comprises a plurality of first NPN transistors each having a base adapted to receive the holding-current determining signal from the differential amplifier, a collector connected to the hold line, and an emitter connected to a first power supply.

According to a still further aspect of the invention, the first current source and the second current source comprise second NPN transistors each having a base adapted to receive the current-source current determining signal.

According to a still further aspect of the invention, the differential amplifier comprises a third NPN transistor having a base adapted to receive a reference signal, a collector connected through a resistor to a second power supply, and an emitter connected to a current source; and a fourth NPN transistor having a base adapted to receive a block selecting signal, a collector connected through a resistor to the second power supply, and an emitter connected to the current source. The collector of the third NPN transistor is adapted to provide the holding-current determining signal. The collector of the fourth NPN transistor is adapted to provide the current-source current determining signal.

Each of the memory blocks may be one memory chip. Alternatively, a predetermined number of the memory blocks may comprise one memory chip.

The above objects and advantages as well as other features of the present invention will be apparent from the following description of the preferred embodiments with reference to the accompanying drawings.

FIG. 1 is a general block diagram of a semiconductor memory device according to an embodiment of the present invention;

FIG. 2 is a circuit diagram of one of the memory IC chips in the block diagram of FIG. 1, the memory IC chip including a memory cell array, a peripheral circuit, and a holding-current controlling circuit; and

FIG. 3 is an equivalent circuit diagram of an example of a well-known bipolar memory cell.

An embodiment of the present invention will now be described with reference to the drawings.

FIG. 1 is a general block diagram of an embodiment of the present invention. In the figure, MIC.sub.11 through MIC.sub.mn are memory IC chips; MCA.sub.11 through MCA.sub.mn are memory cell arrays; PH.sub.11 through PH.sub.mn are peripheral circuits of the memory cell arrays; HC.sub.11 through HC.sub.mn are holding-current controlling circuits; CS.sub.11 through CS.sub.mn are chip-selecting terminals; and CS.sub.1 through CS.sub.m are chip-selecting signals. Each static-type semiconductor memory IC chip comprises a memory cell array, a peripheral circuit, and a holding-current controlling circuit for controlling the holding current supplied to the memory cell array and the current supplied to the peripheral circuit. That is, when a memory IC chip is in a selected state, i.e., when the chip-selecting signal applied to the chip-selecting terminal is at a low level, the ratio between the holding current supplied to the memory cells in the chip and the current supplied to the peripheral circuit in the chip is the same as the ratio in conventional devices. When the memory IC chip is in an unselected state, i.e., when the chip-selecting signal is at a high level, the holding current supplied to the memory cells is increased, and the current supplied to the peripheral circuit is decreased. The total power consumption in all of the memory IC chips is thus either constant or decreased. Thus, almost no data stored in the unselected-state memory cells are destroyed because of the increased holding currents.

The operation of the circuit of FIG. 1 will now be described. When the chip-selecting signal CS.sub.1 becomes the low level (L) so that the memory IC chips MIC.sub.11, ---, and MIC.sub.1n in the first row are turned to the selected states, the holding current flowing through the memory cell arrays MCA.sub.11, ---, and MCA.sub.1n and the current flowing through the peripheral circuits in the first row are the same as the holding current in conventional devices. However, the holding current flowing through the memory cell arrays MCA.sub.21, ---, MCA.sub.2n, ---, MCA.sub.mn in and after the unselected-state second row, becomes greater than the holding current in the selected state. Also, the current flowing through the peripheral circuits PH.sub.21, ---, PH.sub.2n, ---, and PH.sub.mn in and after the second row becomes smaller than the current flowing through the selected-state peripheral circuits, as described in detail later. Since no writing or reading operation is carried out in the unselected-state memory IC chips, the operating speed is not reduced even when the holding current supplied to the unselected memory IC chips is increased. Also, since the peripheral circuit does not operate in the unselected state, the current supplied to the peripheral circuit in the unselected memory IC chip can be decreased without any trouble.

FIG. 2 is a circuit diagram of one of the memory IC chips MIC.sub.11 in the block diagram of FIG. 1. The memory IC chip MIC.sub.11 includes the memory cell array MCA.sub.11, its peripheral circuit PH.sub.11, and the holding-current controlling circuit HC.sub.11. In FIG. 2, the memory cell array MCA.sub.11 and the peripheral circuit PH.sub.11 have well known constructions. In brief, the memory cell array MCA.sub.11 has bipolar memory cells MC.sub.11, ---, MC.sub.1n, --- arranged in a matrix. The peripheral circuit PH.sub.11 includes a word-line driving transistor T.sub.1 and a holding-current supplying transistor T.sub.2 for each row of the memory cell array, bit-line level detecting transistors T.sub.3 and T.sub.4, transistors T.sub.5 and T.sub.6 for supplying currents to the bit lines BL and BL, and a well-known sense amplifier SA, for each column of the memory cell array. The detected levels of the bit lines BL and BL are amplified to obtain the read-out data at output terminal D.sub.0. Transistors T.sub.7 through T.sub.12 in the peripheral circuit PH.sub.11 are transistors for a current source for the sense amplifier. For the sake of simplicity, the other sense amplifiers for the memory cells MC.sub.11 through MC.sub.1n-1 and their peripheral circuits are eliminated in the drawing.

The holding-current controlling circuit HC.sub.11, provided according to the present invention, comprises a pair of NPN transistors Q .sub.1 and Q.sub.2 Reference voltage Ref is applied to the base of the transistor Q.sub.1. A chip-selecting signal CS.sub.1 is applied to the base of the transistor Q.sub.2. The emitters of the transistors Q.sub.1 and Q.sub.2 are commonly connected to a current source I.sub.0. The collectors of the transistors Q.sub.1 and Q.sub.2 are respectively connected via resistors R.sub.1 and R.sub.2 to one end of the resistor R.sub.3, the other end of the resistor R.sub.3 being connected to a power supply line V.sub.CC. The collectors of the transistors Q.sub.1 and Q.sub.2 are also connected to the bases of NPN transistors Q.sub.3 and Q.sub.4, respectively. The collectors of the transistors Q.sub.3 and Q.sub.4 are connected to the power supply line V.sub.CC. The emitters of the transistors Q.sub.3 and Q.sub.4 are respectively connected via resistors R.sub.4 and R.sub.5 to the collectors of NPN transistors Q.sub.5 and Q.sub.6. The emitters of the transistors Q.sub.5 and Q.sub.6 are connected to the ground supply line V.sub.EE. The bases of the transistors Q.sub.5 and Q.sub.6 are respectively clamped by diodes D.sub.1 and D.sub.2. That is, the anodes of the diodes D.sub.1 and D.sub.2 are respectively connected to the bases of the transistors Q.sub.5 and Q.sub.6, and the cathodes of the diodes D.sub.1 and D.sub.2 are connected to the ground supply line V.sub.EE. Also, the anodes of the diodes D.sub.1 and D.sub.2 are respectively connected via resistors R.sub.6 and R.sub.7 to the cathodes of diodes D.sub.3 and D.sub.4. The anodes of the diodes D.sub.3 and D.sub.4 are connected to the power supply line V.sub.CC. The collectors of the transistors Q.sub.5 and Q.sub.6 are also connected to the bases of transistors Q.sub.7 and Q.sub.8, respectively. The collectors of the transistors Q.sub.7 and Q.sub.8 are connected to the power supply line V.sub.CC, and the emitters of the transistors Q.sub.7 and Q.sub.8 are connected via resistors R.sub.8 and R.sub.9, respectively, to the ground supply line V.sub.EE. The emitter .circle.A of the transistor Q.sub.7 is also connected to the base of the holding-current supplying transistor T.sub.2 in the memory cell array MCA.sub.11. The emitter .circle.B of the transistor Q.sub.8 is connected to the bases of the transistors T.sub.7 through T.sub.12 and to the bases of the current-source transistors such as the transistors T.sub.5 and T.sub.6 for the bit lines.

The operation of the circuit of FIG. 2 will now be explained.

Normally, when the potential of the chip-selecting signal CS.sub.1 is at the H level, which is higher than the reference voltage Ref, the memory IC chips MIC.sub.11, ---, and MIC.sub.1n in the first row as shown in FIG. 1 are in the unselected state. In this state, with respect to the memory IC chip MIC.sub.11, the transistor Q.sub.1 is off, and the transistor Q.sub.2 is on. Accordingly, the base level of the transistor Q.sub.3 is at the H level, and the base level of the transistor Q.sub.4 is at the L level. Thus, the collector level of the transistor Q.sub.5 or the base level of the transistor Q.sub.7 becomes the H level, and the collector level of the transistor Q.sub.6 or the base level of the transistor Q.sub.8 becomes the L level. Thus, the potential at the emitter .circle.A of the transistor Q.sub.7 becomes the H level, and the potential at the emitter .circle.B of the transistor Q.sub.8 becomes the L level. Accordingly, to the base of the holding-current supplying transistor T.sub.2 in the memory cell array MCA.sub.11, the H level voltage is applied to turn on the transistor T.sub.2 so that a large holding current I.sub.H flows from the word line W through the memory cells MC.sub.11 through MC.sub.1n and through the transistor T.sub.2 to the ground supply line V.sub.EE. On the other hand, since the L level potential is applied to the bases of the current source transistors T.sub.7 through T.sub.12 and to the bases of the bit-line current source transistors T.sub.5, T.sub.6, ---, the transistors T.sub.5 through T.sub.12 are turned off so that the current flowing through the peripheral circuit PH.sub.11 is decreased. By setting the holding current for the unselected-state memory cells and the current for the peripheral circuit to the appropriate values so that the increase in the power consumption due to the increase of the holding current is compensated for or decreased by the decrease in the power consumption due to the decreased current flowing through the peripheral circuit, the total power consumption in the memory IC chip MIC.sub.11 is constant regardless of its selected state or unselected state, or may be decreased in comparison with its selected state.

It is apparent that, when the chip-selecting signal CS.sub.1 is lower than the reference voltage Ref, an inverse of the above-described operation is carried out. That is, the holding current for the selected-state memory cells is decreased, and the current for the peripheral circuit is increased.

The reason for the increased data-holding capacity of a memory cell due to the increased holding current I.sub.H will now be described with reference to FIG. 3. FIG. 3 is an equivalent circuit diagram of an example of a well-known bipolar memory cell. In FIG. 3, the memory cell MC comprises, as is well known, a pair of multi-emitter NPN transistors Q.sub.a and Q.sub.b, a load resistor R.sub.a and a clamping diode D.sub.a connected in parallel between the collector of the transistor Q.sub.a and the word line W.sub.+, and a load resistor R.sub.b and a clamping diode D.sub.b connected in parallel between the the collector of the transistor Q.sub.b and the word line W.sub.+. The first emitters E.sub.a1 and E.sub.b1 of the transistors Q.sub.a and Q.sub.b are connected to the bit lines BL and BL, respectively. The emitters E.sub.a1 and E.sub.b1 are referred to as detecting emitters. The second emitters E.sub.a2 and E.sub.b2 are connected to a hold line H. The emitters E.sub.a2 and E.sub.b2 are referred to as holding emitters. As long as the voltage between both ends of the resistor R.sub.a or R.sub.b is smaller than the clamping voltage of the diode D.sub.a or D.sub.b, a current flows through the resistor R.sub.a or R.sub.b. When the transistor Q.sub.a is in an on state and the transistor Q.sub.b is in an off state, a current nearly equal to the holding current I.sub.H flows through the resistor R.sub.a, while almost no current flows through the resistor R.sub.b. Therefore, the base potential of the transistor Q.sub.a is nearly equal to the potential V.sub.W of the word line W, and the base potential of the transistor Q.sub.b is V.sub.W -I.sub.H .multidot.R (where R is the resistance of the resistor R.sub.a). Accordingly, the potential difference V between the bases of the transistors Q.sub.a and Q.sub.b can be expressed as follows: V =V.sub.W -(V.sub.W -I.sub.H .multidot.R) =I.sub.H .multidot.R. The greater the holding current I.sub.H, the greater the potential difference V between the bases. Since the data holding capacity can be expressed by 1/2CV, as described before, the data holding capacity of each memory cell in the unselected memory IC chips is increased by increasing the holding current I.sub.H.

It should be noted that a PNPN-type memory cell is also known. In place of the load resistors, the PNPN-type type memory cell uses diodes as the loads. Each of the diodes is formed between the emitter and the base of a PNP transistor. In the PNPN-type memory cell, the voltage drop between the ends of the load is not increased even when the holding current is increased. Accordingly, the potential difference between the bases of the transistors which comprise the flip-flop is not increased. However, in this case, when the holding current I.sub.H is increased, the depletion layer of the load PNP transistor is narrowed due to the increase in the forward-direction bias current. Therefore, the capacitance C is increased, and, thus, the data holding capacity 1/2CV is also increased.

The above explanation has been made with reference to examples using bipolar transistors in memory cells. However, it will be apparent to those skilled in the art that the present invention is also applicable to a static-type semiconductor memory device using MIS transistors. Also, the above explanation described the holding current as being increased when the memory IC is unselected. Alternatively, the memory cell array in the memory IC may be separated into several blocks, and the holding current in the unselected-block memory cells may be increased and the supplying current to its peripheral circuit may be decreased.

From the foregoing description, it will be apparent that, according to the present invention, by making the holding current flowing through unselected-state memory IC chips greater than that flowing through selected-state IC chips, the data holding capacity of the memory cells in unselected-state memory IC chips, the number of which is usually large, can be increased. Accordingly, the danger of destruction of the stored data in the memory cells due to alpha rays or power-supply noise fluctuation is reduced.