Data Processing System Having an Address Translation Unit Shared by a CPU and a Channel Unit

This invention relates to a data processing system comprising a main memory, a central processing unit, and a channel unit, which are all connected to a data bus and, in particular, to a data processing system for use in accessing the main memory from each of the central processing unit and the channel unit.

A virtual or logical address method is often adopted in a data processing system when a main memory is used in common to a plurality of programs and a memory capacity of the main memory is smaller than a capacity necessary for all of the programs. With the virtual address method, a virtual address should be converted or translated into a real address specifying each of physical addresses of the main memory when the main memory is accessed by each of a central processing unit and a channel unit.

It is preferable that such address translation is made as fast as possible. In particular, the address translation should proceed faster on an access from the central processing unit than on an access from the channel unit.

A conventional data processing system is provided with an address translating table memorized in a main memory to translate each virtual address into a real address. With the conventional system, address translation is possible without an increase of superfluous hardware. However, the main memory should be accessed to look up the address translating table each time when the address translation becomes necessary. Therefore, overhead time extremely becomes long for the address translation. This means that the address translating table can not be substantially utilized by the central processing unit because of a long overhead time. At any rate, the conventional data processing system inevitably brings about degradation of system performance.

In U.S. Pat. No. 3,902,163, issued to G. M. Amdahl et al and assigned to Amdahl Corporation, a data processing system is described which comprises a storage control section coupled to a central processing unit. The storage control section comprises a primary buffer memory for storing an address translation table transferred from a main memory. Such a buffer memory may generally be called a Table Lookaside Buffer (usually abbreviated to TLB in the art) and is operable at a high speed in comparison with the main memory. With the Amdahl system, address translation can rapidly be made by the use of the primary buffer memory when the central processing unit accesses the main memory. However, no suggestion is offered as to address translation of a logical address given from a channel unit. Therefore, such address translation slowly proceeds by accessing an address translating table stored in the main memory as mentioned before.

In order to carry out rapid address translation related to the channel unit, another buffer memory should be incorporated in the channel unit so as to store an additional address translation table which is identical with the address translation table stored in the primary buffer memory incorporated in the central processing unit. This, however, results in an increase of hardware. Inasmuch as both of the primary and the additional buffer memories must always be coincident in their contents with each other, superfluous hardware should also be added to the primary and the additional buffer memories as peripheral circuits.

It is an object of this invention to provide a data processing system wherein address translation can rapidly be carried out with an increase of hardware suppressed in comparison with the Amdahl system even when an access originates at a channel unit.

It is another object of this invention to provide a data processing system of the type described, wherein overhead time is reduced for address translation and, therefore, system performance is raised up.

A data processing system to which this invention is applicable is for use in accessing a main memory from each of a central processing unit and a channel unit through a data bus shared by the central processing and the channel units. The central processing unit comprises first access signal producing means for producing a first access signal and first request signal producing means for producing a first request signal. The channel unit comprises second access signal producing means for producing a second access signal and second request signal producing means for producing a second access signal. The main memory produces an acknowledgement signal when accessed. According to this invention, the central processing unit further comprises first delivering means responsive to a selected one of the first and the second access signals for delivering a third access signal to the main memory through the data bus, second delivering means operatively coupled to the first delivering means for delivering one of the first and the second request signals to the main memory that is selected in correspondence to the selected one of the first and the second access signal, and energizing means operatively coupled to the second delivering means and at least to the second request signal producing means and responsive to the acknowledgement signal for energizing the channel unit with the data bus assigned to the channel unit when the second request signal producing means produces the second request signal and the second delivering means delivers the second request signal as the one of the first and the second request signals.

FIG. 1 is a block diagram of a data processing system according to a preferred embodiment of this invention; and

FIG. 2 is a block diagram for use in describing a part of the data processing system illustrated in FIG. 1 in detail.

Referring to FIG. 1, a data processing system according to a preferred embodiment of this invention is for use in accessing a main memory 10 from each of a central processing unit 11 and a channel unit 12. The channel unit 12 may be called an input/output processor (IOP). A data bus 15 is laid between the main memory 10 and the central processing unit 11 and between the main memory 10 and the channel unit 12 together with an address bus 16 and a command bus 17. Each of the central processing unit 11 and the channel unit 12 is connected to the main memory 10 through the data bus 15, the address bus 16, and the command bus 17 as will presently be described. In other words, the data bus 15, the address bus 16 and the command bus 17 are shared by the central processing unit 11 and the channel unit 12. More particularly, the data bus 15 is connected through first, second, and third data lines 21, 22, and 23 to the central processing unit 11, the channel unit 12, and the main memory 10, respectively, while the address bus 16 is connected through first, second, and third address lines 26, 27, and 28 to the central processing unit 11, the channel unit 12, and the main memory 10, respectively. In addition, the command bus 17 is connected through first, second, and third command lines 31, 32, and 33 to the central processing unit 11, the channel unit 12, and the main memory 10, respectively. In the example being illustrated, the second address line 27, and the second command line 32 serve to carry out transfer operation between the channel unit 12 and input/output devices (not shown), as will become clear as the description proceeds. The transfer operation between the channel unit 12 and the input/output devices is out of the scope of this invention and will therefore not be described in detail in the instant specification.

The illustrated central processing unit 11 comprises a primary controller 35 for delivering a set of control signals C to an access circuit 36 and a request circuit 37 to put them into operation in timed relation to the control signals C. The access circuit 36 comprises a first address register 38 and a first command register 39 for holding a first address signal AD.sub.1 and a first command signal CM.sub.1, respectively, under control of the primary controller 35. Both of the first address signal AD.sub.1 and the first command signal CM.sub.1 may collectively be called a first access signal because they serve to access the main memory 10. In this connection, a combination of the first address register 38 and the first command register 39 may be referred to as a first access signal producing circuit.

It should be mentioned here that the first address signal AD.sub.1 specifies a logical address for designating a program or the like. Therefore, the first address signal AD.sub.1 should be translated or converted into a physical or real address in order to actually access the main memory 10 in a manner to be described later.

Anyway, the first address signal AD.sub.1 is supplied to an address translation circuit 45 through a first multiplexer 46 while the first command signal CM.sub.1 is given to a second multiplexer 47. The first and the second multiplexers 46 and 47 are operatively coupled to the channel unit 12, as will be described later.

The request circuit 37 is operable in timed relation to the access circuit 36 under control of the primary controller 35 and comprises a first request signal circuit 51 for producing a first request signal RQ.sub.1 in response to a preselected one of the control signals C. The first request signal circuit 51 may be a flip flop. The first request signal RQ.sub.1 is delivered to a request signal processor 52 and a response control circuit 53 both of which are put into operation in a manner to be described later.

The channel unit 12 comprises a channel controller 55 for producing a group of channel control signals CC to control various parts of the channel unit 12. A second address register 57 is controlled by the channel controller 55 and produces second address signal AD.sub.2 kept therein. The second address signal AD.sub.2 specifies a second logical address designated by the input/output device in the form of a logical or virtual address, like the first address signal AD.sub.1. A second command register 62 is controlled together with the second address register 57 and produces a second command signal CM.sub.2. The second address signal AD.sub.2 and the second command signal CM.sub.2 may collectively be called a second access signal, as mentioned in conjunction with the first address signal AD.sub.1 and the first command signal CM.sub.1.

It is to be mentioned here that each of the first and the second command signals CM.sub.1 and CM.sub.2 is representative of a species of accesses, namely, a readout access or a write-in access.

The illustrated channel unit 12 further comprises a main memory access circuit 64 put into operation by the channel controller 55. The main memory access circuit 64 is connected direct to the main memory 10 through an access request signal line 66, an access acknowledgement signal line 67, and an indication signal line 68, like in a conventional data processing system. The indication signal line 68 serves to indicate, to the channel unit 12, either transmission or reception of data. At any rate, the access request signal line 66, the access acknowledgement signal line 67, and the indication signal line 68 are used together with the second address line 27 and the second command line 32 only when the main memory 10 is directly accessed by the channel unit 12, as will become clear as the description proceeds.

The main memory access circuit 64 is specified by a second request signal circuit 72 which may be a flip flop, like the first request signal circuit 51 and which produces a second request signal RQ.sub.2 representative of an access request sent from the channel unit 12.

The channel unit 12 comprises first and second data registers 76 and 77 coupled to the data bus 15 through the second data line 22. The first and the second data registers 76 and 77 are operable under the control of the channel controller 55. Specifically, the first and the second data registers 76 and 77 are enabled when the readout and the write-in accesses are specified by the second command signal CM.sub.2, respectively, on production of the second request signal RQ.sub.2. Thus, the first and the second data registers 76 and 77 are operatively coupled to the main memory access circuit 64 and the second command register 62.

The second data line 22, the second address line 27, and the second command line 32 are coupled to a data transfer control circuit 81 for controlling the transfer operation between the input/output device and the main memory 10. Such transfer operation will not be described any longer.

It should be noted here that the second address signal AD.sub.2, the second command signal CM.sub.2, and the second request signal RQ.sub.2 are not sent directly to the main memory 10 but sent to the central processing unit 11 through first, second, and third interconnection lines 86, 87, and 88 connected to the first multiplexer 46, the second multiplexer 47, and the request signal processor 52, respectively. This means that the channel unit 12 indirectly accesses the main memory 10 through the central processing unit 11 when address translation is necessary about the second address signal AD.sub.2.

Let the channel unit 12 produce a readout request so as to read a predetermined data group out of the main memory 10 by the use of a predetermined virtual or logical address specified by the second address signal AD.sub.2. In this event, the second address signal AD.sub.2 and the second command signal CM.sub.2 are kept in the second address register 57 and the second command register 62, respectively, under control of the channel controller 55. The second command signal CM.sub.2 specifies the readout request. Simultaneously, the second request signal circuit 72 is loaded with a logic "1" level as the second request signal RQ.sub.2.

The second address signal AD.sub.2 and the second command signal CM.sub.2 are sent to the first and the second multiplexers 46 and 47 and to the primary controller 35. As a consequence, the second address and the second command signals AD.sub.2 and CM.sub.2 are delivered to the request circuit 37. The second request signal RQ.sub.2 is sent from the second request signal circuit 72 to the request signal processor 52 and to the primary controller 35. Responsive to the second request signal RQ.sub.2, the primary controller 35 makes the first multiplexer 46 select the second address signal AD.sub.2. As a result, the first multiplexer 46 sends the second address signal AD.sub.2 as a selected address signal to the address translation circuit 45. The address translation circuit 45 converts or translates the selected address signal into a physical or real address corresponding to the predetermined logical address.

The primary controller 35 makes the second multiplexer 47 select the second command signal CM.sub.2. The second multiplexer 47 produces the second command signal CM.sub.2 as a selected command signal which may be called a third command signal CM.sub.3.

After the address translation is made by the address translation circuit 45, the request circuit 37 is enabled by the primary controller 35. More specifically, the request signal processor 52 checks whether or not the central processing unit 11 is accessing the main memory 10. If the central processing unit 11 is not accessing the main memory 10, the request signal processor 52 produces the second request signal RQ.sub.2 as a third request signal RQ.sub.3 on a main memory request line 91. The third request signal RQ.sub.3 is specified by the logic "1" level. On the other hand, the request signal processor 52 produces the first request signal RQ.sub.1 as the third request signal RQ.sub.3 while the central processing unit 11 is accessing the main memory 10. This means that the central processing unit 11 preferentially processes an access issued from the central processing unit 11 in comparison with an access issued from the channel unit 12.

The main memory 10 receives the third request signal RQ.sub.3 at a memory control section 93. The memory control section 93 supplies an acknowledgement signal ACK to the central processing unit 11 through an acknowledgement signal line 96 in a known manner when the main memory 10 can receive the third request signal RQ.sub.3. The acknowledgement signal ACK is specified by the logic "1" level. Reception of the acknowledgement signal ACK puts the central processing unit 11 into a state wherein each of the data, the address, and the command buses 15 to 17 can exclusively be used by the central processing unit 11.

The acknowledgement signal ACK is transferred through the response control circuit 53 to the primary controller 35. The primary controller 35 makes the address translation circuit 45 supply the third address signal AD.sub.3 to the main memory 10 through the first address line 26, the address bus 16, and the third address line 28. Likewise, the primary controller 35 makes the second multiplexer 47 supply the third command signal CM.sub.3 to the main memory 10 through the first command line 31, the command bus 17, and the third command line 33. Thus, the third access signal which is a combination of the third address signal AD.sub.3 and the third command signal CM.sub.3 is delivered from the access circuit 36 to the main memory 10. As a result, a combination of the address translation circuit 45 and the second multiplexer 47 may be referred to as a first delivery circuit for delivering the third access signal to the main memory 10. Likewise, the request signal processor 52 may be called a second delivery circuit for delivering the third request signal RQ.sub.3 to the main memory 10. It will be needless to say that the first and the second access signals are selected as the third access signal when the first and the second request signals RQ.sub.1 and RQ.sub.2 are selected as the third request signal RQ.sub.3, respectively. In other words, the selected one of the first and the second access signals is in correspondence to the selected one of the first and the second request signals RQ.sub.1 and RQ.sub.2.

The main memory 10 executes operation in accordance with the third command signal after interpretation of the third command signal CM.sub.3. Inasmuch as it is assumed before that the exemplified third command signal CM.sub.3 specifies the readout request, readout operation is carried out to read the predetermined data group out of the main memory 10 in accordance with the third address signal AD.sub.3.

When the predetermined data group is put on the third data line 23, the memory control circuit 93 produces an indication signal IND indicative of fetch or supply of the predetermined data group. The indication signal IND is sent through an indication signal line 98 to the response control circuit 53 of the central processing unit 11.

Referring to FIG. 2 together with FIG. 1, the response control circuit 53 comprises first and second storage control circuits 101 and 102 operable in response to the control signals C for storing the first and the second request signals RQ.sub.1 and RQ.sub.2, respectively. The first and the second request signals RQ.sub.1 and RQ.sub.2 are derived from the first and the second storage control circuits 101 and 102 to be sent to the primary controller 35 and channel unit 12 through first and second AND gates 106 and 107 enabled by the indication signal IND. In the example being illustrated, the second request signal RQ.sub.2 is delivered as an energizing signal EG from the second storage control circuit 102 to the channel unit 12 through the second AND gate 107 and an internal connection line 108. The energizing signal EG is specified by the logic "1" level.

Supplied with the energizing signal EG, the channel controller 55 looks up the second command signal CM.sub.2 stored in the second command register 62. Inasmuch as the second command signal CM.sub.2 is indicative of the readout request, the channel controller 55 puts the first data register 76 into an enable state. As a result, the predetermined data group which stands on the data bus 15 is fetched into the first data register 76 through the second data line 22. Thus, the energizing signal EG serves to assign the data bus 15 to the channel unit 12 when the second request signal RQ.sub.2 is produced from the channel unit 12.

In FIG. 2, when the first request signal RQ.sub.1 is read out of the first storage control circuit 101 to be sent through the first AND gate 106 to the primary controller 35, the central processing unit 11 is put into operation under control of the primary controller in a usual manner.

It is mentioned here that both of the acknowledgement and the indication signals ACK and IND are sent to the central processing unit 11 alone even when the second request signal RQ.sub.2 is selected by the request signal processor 52. Therefore, it is unnecessary to add any flag to each of the acknowledgement and the indication signals ACK and IND so as to identify each of the central processing unit 11 and the channel unit 12.

Although the description has thus far been described as regards the readout request, the illustrated system can effectively be operable when a write-in request is issued from the channel unit 12 in the form of the second command signal CM.sub.2. In this event, the energizing signal EG is also sent back to the channel unit, as is the case with the readout request. The channel controller 55 enables the second data register 77 to send a data group kept therein to the main memory 10 through the data bus 15, after looking up the second command signal CM.sub.2. Any other operations are similar to those mentioned before.

Thus, the illustrated data processing system carries out high-speed address translation of each logical address given from the channel unit 12, by the use of the address translation circuit 45. Stated otherwise, no internal address translation circuit is necessary in the channel unit 12. It is therefore possible to reduce an amount of hardware necessary for address translation. In addition, each of the data, the address, and the command buses 15 to 17 is effectively assigned to each of the central processing unit 11 and the channel unit 12 because the central processing unit 11 always monitors the access request issued from the channel unit 12 in the form of a logical address.

While this invention has thus far been described in conjunction with a preferred embodiment thereof, it will readily be possible for those skilled in the art to put this invention into practice in various other manners. For example, a real address may be sent from the channel unit 12 through the central processing unit 11 to the main memory 10. The indication signal IND may be for distinguishing between fetch and supply of a data group. In this case, either a fetch or a supply signal is delivered from the response control circuit to each of the primary and the channel controllers 35 and 55. Production of such a fetch or a supply signal is possible by the use of a decoder. With this structure, the second command register 62 may not be monitored by the channel controller 55. Further, the acknowledgement signal ACK may be monitored in the response control circuit 53 together with the first and the second request signals RQ.sub.1 and RQ.sub.2 to individually distribute the acknowledgement signal ACK to the primary and the channel controllers 35 and 55, respectively.