One-Pin Crystal Oscillator

The present invention relates to a crystal oscillator for use as a clock generator for digital integrated circuits.

Crystal oscillators were developed in the 1920's. There are a number of crystal oscillator circuits presently available for use as clock generators for digital circuits. Among the most well known are the series inverter chain, the Pierce and the Colpitts oscillators. The series inverter chain is generally considered to be inferior to the Pierce oscillator because of its tendency to either oscillate on crystal overtones, oscillate without a crystal or even fail to oscillate at all. Furthermore, the series inverter chain tends to be rather large, since it must be capable of driving the external pin capacitance. The Pierce oscillator, when properly designed, has none of these problems. Both oscillators, however, have the disadvantage that they require two package pins and several external components dedicated solely to the oscillator. Although either circuit may be adequate for general use, an oscillator requiring only one package pin and no external components is preferable.

In chip design, in order to keep the size of the package manageable, the number of external connections allowed is usually less than that desired. Often signals are multiplexed on the same pin instead of given separate pins to accommodate this need. Accordingly if one of the pins required for the oscillator could be eliminated, the chip designer would have greater design flexibility. Also with no external components, the oscillator would be immune to problems associated with their improper selection and placement.

The basic oscillator block, with an inverter 10, crystal Y.sub.1, and capacitors C.sub.A, C.sub.B, used in both the Colpitts and Pierce oscillators, is shown in FIG. 1. The capacitance C.sub.A, C.sub.B are external components which have high values on the order of 30 pF. This circuit has none of the problems of the series inverter chain. At resonance, the impedance of the crystal Y.sub.1 appears inductive, giving the necessary zero degrees loop phase shift for oscillations to occur. Parasitic elements along cannot have the same effect; therefore oscillations without the crystal are impossible. With only one stage of gain and a reactive feedback network which has low gain at all frequencies except the frequency of oscillation, the basic oscillator block does not have enough loop gain at the crystal overtones to allow oscillations at those frequencies. Also most important is the fact that all parasitic capacitances of the transistors, layout and external connections may be lumped into either C.sub.A, C.sub.B or the case capacitance of the crystal. Since these elements resonate together during oscillation, these capacitances are driven by the resonant current, and thus a high oscillator bias current is not necessary to drive large loads.

The basic oscillator block can be implemented as follows. By grounding node 3 and biasing node 2 with a current source, the Pierce oscillator is formed. Note that two pins (at nodes 1 and 2) are required to connect the crystal to the integrated circuit. Alternately, node 1 may be grounded and node 2 biased with a current source forming the Colpitts oscillator. In this configuration, the crystal Y.sub.1 is grounded on one side, and therefore only one pin of the integrated circuit need be dedicated to the oscillator and connected to node 2, as ground of the oscillator can be connected to the ground of the package. Unfortunately, in integrated form the Colpitts oscillator is difficult to bias.

The present invention is directed to overcoming the above disadvantages.

In summary, the present invention provides for the grounding of node 2 of the basic oscillator block of FIG. 1 and the biasing of node 3 with a current source to form a one-pin oscillator.

The oscillator circuit of the invention comprises a crystal, a first transistor forming one amplifier of the circuit and a second transistor interconnected in series with the first transistor forming a current source of the circuit. The oscillator circuit further includes a high impedance voltage source biasing the gate of the first transistor. The cyrstal is connected between the gate of the first transistor and a ground.

The present one-pin crystal oscillator is especially well-suited to VLSI circuits. The design features include excellent frequency stability, with no overtone oscillation tendencies nor any possibility of oscillations if the crystal is removed. The oscillator is designed such that no external components other than the crystal are required. In addition, the oscillator may be bypassed by removing the crystal and driving the circuit directly from an external source connected to the same pin. Using this design, several circuits with identical oscillators may share the same crystal, thus insuring synchronous operation.

FIG. 1 is a schematic view of a basic oscillator block.

FIG. 2 is a schematic view of an embodiment of the oscillator of the invention.

FIG. 3 is a schematic view of another embodiment of the oscillator of the invention.

FIG. 4 is a schematic view of still another embodiment of the oscillator of the invention.

FIG. 5 is the schematic view of FIG. 2 with transistors substituted for the capacitors.

In FIG. 2 an embodiment of the one-pin crystal oscillator of the invention is depicted and identified by the numeral 20. This embodiment is implemented using a NMOS process.

Transistor M.sub.1 is the actual gain element of the oscillator. Transistor M.sub.1, in a preferred embodiment is a depletion mode FET (Field Effect Transistor). Transistor M.sub.2 is the biasing current source which has a grounded gate. Transistor M.sub.2 in a preferred embodiment is also a depletion mode FET. Together these elements, along with the feedback network composed of the crystal Y.sub.2 and capacitors C.sub.1 and C.sub.2, give the necessary loop gain and phase shift for oscillations to occur.

As can be seen in FIG. 2, the drain terminal of transistor M.sub.1 is connected to V.sub.DD with the source terminal thereof connected to a node 3 which is connected to the drain terminal of transistor M.sub.2. The source of transistor M.sub.2 is connected to ground which can be considered node 2 of the above basic oscillator block circuit. Capacitors C.sub.1 and C.sub.2 are connected in series between the gate of transistor M.sub.1 (node 1) and the ground (node 2). The connection between capacitors C.sub.1 and C.sub.2 is communicated with node 3. Crystal Y.sub.2 is also connected between node 1 and node 2.

Resistors R.sub.1 and R.sub.2 are connected between V.sub.DD and ground at node 2. A transistor M.sub.3 is provided such that its gate is connected to V.sub.DD, with its drain connected to the gate of transistor M.sub.1 and its source connected to the line connecting resistors R.sub.1 and R.sub.2. In a preferred embodiment, transistors M.sub.3 is an enhancement mode FET. Since a very high impedance at the gate of transistor M.sub.1 is necessary, the bias voltage generated by resistors R.sub.1 and R.sub.2 is coupled to node 1 by transistor M.sub.3 whose small-signal source-drain resistance is made large. This configuration can give an impedance at node 1 on the order of one megaohm in the preferred embodiment while keeping the die area within allowable limits.

As node 3 is not externally available, capacitors C.sub.1 and C.sub.2 must be integrated. In the NMOS implementation 50 of the embodiment, capacitors C.sub.1 and C.sub.2 are realized using the gate capacitance C.sub.1 ', C.sub.2 ' of depletion transistors biased in the linear region. This is accomplished by tying the source and drain terminals together, the capacitance being provided between the gate terminal and the tied-together source and drain terminals. The capacitors of this embodiment, as specified below, are approximately one-tenth the size of the capacitors used in the prior art.

In this embodiment, the output of the oscillator 20 may be taken from either node 1 or 3. Node 1 is preferrable because its bias voltage is known precisely, and is generally closer to the threshold of a standard inverter. Also the output amplitude at node 1 is larger, thus requiring fewer stages of gain to generate a square wave.

In a preferred embodiment:

C.sub.1 =4 pF

C.sub.2 =2 pF

R.sub.1 =2 k.OMEGA.

R.sub.2 =2 k.OMEGA.

Y.sub.2 crystal parameters (a 4-MHz quartz crystal in preferred embodiment with low series resistance and low case capacitance).

R.sub.O =25 .OMEGA. (series resistance)

C.sub.O =15.1 fF (series capacitance)

L.sub.O =0.1048 H (series inductance)

C.sub.C =6 pF (capacitance between metallized electrodes of crystal)

It should be understood that other 4-MHz crystals can be used.

M.sub.1 =20/10 (W/L: Where W/L is the ratio of the width in microns to the length in microns of the gate of the fabricated FET)

M.sub.2 =20/10 (W/L)

M.sub.3 =5/660 (W/L)

The one-pin crystal oscillator of the invention can also be implemented in at least the two other ways depicted in FIGS. 3 and 4.

In FIG. 3 a CMOS process is used. This implementation has the same small-signal behavior as the embodiment of FIG. 2. The only difference is in the bias points, and thus the output signal amplitude and bias voltage. In the embodiment of FIG. 3, oscillator 30 has transistors M.sub.1A, M.sub.2A M.sub.3A which are preferably implemented with the p-channel FETs. In this embodiment, transistor M.sub.1A is the actual gain element of the oscillator 30, and transistor M.sub.2A is the biasing current source. Transistor M.sub.2A is biased at node 4 by an internally generated reference. Resistors R.sub.1A and R.sub.2A generate the bias voltage for node 1. Since a very high impedance at the gate M.sub.1A is necessary, this bias voltage is coupled to node 1 by transistor M.sub.3A, whose small-signal source-drain resistance is made large.

As node 3 is not externally available, capacitors C.sub.1A, C.sub.1B must be integrated. In CMOS implementation, this can be accomplished by either poly-poly or metal-metal capacitors.

As can be seen in FIG. 3, the source terminal of transistor M.sub.2A is connected to V.sub.DD with the drain thereof connected to node 3 to which the source of transistor M.sub.1A is connected. The drain of transistor M.sub.1A is grounded at node 2. Capacitor C.sub.2A is tied between nodes 2 and 3 with capacitor C.sub.1A and crystal Y.sub.3 provided in series between nodes 3 and 2. The point of interconnection of capacitor C.sub.1A and crystal Y.sub.3 is connected to the gate of transistor M.sub.1 and the source of transistor M.sub.3A. The gate of transistor M.sub.3A is grounded at node 2. Resistors R.sub.1A and R.sub.1B are provided in series between V.sub.DD and node 2 with their point of interconnection connected to the source of transistors M.sub.3.

Oscillator 40 in FIG. 4 is an NMOS implementation similar to FIG. 2 with the exception that the gate of transistor M.sub.3B is connected to V.sub.DD directly and M.sub.3B is a depletion mode transistor with transistor M.sub.1B being an enhancement mode transistor.

The operation of crystal oscillator 20 of FIG. 2 is as follows. The circuit essentially supplies energy to a crystal Y.sub.2 which operates in a parallel resonant mode. The crystal Y.sub.2 and capacitors C.sub.1, C.sub.2 operate as a feedback loop (and can be modeled as an LC circuit in an ideal situation) in order to regulate the energy provided to crystal Y.sub.2. The transistor M.sub.3 and the resistors R.sub.1 and R.sub.2 can be thought of as a single resistance in parallel with crystal Y.sub.2 in order to bias the gate of transistor M.sub.1. The input voltage to the feedback circuit is measured across capacitor C.sub.2 and the output across capacitor C.sub.1.

At resonance, crystal impedance is at a maximum, and a large feedback voltage is developed. If the frequency drifts above or below resonance, the crystal impedance decreases rapidly, decreasing feedback. Thus the crystal effectively determines feedback and stabilizes the oscillator output frequency.

In an ideal situation transistors M.sub.1 and M.sub.2 can be thought of as controlled current sources that either push current into or pull current from the node interconnecting capacitors C.sub.1 and C.sub.2. As the gate to source voltage of transistor M.sub.1 increases due to increased feedback from the feedback circuit, more current is pushed to node 3 than transistor M.sub.2 can handle, and the current is pushed to the node between capacitors C.sub.1 and C.sub.2 to energize the crystal Y.sub.2. As the gate to source voltage of transistor M.sub.1 decreases due to decreased feedback from the feedback circuit, less current is provided to node 3, and current is pulled from the node between capacitors C.sub.1 and C.sub.2 by transistor M.sub.2 providing less energy to the crystal Y.sub.2.

The limiting phenomenon which stabilizes oscillator output is that the transistors go into a non-linear operating region which reduces positive feedback and thereby stabilizes output amplitude.

For the circuit of FIG. 2 with the component values listed above, the parallel resonant mode frequency is about 4 MHz. It is to be understood that the frequency range for the embodiment of FIG. 2 is about 50 KHz to 20 MHz depending on the values of the components.

The operation of the other embodiments is similar to the embodiment described above.

Other objects and advantages of the invention can be obtained from a review of the figures and claims herewith.