Complex Magnitude Computation

This invention relates to digital signal processing and more particularly to digital processing which involves computing the magnitude of a complex number

Circuits for computing magnitudes of complex numbers are widely used. Navigation and fire control systems, for example, make extensive use of such circuits. Both analog and digital approaches are used, and in the case of digital implementation, a special purpose circuit may be used or a general purpose computer may be employed.

As new signal processing applications have developed, they have brought with them the need for more rapid and accurate computations, trends which are often at cross purposes. These requirements are manifested for example in real time digital signal processing in such areas as radar, acoustics and image processing. Although iteration is often employed in such applications to achieve precision, the resultant process is time-consuming and limits the computation rate.

It is accordingly an object of the invention to provide a complex magnitude computing process and circuit which simultaneously provides high precision and high throughput. Another object of the invention is to provide a digital circuit for computing complex number magnitudes which is amenable to VLSI or gate array implementation. A still further object is to provide a complex magnitude computing technique amenable to expanded word length and increased resolution.

These objects are achieved by a complex magnitude computing circuit which implements piece-wise linear approximations to achieve high precision without the need for iteration and its processing burden. Coefficients and parameters for such approximations are derived to take the form of binary fractions to facilitate implementation.

Serving to illustrate exemplary embodiments of the invention are the drawings of which:

FIG. 1 is a functional block diagram illustrating the stages of a complex magnitude computer;

FIG. 2 is a graphic plot of relative error;

FIG. 3 is a schematic circuit diagram illustrating the input and initial stages of a specific complex magnitude computing circuit; and

FIG. 4 is a schematic diagram illustrating the arithmetic and output sections of the circuit of FIG. 3.

The complex magnitude of

Z=A+iB,

r(A,B)=.sqroot.A.sup.2 +B.sup.2

can be represented by a dual piecewise linear approximation and an error term: ##EQU1##

The coefficients a and b may be related by the variable X=b/a where 0.ltoreq.X.ltoreq.1. X may then be assigned the value of R(X) to minimize the relative error within the range of 0.ltoreq.X.ltoreq.1. This is achieved by equating the relative errors:

and solving 2 non-linear simultaneous equations.

The accuracy of this method for various values of a and b ranges from 3.96% to 11.3% relative error.

To achieve a more accurate approximation, the interval (0,1) may be divided into subintervals. In the case of two subintervals, the coefficients a.sub.1, b.sub.1, and a.sub.2, b.sub.2 of the relative error function in each subinterval and the subinterval dividing point, (w) can be derived to minimize the maximum error over the entire range. Thus: ##EQU2##

FIG. 2 is a plot of the composite relative error function which may be defined as ##EQU3##

The general parameters a.sub.1, b.sub.1, a.sub.2, b.sub.2 and w are calculated from the following system of five non-linear equations:

Table 1 gives the results of a solution of these equations. Note that the dividing point, w, is quite likely equal to .sqroot.2-1. From a hardware standpoint, implementing this value of w has disadvantages in that it requires an extra, time-consuming multiplication. However, as will be shown below, another approximation leads to an avoidance of this shortcoming.

w=0.414214

a.sub.1 =0.990299

b.sub.1 =0.196983

a.sub.2 =0.839535

b.sub.2 =0.560960

The first coefficient, a.sub.1 =0.990, is sufficiently close to 1, so that setting it equal to unity would simplify the hardware without significantly affecting the accuracy. Rerunning the parametric analysis with this restriction gives the remaining four parameters (see Table 2). Note that in this case the value of the subinterval dividing point w (0.378227) is very close to the value 3/8 which, being a binary fraction, is much easier to implement in hardware. As will be seen, the approach permits all parameters to be implemented as binary fractions thereby yielding significant hardware advantages.

w=0.378227

a.sub.1 =1.0

b.sub.1 =0.150824

a.sub.2 =0.849509

b.sub.2 =0.548710

A fixed point data representation analysis gives the remaining parameters as binary fractions which are listed in Table 3. The final error analysis plot is illustrated in FIG. 2 while the maxima and minima and value of w are listed in Table 3. As can be seen, implementation guarantees a worst-case relative error of 1.21% which is significantly (more than 3 times) better than the initially described single interval case.

w=0.375

a.sub.1 =1

b.sub.1 =20/128

a.sub.2 =109/128

b.sub.2 =70/128

min 1=-0.01213266752

max 1=0.00880778468

min 2=-0.01204172986

max 2=0.01115536068

The general organization of one circuit for implementing the algorithm is shown in FIG. 1 where the real and imaginary (or in-phase and quadrature) signals A and B of the complex input Z are each converted to their absolute values in stage S1 to produce binary signals .vertline.A.vertline. and .vertline.B.vertline.. Illustratively, A and B are each represented by 8 bit 2's complement binary signals, a.sub.7. a.sub.6 a.sub.5 a.sub.4 . . . a.sub.0, while their absolute values are 7 bit words, .s.sub.6 s.sub.5 s.sub.4 . . . s.sub.0 (a.sub.7 and s.sub.6 are msb's).

Recalling from equation (1) that the dual approximations involve the maximum and minimum values as between .vertline.A.vertline. and .vertline.B.vertline., the circuit of FIG. 1 implements this selection with a stage S2 having digital circuits which compare the absolute values of A and B to determine and generate a 7 bit digital signal representing max(.vertline.A.vertline., .vertline.B.vertline.), designated X in FIG. 1 and a signal min(.vertline.A.vertline., .vertline.B.vertline.) designated Y.

As previously noted, to implement the two simultaneous non-linear equations, the signal X is subject to multiplication by the coefficients a.sub.1 or a.sub.2 depending on the active interval. This multiplication is implemented in a stage S4 for X while Y is similarly combined with its coefficients b.sub.1 or b.sub.2 in stage S5, also in dependence on the comparison.

To effect this comparison, i.e., to define the sector selection point dividing the two subintervals within the operative range, the digital comparator circuit S3 is employed. In this embodiment, a sector selection value is used such that Y is compared with the value 3X/8 and a corresponding logic level is applied to the multipliers S4 and S5 depending upon the results of that comparison thereby actuating the coefficients a.sub.1, b.sub.1, or a.sub.2, b.sub.2.

An arithmetic stage S6 combines the outputs of S4 and S5 to produce a resultant digital signal representing the magnitude of the input complex number Z.

A specific circuit configuration implementing the foregoing is illustrated in FIGS. 3 and 4. As shown in FIG. 3, the real and imaginary components of complex number Z appear as 8 bit 2's complement digital words A and B each of which is applied to a respective field programmable logic array U1, U2. The arrays are programmed to convert their respective inputs into absolute values. Thus, for example, with input A of the form d=a.sub.7. a.sub.6 a.sub.5 a.sub.4 . . . a.sub.0, an output is produced of the form 0.s.sub.6 s.sub.5 s.sub.4 s.sub.0. If a.sub.7 is 0, the output will equal d; if a.sub.7 is equal to 1, then the output will be the 2's complement of d.

Expressed relative to the input bits, the output bits are typically determined by ANDing and ORing combinations of input bits and their complements. For example the computations involving s.sub.0, s.sub.1 and s.sub.2 are:

These functions and those controlling the remaining bits are implemented in U.sub.1 and U.sub.2 ; they are determined in the case of two's complement by: ##EQU4## and in the case of absolute value by:

The absolute values, .vertline.A.vertline., and .vertline.B.vertline. are applied to respective registers U38 and U37. The absolute value of A clocked at the output of U38 has its three ms bits a.sub.4, a.sub.5, a.sub.6 applied to a comparator U3 which also receives the three msbs b.sub.4, b.sub.5, b.sub.6 of U37's output. The four lsb's at the output of U38, a.sub.0, a.sub.1, a.sub.2 and a.sub.3 are applied to comparator U4 along with the corresponding least significant bits of the B signal. The outputs of the comparators U3 and U4 are applied to a further comparator U5 having two output lines one of which will be high depending upon whether .vertline.A.vertline. is greater than or less than .vertline.B.vertline.. In the illustrative embodiment, data selector U6 receives the three ms bits of .vertline.A.vertline. and .vertline.B.vertline.. Data selector U7 receives the four ls bits of .vertline.A.vertline. and .vertline.B.vertline.. Consequently, the combined output X of selectors U6 and U7 will represent either .vertline.A.vertline. or .vertline.B.vertline. depending upon which of those is larger.

A similar arrangement characterizes U8 and U9. U9 receives the four ls bits of .vertline.A.vertline. and .vertline.B.vertline. while U8 receives the three ms bits of both variables. Depending upon the condition of the select line of U8 and U9, (which U5 will make high or low depending upon the relationship of .vertline.A.vertline. to .vertline.B.vertline.), the combined output Y of U8 and U9 will be either .vertline.A.vertline. or .vertline.B.vertline. depending upon which has the smaller value.

Outputs X and Y are applied to registers U11 and U12 respectively. The output of U11 is applied in turn to a register U21 whose output is applied to a register U24. That register has its seventh bit determined by the output of OR gate U39.

A similar data flow may be traced for the Y input to register U12. The output of the latter is applied to a register U15 whose output is applied in turn to a register U23. As with U24, this register has its seventh bit determined by the output of OR gate U39.

The state of U39 is determined by a comparison of signal Y with the term 3X/8 which indicates the boundary between sub-intervals. The term 3X/8 is obtained by applying signal X to a pair of cascaded 4-bit binary full adders U13 and U14. The bits are distributed between the two to in effect multiply X by 0011 (binary), i.e. by 3. The resultant outputs are applied in turn to register U16. In addition, the least significant bit of U13 is applied to one stage of a register U17 whose q output is applied to 4-bit magnitude comparator U19 along with bits 4 through 7 of the output of U16 and bits 4 through 8 of the output of U15.

Another 4-bit magnitude comparator U18 receives bits 0 through 3 of U16 along with bit .0. of U15. A third magnitude comparator working with U18 and U19 is U20 which receives bit 6 from U15.

The comparisons made by U18, U19 and U20 are reflected in their output lines which are connected to 4-bit magnitude comparator U22 whose output lines constitute the inputs to the previously mentioned OR gate U39. As a consequence of the foregoing comparisons and bit manipulations, Y is compared with 3X/8 thus determining the output of U39 as true or false and thereby specifying the operating sub-interval and active coeffecients.

As previously mentioned, the state of U39 determines whether bit 7 (the eighth bit) of the X and Y registers U24 and U23 are on or off. As a consequence, the coefficient of X and the coefficient of Y will have one of two values depending upon the comparison of Y to 3X/8.

As seen in FIG. 4, the outputs of U24 and U23 are applied to a set of logic arrays U25, U27, U29 and U31 in the case of the X output and to U26, U28 and U30 in the case of the Y output. These stages and those they drive constitute the arithmetic section of the magnitude computing module and both the X channel and Y channel logic arrays are programmed to multiply the X and Y signals by the appropriate coefficients.

The resultant in the X channel is applied to a register U32 while the Y channel computation is applied to a register U33. The outputs of these registers are each directed to the cascaded adders U34 and U35. The outputs of the latter are combined in register U36 to provide a combined output at the data bus output OB for use as required. The result may also appear on a display of any convenient form, e.g., by displaying the 4 msb's and 4 lsb's in side-by-side relationship as illustrated.

For pipelining, the various interstage registers referred to above are synchronized from a clock source CP, FIG. 3, which produces an output CP.sub.1 and CP.sub.2 via inverters U10. The interstage registers synchronized by these sources are U37/U38, U11/U12, U15/U21, U23/U24, U32/U33, and U36.

By way of providing further implementation details, the registers in this implementation are 74LS377 types; the 4-bit magnitude comparators are each a 74S85. The data selector type is a 74LS157 while the 4 bit adders are each a 74S283.

The circuit of FIGS. 3, 4 operates at a maximum absolute error of 2.2%, a value which can be reduced with higher resolution. The synchronization rate is 10 mhz.

Longer word lengths e.g. 12 bit inputs, may be utilized. Also the interstage pipelining registers may be eliminated for straight combinatorial implementation with some sacrifice in speed.

Adoption of new developments in digital hardware technology (e.g., high speed 8K proms) would lead to circuit simplification along with increased accuracy and speed. The analytical algorithm would remain unchanged. The ultimate hardware realization would be the consoldition of all logic onto a single integrated circuit.