US 4,598,462 AGrant
Method for Making Semiconductor Device With Integral Fuse
Issue Date:1986-07-08
•7 Claims
•4 Drawing Sheets
Abstract
A semiconductor device and method for making same having dielectrically isolated individual elements such as transistors, diodes, et al. Some of the isolated elements having fuses formed integral thereto.
Metadata
Assignee
- RCA Corporation
Inventor
- Hosekere S. Chandrasekhar
Application Information
Application Number:US 7150393
Filing Date:1985-03-22
Priority Date:1983-04-07
Art Unit:114
Classifications
IPC:
H01L 21225
Field of Search:
29148357577 C;576 B;5911.5;DIG. 5549;51;55
Patent Drawings (4 sheets)
Description
The present invention relates to dielectrically isolated fusible devices and more particularly to such devices having the fuse element integrated into the device structure, and method of making same.
Semiconductor devices having dielectrically isolated well regions heretofore have been formed independent of the formation of fuse elements that may be associated therewith. That is, the fuse element has not been formed integral to the well region, but rather, has been arranged external thereto. Frequently, a portion of a conductor which interconnects two or more well regions on the same semiconductor device is utilized as the fuse element. In such cases the portion of the conductor that is to be the fuse is formed with a cross section that is considerably smaller than that of the rest of the conductor. When sufficient current is passed through the conductor, the portion having the reduced cross section will fuse and thereby open the circuit. See, for example U.S. Pat. No. 3,564,354, issued Feb. 16, 1971 to Aoki et al and U.S. Pat. No. 3,699,395 issued Oct. 17, 1972 to Boleky, both of which disclose such structures.
Summary of the Invention
According to the present invention a semiconductor device is disclosed having a substrate and a plurality of spaced apart well or conductive regions formed therein. An insulating means is provided for dielectrically isolating the conductive regions from each other and from the substrate. A fuse element comprising platinum silicide is associated with and formed integral to at least one of the conductive regions.
Brief Description of the Drawings
FIGS. 1 through 12, 12a and 13 through 16 are schematic representations of cross sectional views of a portion of a semiconductor device showing various steps of manufacture utilizing the teachings of this invention.
Description of the Preferred Embodiment
The device shown in FIG. 1 has a plurality of dielectrically isolated well or conductivity regions, some of which are of n-type conductivity material and others are of p-type conductivity material. Such wafers are well known in the art as are the methods for making them. For more detailed information on the structure and methods of manufacture of such devices, the reader is referred to U.S. Pat. No. 3,852,802, issued on Dec. 3, 1974 to Wolf et al and U.S. Pat. No. 3,954,522, issued on May 4, 1976 to Robinson. For purposes of this disclosure the device shown in FIG. 1 is presumed to be easily obtainable by one skilled in the art and therefore will represent the starting point in describing the semiconductor device of the present invention and the method for making same.
Referring to FIGS. 1 through 16 there is shown a portion of an integrated circuit in cross section including a substrate and a plurality of spaced apart well or conductivity regions 4. Each of the well regions 4 are dielectrically isolated from the substrate 2 by a layer of silicon oxide 6 or some other suitable dielectric material. The well regions 4 form individual elements such as transistors, diodes, memory devices, or the like and are composed of various semiconducting materials suitable for the specific element desired.
Referring to FIGS. 15 and 16 the well region shown in the preferred embodiment is an NPN transistor having an emitter 20, a base 22, and a collector 24. A pair of contacts 26 and 28 form electrical connections to the emitter 20 and base 22 respectively. A collector contact is made through a buried layer region 30, a deep collector diffusion 32, and a contact 34 on the surface of this integrated circuit. A layer of silicon dioxide 40 or some other suitable insulating material is arranged in intimate contact with the surface 42 of the substrate 2 and extends over the plurality of well regions 4 thereby completely covering the surface of the semiconductor device except for the contacts 26, 28, and 34. A fuse 50 is disposed on the layer of silicon dioxide 40 directly above the well region 4. The fuse 50 comprise a fuse element 52, a holder 54, and a pair of fuse contacts 56. As is best seen in FIG. 12a the fuse element 52 has a portion 53 of reduced cross section area which defines the current and time characteristics of fusing.
Turning now to the method of manufacturing the semiconductor device of the present invention, a relatively thick insulating layer 60, which may be silicon dioxide for example, is deposited; or otherwise formed on the surface 42 of the substrate 2. An opening 62 is then etched in this layer 60 through a suitable mask 64 as shown in FIG. 2. A base 22 is then diffused into the collector 24 through the opening 62, or implanted and then diffused, and the mask 64 removed. The diffusion process partially restores the layer of silicon dioxide 60 directly over the collector whereupon additional silicon dioxide is formed to completely restore the layer 60 as is shown in FIG. 3. A layer of silicon nitride 53 having a thickness of approximately 2000 angstroms is then deposited on the layer of silicon dioxide 60 followed by a layer of polycrystalline silicon (polysilicon) 51 having a thickness of approximately 1000 angstroms. This double layer of silicon nitride and polysilicon extends over the entire wafer and comprises the material from which the fuses 50 are made. A mask is positioned over the double layer and is arranged to define the fuse 52 as shown in FIG. 12a. Excess polysilicon is then etched away. A second mask is then utilized to define the fuse holder 54. The excess silicon nitride is then etched away leaving the fuse element 52 upon the rectangular holder 59, as shown in FIGS. 6 and 12a.
An opening 66 is then etched in the layer 60 through a suitable mask as shown in FIG. 7 and an emitter 20 is either diffused into the base 22 or implanted and then diffused. The diffusion process partially restores the layer of silicon dioxide 60 directly over the base whereupon additional silicon dioxide is formed to completely restore the layer 60 as shown in FIG. 8. A plurality of openings are then formed in the layer 60, one opening directly over each area of the well region where an electrical contact is to be established thereby defining contact areas 78. A layer 80 of platinum having a thickness of approximately 700 angstroms is then formed on the entire surface of the wafer including the fuse element and the contact areas 78, as shown in FIG. 10. The platinum layer 80 is formed by platinum sputtering techniques well known in the art. The wafer is then heated to a temperature of 650.degree. C. for 13 minutes whereupon the platinum alloys with the fuse element 52 and the surfaces of the contact areas 78 forming platinum silicide. The residual platinum is then etched away from the wafer as shown in FIG. 12. A heavy layer 83 of silicon dioxide or similar protective coating is formed on the fuse 52 in the area indicated by the broken lines 84 shown in FIGS. 12a and 13. This layer 83 is used to protect the delicate fuse element 52 while forming electrical contacts at each end thereof.
A layer 90 of titanium having a thickness of approximately 2000 angstroms is formed on the entire surface of the semiconductor including the two ends or extremities of the fuse element 52 and the surfaces of the contact areas 78. A layer 92 of aluminum having a thickness of approximately 15,000 angstroms is then formed on the layer 90 of titanium. The layers of titanium and aluminum are formed in any conventional but suitable manner well known in the art such as sputtering or evaporation. The layers 90 and 92 of titanium and aluminum are then removed from all areas of the semiconductor except the two ends of the fuse element 52 not covered by the layer 83 of silicon dioxide and the contact areas 78. This procedure yields a pair of electrical contacts 56, one disposed at each extremity of the fuse element 52, and electrical contacts 26, 28, and 34 arranged on the surfaces of the emittor 20, base 22, and collector 24 respectively, as shown in FIG. 15. Finally, a protective passivation layer 100 of phosphorus silicate glass is applied to the entire surface of the wafer.
The method described herein pertains to the construction of a single NPN transistor with an integral fuse. As pointed out above, the starting wafer shown in FIG. 1 has a plurality of dielectrically isolated well regions, some of which are of n-type conductivity material and others are of p-type conductivity material. Therefore, a variety of individual elements such as transistors, diodes, et al, some containing fuses, may be concurrently constructed on the wafer. The individual elements may be electrically interconnected by metal conductors 94, as best seen in FIG. 16, thereby forming an integrated circuit device. The metal conductors may be formed by dual layer metallization techniques the methods of which are known by those skilled in the art, or any other suitable method.
Claims
I claim:
1. A method of forming a semiconductor device comprising the steps of: (a) forming a plurality of spaced apart first conductivity type regions in the surface of a substrate, each of said regions being dielectrically isolated from said substrate; (b) forming a base of second conductivity type within at least one of said plurality of regions; (c) forming a layer of silicon oxide on the surface of said at least one region; (d) forming a layer of silicon nitride on said layer of silicon oxide; (e) forming a layer of polycrystalline silicon on said layer of nitride; (f) removing a portion of said layers of nitride and polysilicon to define a fuse element of the remaining portion of said layers; (g) forming an emitter of first conductivity type within said base formed in step b; (h) forming a layer of silicon oxide upon said emitter; (i) forming a plurality of openings in said layer of silicon oxide; thereby exposing portions of said regions; (j) forming a layer of platinum upon said layer of silicon oxide, said exposed portions of said regions, and said fuse element; (k) heating said semiconductor and alloying said platinum and said remaining portion of polysilicon of said fuse element and said portions of said regions to form platinum silicide; (l) removing residual platinum from said semiconductor leaving said platinum silicide fuse element and said platinum silicide portions of said regions; (m) forming a plurality of electrical contacts, one at each of two extremities of said fuse element and one at each of said portions of said regions; (n) interconnecting said electrical contacts to form an integrated circuit.
2. The method is set forth in claim 1 wherein the base of step (b) and the emitter of step (g) are formed by implanting.
3. The method is set forth in claim 2 wherein the layers of silicon oxide of steps (c) and (h) are formed by diffusing said base and said emitter respectively.
4. The method is set forth in claim 3 wherein step (m) includes the steps of: (m1) forming a layer of titanium upon said semiconductor; (m2) forming a layer of aluminum upon said layer of titanium. (m3) removing said layers of titanium and aluminum formed in steps (m1) and (m2) from said semiconductor except from said two extremities of said fuse element and from each of said portions of said regions.
5. The method as set forth in claim 4 wherein step (m1) is preceded by a step of forming a layer of silicon dioxide on a portion of said fuse element.
6. The method as set forth in claim 5 wherein said interconnecting of electrical contacts in step n is effected by dual layer metallization techniques.
7. The method as set forth in claim 6 including a final step of passivating said semiconductor.
Patent Citations (12)
| Patent | Date | Inventor | Cited By |
|---|---|---|---|
| US3391023 | 1968-07-01 | Frescura | |
| US3564354 | 1971-02-01 | Aoki et al. | |
| US3619725 | 1971-11-01 | Soden et al. | |
| US3699395 | 1972-10-01 | Boleky | |
| US3699403 | 1972-10-01 | Boleky, III | |
| US3852802 | 1974-12-01 | Wolf et al. | |
| US3865649 | 1975-02-01 | Beasom | |
| US3895392 | 1975-07-01 | Polata et al. | |
| US4042950 | 1977-08-01 | Price | |
| US4299024 | 1981-11-01 | Piotrowski | |
| US4553318 | 1985-11-01 | Chandrasekhar | |
| JPX105988 | 1979-08-01 |
Non-Patent Literature (1)
- Isolation Techniques for Very Large Scale Integration, D. Beernaert, G. Schols, P. Van Iseghem, The Technical Journal.