Differential Common Base Amplifier With Feed Forward Circuit

The invention relates to differential common base amplifier circuits, especially of the type having field effect transistor input stages, and more particularly to circuitry for preventing variations in the gate to source voltage characteristics of the field effect transistors from causing variations in the input offset voltages of the differential common base amplifier circuits, and still more particularly to techniques for preventing roll off of the frequency response of differential common base amplifier circuits.

Several differential common base amplifiers are known, and have various advantages, including optimum bandwidth that results from the use of the common base connection of bipolar transistors. I.e., differential common base amplifiers have high frequency response because the common base connection of a bipolar transistor has superior bandwidth characteristics. However, since the "input characteristics" of a common base connection of a bipolar transistor have various shortcomings, including the disadvantage that the input impedance of a common base connected transistor at its emitter terminal is low, its DC input current is high and its associated noise current is high. For these reasons, it is common to drive the two inputs of a common base differential input stage with emitter follower circuits. The input impedance of such follower circuits is very high, resulting in fairly low input currents and low associated noise currents. But it would be very desirable for certain low noise applications to have lower noise currents than is achievable with bipolar emitter followers. Ordinarily, JFET input circuitry would be used to achieve low noise operation, but, for the reasons subsequently explained, JFET source followers are incompatible with common base differential input circuitry.

Before describing the limitations of common base differential input stages driven by source follower circuits it will be helpful to briefly describe the structure and shortcomings of such a device with reference to FIG. 5 of the appended drawings. Referring now to FIG. 5, reference numeral 40 designates a typical prior art, common base differential input stage including two NPN transistors 8 and 9 having their bases connected together. The base of transistor 8 is connected to its collector and to a constant current source circuit 12. Typically the output of a bipolar emitter follower (not shown) is connected to the emitter of transistor 8. Similarly the collector of transistor 9 is connected to a second current source 13. Typically, the output of another emitter follower is connected to the emitter of transistor 9. The collector of NPN transistor 9 is coupled by means of conductor 11 to the base of an NPN output transistor 14. The emitter of transistor 14 is normally connected to a relatively constant voltage source circuit which is schematically represented by a battery having a voltage V.sub.B in FIG. 5. The collector of output transistor 14 is connected to a constant current source load circuit 18. The constant current sources of circuits 12, 13, and 18 can be lateral PNP current mirror circuits, which have high dynamic resistance, and are well known to those skilled in the art. An output voltage V.sub.O is produced on the collector of output transistor 14.

It is desirable that transistor 14 be an NPN transistor, even though for simple biasing, a PNP transistor would be better because lateral PNP transistors that can be fabricated in conventional bipolar integrated circuit manufacturing processes commonly used for linear integrated circuits have very low frequency response.

It would be desirable to use FET source followers, as shown in FIG. 5, in order to achieve low noise operation. But, unfortunately, in the circuit shown in FIG. 5, wherein the voltage at the emitter of transistor 14 is relatively constant, and source followers 4 and 5 are used as shown, if there are shifts in the gate-to-source voltage characteristic of JFET (junction field effect transistors) 4 caused by variations in integrated circuit processing variations or by variations in operating temperature of the circuit, such variations in the gate-to-source voltage characteristic of field effect transistor 4 result in a corresponding change in the voltage on the bases of NPN transistors 8 and 9. Since the voltage of the emitter, and hence also of the base, of output transistor 14 remains relatively constant, there is an equal change in the collector to base voltage of transistor 9. Shifts of one to three volts in the gate-to-source voltage characteristic of junction field effect transistors are common for bipolar integrated circuit manufacturing processes that are most commonly used. (The "gate-to-source voltage characteristic" is value of the gate-to-source voltage V.sub.GS of the JFET for a predetermined drain current.) Obviously, such voltage variations, when imposed on the collector-to-base voltage of transistor 9, but not transistor 8, result in unacceptable variations of 0.3 to 1.2 millivolts in the input offset voltage of the differential pair of transistors 8 and 9, since input offset errors of more than 0.1 millivolts are usually unacceptable.

This mismatch between the collector-to-base voltages of transistors 8 and 9 results in an input offset voltage caused by the above-mentioned shifts in the gate-to-source voltage characteristic of the field effect transistor 4, of base width modulation in transistor 9. This input offset voltage could be multiplied by the stage of gain including transistor 9 and current source 13, followed by the stage including transistor 14 and constant current source 18.

Furthermore, any common mode voltage component of V.sub.in1 and V.sub.in2 similarly causes a corresponding change in the collector-to-base voltage of transistor 9; the resulting base-width modulation of transistor 9 does not occur in transistor 8, so input offset errors occur in the differential stage including transistors 8 and 9 and are amplified by the high gain of the circuit.

Because of these obvious problems, no one is known to have used source follower input circuitry in a differential common base amplifier to obtain low noise, high gain performance.

Thus, there remains an unmet need for a simple, easily fabricated differential common base amplifier circuit with very low noise performance, and for such a circuit that makes it possible to conveniently take advantage of the high frequency response characteristics of a bipolar NPN integrated circuit connected in a common base configuration.

Accordingly, it is an object of the invention to provide a simple, easily fabricated differential common base amplifier having very high input impedance and very low noise operation and low input offset errors despite normal shifts in operating temperature or manufacturing parameters for linear integrated circuits.

It is another object of the invention to provide a very high input impedance differential common base amplifier circuit which has a very low input offset voltage characteristic.

It is another object of the invention to provide a simple, accurate, extremely high frequency, high input impedance differential common base amplifier circuit which is very independent of fabrication-induced parameter variations.

Briefly described, and in accordance with one embodiment thereof, the invention provides a differential common base amplifier circuit including first and second bipolar transistors having their base electrodes connected together, first and second high impedance load devices coupled to their collectors, first and second input voltage follower circuits having outputs coupled to the emitters of the first and second bipolar transistors, the collector of the first bipolar transistor being coupled to produce a bias voltage on the common bases of the first and second bipolar transistors, the collector of the second transistor being coupled to a third bipolar transistor, a first input voltage being applied to the input of a transistor of the first voltage follower circuit and also being applied to a corresponding input of a transistor of a third voltage follower circuit, the output of which is connected to the emitter of the third bipolar transistor. In the described embodiment of the invention, the first and second transistors are NPN transistors, the first and second load circuits are constant current source circuits, such as lateral PNP current mirror circuits. The first, second, and third voltage follower circuits include first, second, and third P-channel junction field effect transistors having their sources connected, respectively, to the emitters of the first, second and third bipolar transistors. The collector of the third NPN transistor is connected to a third high impedance current source circuit and produces a second output. In one described embodiment of the invention, variations in the gate-to-source voltage characteristic of the first and second P-channel field effect transistors are matched by corresponding variations in the gate to source voltage of the third P-channel field effect transistor, and therefore such changes are equally impressed upon the base electrodes of the second and third NPN transistors. Consequently, there is no base width modulation of the second NPN transistor, and no variation in input offset voltage of the differentially connected first and second NPN transistors is produced. For high frequency operation, the voltage applied to the gate electrode of the first P-channel field effect transistor is "fed forward" to the emitter of the third NPN transistor with substantially higher frequency response than occurs for the primary signal path through the differential input stage of the circuit. This decreases "roll off" of the frequency response of the circuit. The use of the third voltage follower circuit to the emitter of the third NPN transistor allows that emitter to be utilized as a source follower output in which a signal is produced which is 180.degree. out of phase with the output signal produced on a collector of the third NPN transistor.

FIG. 1 is a schematic circuit diagram of one embodiment of the invention.

FIG. 2 is a schematic circuit diagram of another embodiment of the invention.

FIG. 3 is a circuit schematic diagram of a third embodiment of the invention.

FIG. 4 is a schematic circuit diagram of a fourth embodiment of the invention.

FIG. 5 is a schematic circuit diagram useful in explaining the shortcomings of the prior art.

Referring first to FIG. 1, the differential common base amplifier circuit 1 of the present invention is similar to the circuit previously described with reference to FIG. 5, except that the circuit represented by battery V.sub.B has been replaced by a P-channel field effect transistor 16 having its gate electrode connected to conductor 2, the conductor to which the input voltage V.sub.in1 is applied. I.e., NPN transistors 8 and 9 are connected with their bases common and their emitters connected to the sources of P-channel JFETs 4 and 5, respectively. V.sub.in1 and V.sub.in2 are applied by conductors 2 and 3 to the gates of JFETs 4 and 5, respectively. The collector of transistor 8 is connected to its base and to high impedance current source 12. The collector of transistor 9 is connected to high impedance current source 13 and to the base of NPN transistor 14, the collector of which is connected to +V. The emitter of transistor 14 is connected to the source of P-channel JFET 16, the gate of which is connected to conductor 2. The drains of JFETs 4, 5, and 16 are all connected to -V voltage supply conductor 6. The output of differential common base amplifier 1 is produced on conductor 15, which is connected to the emitter of NPN output transistor 14 and to the source of field effect transistor 16. Therefore, output transistor 14 operates as an emitter follower.

Another embodiment of the invention, shown in FIG. 2, is identical to the one shown in FIG. 1 except that constant current source circuit 18 is connected between the collector of output transistor 14 and +V conductor 7, and an output conductor 17 which is connected to the collector of transistor 14 producing a second output voltage V.sub.02.

The main advantageous characteristics of the present invention can be described with reference to FIGS. 1 and 2. Additional variations on the concept of the invention are shown in the implementations of FIGS. 3 and 4, subsequently explained.

To describe the benefits of eliminating the relatively constant bias circuit or reference circuit represented by battery V.sub.B in FIG. 5 with the P-channel JFET 16 shown in FIGS. 1-4, it is convenient to give several examples in which it is assumed that there is a zero common mode component of the input voltage applied to conductors 2 and 3. It is also assumed that NPN transistors 8 and 9 are nearly perfectly matched, as can be readily achieved at the present state of the art of the bipolar integrated circuit manufacturing technology. It is also assumed that on a particular integrated circuit chip, the gate-to-source voltage (V.sub.GS)parameters of each of the JFETs 4, 5, and 16 can be very precisely matched. Again, at the present state of the art, this is a very realistic assumption. However, the chip to chip variation in the value of the matched V.sub.GS clockwise values may vary by as much as approximately three volts.

One of the objectives of the addition of JFET 16 is to cause any change in the value of the characteristic of JFETs 4 and 5 on the emitters of NPN transistors 8 and 9, respectively, to have the same net effect on both the collector voltage and the base voltage of NPN transistor 9. As mentioned above, any variation in the collector to base voltage of NPN transistor 9 produces an input offset error in the circuit including the differential common base connection of transistors 8 and 9, because of the base width modulation that occurs in transistor 9. Such an input offset error is multiplied by the very high gain of the amplification stage including NPN transistor 9 and high impedance constant current source circuit 13, and, if the output is taken at conductor 17, is further amplified by a second high gain stage including NPN transistor 14 and high impedance current source 18.

It is assumed that the current through current sources 12 and 13 are equal, or that the emitter geometries of transistors 8 and 9 are ratioed in the same fashion as the ratio between the current sources 12 and 13, and that the geometries of JFETs 4, 5, and 16 are ratioed in accordance with their quiescent operating currents, so that their V.sub.GS characteristics are very closely matched.

Since the collector-to-base voltage of NPN transistor 8 is zero (by virtue of the short circuit connection), the collector to base voltage of NPN transistor 9 also needs to be zero, despite any temperature-induced or process-induced variations in the characteristics of JFETs 4, 5, and 16, if the circuits of FIGS. 1-4 are to have low input offset voltages and high common mode rejection and high common mode range. As previously mentioned, these process-caused variations in the V.sub.GS parameters of the JFETs can be up to three volts for different wafers from which the individual chips are produced during the manufacturing operation. However, on a particular chip, the V.sub.GS parameters of all of the JFETs 4, 5, and 16 will be very closely matched.

As an example of how the circuits of FIGS. 1-4 avoid input offset errors as a result of variations in the V.sub.GS parameters of the JFETs, assume that V.sub.GS for a particular chip is 1 volt for JFETs 4, 5, and 16, and that the common mode voltage applied to inputs 2 and 3 is zero volts. Then the voltage on the sources of JFETS 4, 5, and 16 will be -1 volt; this will also be the voltage on the emitters of NPN transistors 8, 9, and 14. The base-to-emitter (V.sub.BE ) voltages of each of the NPN transistors 8, 9, and 14 are closely matched (typically within 0.2 millivolts), the voltages on conductors 10 and 11 will be -1 volt plus the respective V.sub.BE voltages (which typically are approximately 0.6 volts), and the collector to base voltage of NPN transistor 9 will be zero volts, the same as for NPN transistor 8. Therefore, there will be no input offset error.

Next, assume that on a different chip, the V.sub.GS parameter of JFETS 4, 5, and 16 is 3 volts different than in the first example, or +4 volts. Again, the voltages on conductors 10 and 11 will be -4 volts plus V.sub.BE volts; the collector-to-base voltage V.sub.CB of transistor transistor 9 will again be zero volts. Therefore, it can be seen that throughout the range of likely variations in the V.sub.GS parameter of JFETs 4, 5 and 16, the collector-to-base voltage of NPN transistor 9 will remain at zero volts, so there will be no input offset error.

Thus, it can be seen that the above-mentioned very undesirable variation of input offset voltage that would be expected if integrated JFET source followers are used as input stages for the differential common base NPN transistor circuit 40 in FIG. 5 is completely avoided by using a JFET 16 that matches JFETs 4 and 5, rather than an emitter follower resistor or a relatively constant emitter bias circuit such as the one represented symbolically by letter V.sub.B if FIG. 5.

The foregoing analysis applies equally well to temperature-induced variations in the V.sub.GS parameters of JFETs 4, 5, and 16 as to process-induced variations, since these JFETs will all normally be at precisely the same temperature.

From the foregoing analysis, one skilled in the art will be able to readily see that any change in the common mode voltage applied to conductors 2 and 3 will produce exactly the same effect on conductor collector 11, as a result of the presence of JFET 16, as is produced on collector conductor 10 as a result of the source follower operation of JFET 4. Consequently, the embodiments of the invention shown in FIGS. 1-4 all have exceptionally high common mode rejection and common mode range. Common mode range is increased greatly over the circuit of FIG. 5, since in that circuit the emitter of transistor 14, and hence, conductor 11 are fixed at plus V.sub.BE. In the circuits of FIGS. 1-4, voltage on the collectors of transistors 8 and 9 track precisely with the common mode voltage applied to input conductors 2 and 3, until the current source circuits 12 and 13 become non-linear. The low frequency gain from the inputs to the V.sub.02 output is approximately 100,000, and the bandwidth is several hundred megahertz, which is an order of magnitude greater than could be achieved without the "feed forward" operation.

The reader who is not familiar with the details of input offset voltage of differential circuits and with the concepts of common mode rejection and common mode range is referred to the text "Operational Amplifiers: Design and Applications", edited by one of the the present inventors, G. Tobey and L. Huelsman, and incorporated herein by reference.

Output voltages of the differential common base amplifier of FIGS. 2-4 can be taken at either the emitter of NPN transistor 14, on conductor 15, or at the collector of NPN transistor 14, on conductor 17 or both.

If the output V.sub.02 is taken on conductor 17, then it is desirable that the high frequency impedance at the base of transistor 14 be as low as possible. Since the output impedance of both constant current source 13 and the collector of NPN transistor 9 are very high, it is necessary to reduce the effects of these high impedances by either adding a compensation capacitor, such as the one indicated by dotted lines 19 in FIG. 2, or by adding an emitter follower transistor such as 20 shown in FIGS. 3 and 4. In FIGS. 3 and 4, transistor 20 has its base connected to conductor 11 and its emitter connected to the base of NPN transistor 14. The collector of NPN transistor 20 can be connected to conductor 17, as shown in FIG. 3, or to the +V conductor 7, as shown in FIG. 4. The emitter of transistor 20 can be connected solely to the base of NPN transistor 14 in the well known Darlington configuration as shown in FIG. 3, or to a constant current source transistor such as 25 in FIG. 4. In either case, the impedance at the base of transistor 14 is substantially decreased.

In both FIG. 3 and FIG. 4, it is necessary to replace the short circuit connection between the base and the collector of NPN transistor 8 with emitter follower transistor 22, so that the collector to base voltage of transistor 8 is the same as the collector to base voltage of transistor 9, i.e., one V.sub.BE voltage drop.

In accordance with the present invention, the addition of JFET 16 provides an additional important advantage that substantially increases the frequency response of the differential common base amplifier of the present invention. That advantage is to provide a "feed forward" signal in response to V.sub.in1 wherein JFET 16 acts as a source follower that provides a replica of V.sub.in1 as an input to the emitter of NPN transistor 14 just as JFET 4 provides a replica of V.sub.in1 as an input to the emitter of transistor 8.

With respect to the signal produced by source follower JFET 16 as an input to the emitter of NPN transistor 14, NPN transistor 14 effectively operates as a grounded base transistor, which, as mentioned above, has a very high frequency response. The capacitance or low AC impedance associated with the base of transistor 14 causes that point to act as a "virtual ground" with respect to the small signal variations applied to the emitter of NPN transistor 14 in response to V.sub.in1.

In FIG. 2, NPN transistor 14, operating as a high frequency common base amplifier in response to the feed forward replica of V.sub.in1 on conductor 15 by source follower JFET 16, produces an amplified replica of having very frequency response on conductor 17. This high high frequency accuracy of the amplified "feed forward" signal component of V.sub.02 greatly reduces the frequency response roll off of the net V.sub.02 output signal.

Note that V.sub.02 includes a "feed forward component" passing through JFET 16, and also another component having lower high frequency accuracy produced by the differential common base transistors 8 and 9 as a result of the signals produced at the emitters of transistors 8 and 9 by JFET source follower transistors 4 and 5, respectively. The frequency response of the signal path through JFET transistors 4 and 5 is much lower than the frequency response of the signal path through JFET 16 and NPN transistor 14 because of the lower gain of the latter path.

In FIG. 4, practical implementations of the current source circuits 12, 13, and 18 are shown. Constant current source 12 is implemented by means of a lateral PNP transistor 27 and an emitter ballast resistor 35. Current source 13 includes lateral PNP transistor 28 and emitter resistor 36. Current source 18 is implemented by a P-channel JFET 33 having its source connected to the collector of lateral PNP transistor 32. Emitter resistor 37 is connected between the emitter of transistor 32 and +V supply voltage conductor 7. The base of transistor 32, the gate of JFET 33, and the bases of transistors 27 and 28 are connected to a fixed bias generated by an external circuit (not shown) that drives conductor 34 in FIG. 4.

In FIG. 4, diodes 30 and 31 act as clamping diodes which perform the function of improved overload recovery. NPN transistors 24 and 25 function as constant current sources for the emitter follower buffers that include NPN transistors 22 and 20, respectively.

Although the embodiments of the invention shown utilize source followers connected to the inputs of NPN transistors 8, 9, and 14, the above-described benefits of the invention could be accomplished using NPN emitter followers as well.

The above-described configuration provides the previously un-attainable benefit of very low noise operation in a differential input stage with very good common mode rejection, common mode voltage range, and low input offset voltage over the usual operating temperature range of -55 to +125 degrees Centigrade, and further provides very high bandwidth. These advantages have caused the assignee's OPA111 low noise Precision Operational Amplifier, which incorporates the present invention, to become one of the assignee's most commercially successful products in the short time since its introduction in December of 1983.

While the invention has been described with reference to a particular embodiment thereof, those skilled in the art will be able to make various modifications to the described structure and underlying method of operation without departing from the true spirit and scope of the invention. It is intended that all elements and methods which perform substantially the same function in substantially the same way to achieve the substantially the same result as the elements and method steps disclosed herein are to be encompassed within the invention.