Semiconductor Memory Device Having Clamp Circuits

(1) Field of the Invention

The present invention relates to a semiconductor memory device and more particularly to a semiconductor memory device comprising clamp circuits, each of which is connected to an end of a word line and each of which operates reliably without being affected by the resistance of the word line.

(2) Description of the Prior Art

Generally, in a semiconductor memory device having a large memory capacity, there are provided clamp circuits, each clamp circuit being connected to one end of each word line. The clamp circuit is operated in accordance with the selecting voltage input thereto from a word decoder connected to the other end of the word line so that the potential of the word line rises sufficiently when the word line is selected, and so that the potential of the word line is clamped to a low voltage when the word line is not selected, thereby ensuring the selecting operation of the word line.

However, since the operation of each clamp circuit of a conventional semiconductor memory device is greatly influenced by the resistance of a corresponding word line, the selecting operation of the word line is not reliable when the resistance of the word line is relatively high.

In order to eliminate the above-mentioned problems of conventional semiconductor memory devices, the present invention adopts the idea of operating a clamp circuit after the potential of a word line has become sufficiently high in a semiconductor memory device having a clamp circuit connected to an end of the word line.

It is an object of the present invention to prevent the operation of a clamp circuit from being affected by the resistance of a word line and to make the selecting operation of the word line reliable, thereby improving the overall reliability of a semiconductor memory device.

According to the present invention, this object is attained by providing a semiconductor memory device having clamp circuits, each of which is connected to a corresponding word line and each of which clamps the potential of a non-selected word line to a reference potential. Each of the clamp circuits comprises a flip-flop having a first terminal connected to the corresponding word line and a second terminal which receives a controls signal for operating each of the clamp circuits. The control signal is applied to the second terminal when the potential of a selected word line exceeds at least the potential necessary for inverting the condition of the flip-flop.

FIG. 1 is a block circuit diagram of the structure of a conventional word line clamp circuit;

FIG. 2 is a time chart which explains the operation of the circuit of FIG. 1;

FIGS. 3A and 3B are block circuit diagrams of a word line clamp circuit used in a semiconductor memory device of an embodiment of the present invention.

FIG. 4 is a time chart which explains the circuit of FIGS. 3A and 3B.

FIGS. 5A and 5B are block circuit diagrams of a word line clamp circuit used in a semiconductor memory device of another embodiment of the present invention;

FIG. 6 is a time chart which explains the operation of the circuit of FIGS. 5A and 5B;

FIGS. 7A and 7B are block circuit diagrams of a word line clamp circuit used in a semiconductor memory device of still another embodiment of the present invention; and

FIG. 8 is a time chart which explains the operation of the circuit of FIGS. 7A and 7B.

Before describing the embodiments of the present invention, a conventional semiconductor memory device is explained with reference to FIGS. 1 and 2.

FIG. 1 is a clamp circuit used in a conventional semiconductor memory device. The clamp circuit of FIG. 1 is composed of mutually cross-coupled metal-insulator-semiconductor (MIS) transistors Q2 and Q3, an MIS transistor Q1 connected between a high-voltage power source V.sub.CC and the MIS transistor Q2, and so on. The symbol R1 indicates an equivalent resistor of a word line, and to both ends of this resistor R1, i.e., the word line, are connected a word decoder WD and the drain of the transistor Q3 of the clamp circuit.

The operation of the clamp circuit of FIG. 1 is described with reference to FIG. 2. At or before the time t.sub.0, i.e., during a reset period, since the reset signal .phi..sub.R is high, the potential of the node N1 is charged to a high level via the transistor Q1, and the transistor Q3 is turned on. At a time near the time t.sub.0, the reset signal .phi..sub.R becomes low and the output WL0 of the word decoder WD rises. In this condition, since the transistor Q3 is turned on, the potential of the drain WL1 of the transistor Q3 rises in accordance with the ratio determined by the resistance of the resistor R1 of the word line and the gm of the transistor Q3. When the potential of the node WL1 reaches a potential which is equal to or higher than the threshold voltage of the transistor Q1, the transistor Q2 is turned on and the potential of the node N1 falls to approximately that of a low-voltage power source V.sub.SS. Thereby, the transistor Q3 is turned off and the potential of the node WL1 further rises.

In the above-mentioned conventional semiconductor memory device, however, if the resistance of the resistor R1 of the word line is too large, the potential of the node WL1 does not rise higher than or equal to the threshold potential of the transistor Q2, with the result that the transistor Q2 is not turned on. Therefore, as is illustrated in FIG. 2, the potential of the node WL1 does not rise even at or after the time t.sub.1, and the selecting operation of the word line is not performed reliably. In recent large-capacity semiconductor memory devices, the word lines are very thin and polycrystalline silicon and the like are often used as the material thereof. Therefore, the resistance of each word line is relatively high and the possibility of the above-mentioned disadvantages arising becomes very high.

According to the present invention, there is provided a semiconductor memory device which overcomes these problems.

The embodiments of the present invention are explained with reference to the drawings. FIGS. 3A and 3B illustrate the structure of a clamp circuit as an embodiment of the present invention. In FIG. 3A, the signal at each portion in the selected word line is shown. In FIG. 3B, the signal at each portion in the nonselected word line is shown. The clamp circuit of FIGS. 3A and 3B comprises cross-coupled MIS transistors Q2 and Q3 and a depletion-type MIS capacitor Q4 connected to the drain of the transistor Q2. The MIS capacitor Q4 is composed of a depletion-type MIS transistor whose source and drain are mutually connected to form one terminal and whose gate is used as the other terminal, thereby forming a capacitor. Since the MIS capacitor Q4 is composed of a depletion-type transistor, it operates as a capacitor even when the potential of the gate is lower than that of the source and the drain. In the circuit of FIGS. 3A and 3B, the drain of the transistor Q3 is connected to one end of the word line which has the same resistance as that of the resistor R1. The other end of the word line is connected to the word decoder WD.

The operation of the circuit in FIGS. 3A and 3B is explained with reference to FIG. 4. When the word line is in a selected condition, the output WL00 of the word decoder WD shown in FIG. 3A rises at the time t.sub.0. In this case, both drains of the transistors Q2 and Q3 are, at first, at a low level, and, consequently, each of the transistors Q2 and Q3 is cut off. Therefore, the drain potential WL01 of the transistor Q3 rises to a high-voltage power source V.sub.CC without being affected much by the resistance of the resistor R1 of the word line, and thereby the transistor Q2 is turned on. At the time t.sub.1 when the potential WL01 has risen to a sufficiently high level, even if a clamp-activating clock .phi..sub.CA applied via the MIS capacitor Q4 is rendered high, the drain potential N01 of the transistor Q2 is maintained at a low level because the transistor Q2 is in a turned-on condition. Therefore, the transistor Q3 is maintained in a cutoff condition. If the word line is in a non-selected condition, the ouput potential WL10 of the word decoder WD and the potential WL11 of an end of the word line shown in FIG. 3B are both at a low level, and, therefore, both of the transistors Q2 and Q3 in the clamp circuit are in a cutoff state. At the time t.sub.1, if the clamp-activating clock .phi..sub.CA applied to the MIS capacitor Q4 rises, the potential N11 of the drain of the transistor Q2 rises and, therefore, the gate of the transistor Q3 rises because the transistor Q2 is in a cutoff state. Thereby, the transistor Q3 is turned on and the potential WL11 at the end of the non-selected word line is clamped to V.sub.SS.

FIGS. 5A and 5B illustrate the structure of a clamp circuit used in a semiconductor memory device as another embodiment of the present invention. FIG. 5A illustrates the signals of every portion of the clamp circuit when the word line connected to the clamp circuit is in a selected condition. FIG. 5B illustrates the signals of very portion of the word line when the word line is in a non-selected condition. The clamp circuit of FIGS. 5A and 5B is composed of cross-coupled transistors Q2 and Q3, a depletion-type transistor Q5 connected to the drain of the transistor Q2, and so on. The gate and the source of the depletion-type transistor Q5 are commonly connected, and a clamp-activating clock .phi..sub.CA is applied to the drain thereof.

The operation of the circuit of FIGS. 5A and 5B is explained with reference to FIG. 6. When the word line is in a selected condition, the output WL00 of the word decoder WD shown in FIG. 5A starts to rise to a high potential level near the time t.sub.0. In this case, since the clamp-activating clock .phi..sub.CA is at a low potential level, both of the drain potentials N01 and WL01 of the transistors Q2 and Q3 are low, and the transistors Q2 and Q3 are both in a turned off state. Therefore, according to the rise of the output potential WL00 of the word decoder WD, the drain potential WL01 of the transistor Q3 rises to a high potential level without being affected much by the resistance of the word line. At the time t.sub.1 when the drain potential WL01 of the transistor Q3 has almost reached a high level, even if the clamp-activating clock .phi..sub.CA is rendered to be a high level, the drain potential N01 of the transistor Q2 is maintained at a low level and the transistor Q3 is maintained in a cutoff state because the transistor Q2 was previously turned on.

When the word line connected to the clamp circuit is in a non-selected condition, the output potential WL10 of the word decoder WD and the drain potential WL11 of the transistor Q3 shown in FIG. 5A are both maintained at a low potential level. At the time t.sub.1 when the clamp-activating clock .phi..sub.CA rises, the transistor Q2 is in a cutoff state, and, therefore, the transistor Q3 is turned on and clamps the potential WL11 at the end of the non-selected word line to a low-level voltage V.sub.SS.

FIGS. 7A and 7B illustrate the structure of a clamp circuit used in a semiconductor memory device of still another embodiment of the present invention. The clamp circuit of FIGS. 7A and 7B further comprises a MIS transistor Q.sub.6 which is connected in parallel to the transistor Q.sub.2 of the clamp circuit of FIGS. 3A and 3B and whose gate receives an inverted clamp-activating clock .phi..sub.CA. The other portions are the same as those of the clamp circuit of FIGS. 3A and 3B.

As illustrated in FIG. 8, since the inverted clamp activating clock .phi..sub.CA is high and the transistor Q.sub.6 is turned on during the reset period, i.e., before the time t.sub.0, the node N01 of FIG. 7A does not become a floating state but the potential thereof is clamped to V.sub.SS. In this condition, the transistor Q.sub.3 is surely turned off and the potential WL01 of the word line becomes sufficiently high.

As was mentioned above, according to the present invention, the word line clamp circuit is activated after the potential of the selected word line has become sufficiently high. Therefore, the transistor Q3 of the clamp circuit is in a cutoff state during the rising time of the word line potential, and the potential rise of the word line is not arrested by the clamp circuit even when the resistance of the word line is relatively large. This results in a reliable selection operation of the word line. It should be noted that, in each of the non-selected word lines, since the word line potential is reliably clamped to a low level by the addition of a clamp-activating clock, it is possible to prevent variation of the potential of each non-selected word line due to noise components and so on.