Method and Apparatus for Parallel Processing of Digital Signals Using Multiple Independent Signal Processors

This invention relates to digital computers.

The conventional digital computer is constructed in accordance with what is generally termed the von Neumann model and basically comprises a binary digital store and a single central processor with peripheral input and output units. The computer functions by executing a program which comprises a list of instructions in binary form which is held in part of the store. The instructions are fetched by the central processor one at a time from the store and each is obeyed in turn. The computer can thus only carry out a program one instruction at a time and however fast the speed with which it can obey the individual instructions, the requirement for a single step-by-step sequence constitutes a limiting constraint. Often the computation being performed is such that many parts of the computation are independent of each other and could be computed in parallel, however computers constructed according to the von Neumann model are unable to exploit this. If an alternative architecture to the von Neumann model could be designed to overcome this constraint it would offer many advantages. Various architectures using many processing units have been suggested recently but most of these conform to the von Neumann model and all have their limitations.

It is an object of this invention to provide a digital computer capable of effective multi-processor operation.

A computer according to the invention operates on digital information in the form of "packets". A packet is a collection of binary digits divided into fields. The fields are described more fully below and usually include instruction digits. A packet is identified by an "identifier" which is a unique digital value and may conveniently comprise the address where that packet is located. The identifier constitutes one field of the packet.

According to the invention a digital computer comprises:

digital store means for storing packets;

a plurality of independent digital processing units;

communication means for the transfer of packets between the processing units and the digital store means;

two groups of digital stores each arranged to store identifiers of packets, each group having transfer means for enabling any identifier stored in any store of a group to be transferred to any other store within that group, one group of identifier stores being arranged to carry identifies of packets which require processing and the other groups of identifier stores being arranged to carry identifiers of locations in the packet store which are available to receive packets; and

interface means between the processing units and both groups of identifier stores to enable transfer of identifiers in either direction between the processing units and the groups of identifier stores.

In preferred embodiments the number of identifier stores in each group corresponds to the number of processing units and the interface means couple each processing unit to an individual identifier store of each group. Preferably the identifier stores of the respective groups are coupled together in ring-like fashion through their transfer means.

The packet store may comprise a plurality of storage segments and it may be convenient but it is in no way essential that the number of storage segments corresponds to the number of processing units.

In operation the group of identifer stores which carry identifiers of packets which require processing present these identifiers through the interface means to the processing units when they are called for and the communication means, which may comprise a network or bus, allows the transfer of identifies from the processing units to address the packet store and to return identified packets to the processing units. Each processing unit functions in a manner analogous to the central processor of a conventional computer and contains its own instruction set which enables it to proceed with that part of the computation that is specified by the instructions in the packet. In the course of the computation new packets may be generated and these will require identifiers to enable them to be stored in the packet store.

Identifiers of those locations in the packet store that are available are carried in the second group of identifier stores and when required an identifier is called down from this second group through the interface means and the new packet is transferred through the communication means to the address in the packet store defined by the called down identifier.

It is a feature of the invention that identifiers are readily transferable through the transfer means from store to store within a group. The transfer means operate to even out the number of identifiers held in different stores as far as possible. Thus, as computation proceeds there will be a steady "sideways" transfer of identifiers throughout a group as well as "vertical" transfer of identifiers between the identifier stores and the processing units through the interface means. In embodiments of the invention, a controller associated with each store can provide the function of both the transfer means between neighbouring identifier stores and the interface means between an identifier store and associated processing unit.

In order that the invention may be more fully understood, reference will now be made to the accompanying drawing in which:

FIG. 1 illustrates in diagrammatic form a computer embodying the invention, and

FIG. 2 shows diagrammatically a packet divided into fields.

The computer illustrated in FIG. 1 comprises a main store 1 for storing packets and which is divided into store segments 1a, 1b, etc. Any number of such store segments can be provided. All the segments of store 1 are connected through segment controllers 8a 8b etc. associated with each store segment to a communication facility 2 which may comprise a bus or network. The segments of store 1 are so organised that every location has a unique address. Store 1 as a whole thus acts as a unitary store. An address selection mechanism is provided for store 1. Segment selection occurs in communication facility 2 and the relevant segment controller 8a or 8b, etc. functions to select the required location within a segment. Thus the presentation of any valid identifying address causes the selection of the appropriate location in one of the segments, for writing to or reading from as required. Segment controllers 8a, 8b, etc. may also have an active role in modifying packets stored in the store segments to which they are connected.

Store 1 may be formed of segments as shown or else can be a single store. It may be constructed from magnetic or semiconductor memory or any other suitable digital storage medium.

The computer has a plurality of separate processing units 3a, 3b, etc. which are independent of each other and which can carry out a prescribed set of computation operations according to instruction sets stored internally. All processing units are connected to the communication facility to enable packets to be read from store 1 to any processing unit and to be written into any location in store 1 from any processing unit.

Identifiers, which are the addresses in store 1 of packets, are stored in either of two groups of identifier stores. One group 4a, 4b, etc. stores identifiers of packets which require processing while the other group 5a, 5b, etc. stores identifiers of locations in store 1 which are available to receive packets. Identifier stores 4a, 4b, etc. are coupled to associated controllers 6a, 6b, etc. Similarly identifier stores 5a, 5b, etc. are coupled to associated controllers 7a, 7b, etc. The identifer stores are preferably linear stores in which the identifiers are held in a single sequence. Stack or "push-down" stores are examples of such stores.

The controllers 6a, 6b, etc. and the controllers 7a, 7b, etc. have two functions. One function is to act as transfer means whereby identifiers held in the identifier store coupled to that controller can be transferred to other identifier stores in a group. The other function is to act as an interface to the associated processing unit for the provision of identifiers from the identifier store to the processing unit when called for and the storage of identifiers in the identifier store when provided by a processing unit.

As to the transfer function from store to store in a group, the controllers operate to even out the number of identifiers in each store of a group as far as feasible. Since the identifiers are in a linear sequence the identifiers for transfer can be selected for transfer on a "first in first out" basis or on a "last in first out" basis. To facilitate transfer all the controllers of a group can be coupled together in ring-like fashion with all transfers neighbour to neighbour, but this is not essential and other forms of connection can be provided as long as it is possible to transfer any identifier to any store in a group eventually.

The layout of a packet is shown in FIG. 2. A packet comprises three primary fields 11, 12 and 13. Field 11 is the identifier of the packet, that is its unique identification and this is normally the address in the packet store at which the packet is located. Field 12 is known as the function field and holds binary data specifying the operations to be carried out when this packet is processed. Field 13, known as the argument list field, contains the identifiers of packets containing data required during the processing of this packet (i.e. the arguments of the function). When a packet is employed to represent a numeric value, field 13 holds the number in binary form. In addition, there are three secondary fields 14, 15 and 16 which hold information pertinent to controlling the operation of the computer. The function of these secondary fields will be described below.

If packet store 1 is implemented using conventional addressable memory, the packet when stored in the packet store need not include the identifier field 11 as this information is implicitly in the binary digital value of the address of the location of the packet within the store.

The mode of operation of the computer illustrated in FIG. 1 is that the identifiers of packets in store 1 which are available to be processed are supplied to identifier store group 4a, 4b, etc. Whenever a processing unit requires further work it removes an identifier from its associated identifier store and supplies this address through communication facility 2 to obtain the contents of the packet contained in the location in store 1 named by that identifier. Processing then takes place in the processing unit in accordance with the operation defined by the function field 12 of the packet and the instructions stored within the processing unit. Such processing may generate further packets which will be required to be stored and where a location is needed to store a newly generated packet the processing unit removes an identifier from its associated identifier store 5a or 5b etc. and sends the new packet with its identifier through communication facility 2 to store 1. The identifier of the packet is then used to address the location in store 1 where the packet is to be written. If a new packet requires processing, the processor generating that packet places the identifier of that packet in its associated identifier store 4a or 4b etc.

Clearly not all packets are processable at any one instant. For example the function field 13 may specify an arithmetic operation the operators of which (the packets whose identifiers are listed in the argument list field) are not all in the required form. Use may therefore be made in a packet of the status field 14 and the signal list field 16 to implement an arrangement whereby a packet can be marked as not currently processable and signals sent to it when the processing of other packets make it processable. When a packet is not processable due to the fact that it requires other packets to be further processed, its indentifier is placed in the signal list field 16 of the packets that it is waiting on. In addition a part of its own status field 14 is set to indicate that the packet is waiting. Such a packet is termed "asleep". The identifiers of asleep packets are not held in identifier stores 4.

When a packet is processed "wake-up" signals are sent to any packets whose identifiers appear in its signal list field 16. When an asleep packet has received the required number of "wake-up" signals then its status field 14 is set to indicate that it is now "awake" and available for processing. Its identifier is then put into one of the identifier stores 4a, 4b, etc. by the processor responsible for sending the final "wake-up" signal or by one of the packet store controllers 8a, 8b, etc.

Sometimes a packet may no longer be required although it is still held in store 1. Such a packet is colloquially termed "garbage". Field 15, the reference count field of a packet, indicates how many other packets refer to that packet as data, that is to say how many times its identifier appears in the argument list of other packets. The reference counts are adjusted as the processing of packets modifies their references to other packets. Such adjustment may be carried out by the segment controller 8a or 8b, etc. associated with the segment in store 1 where a packet which requires its reference count field to be adjusted is held.

When the reference count of any packet becomes zero, that packet has become garbage and its store location may be re-used. This is achieved by an operation termed "garbage collection" whereby a processor is used to place the identifiers of such packets in an identifier store 5a, 5b, etc. indicating that these locations are now available for new packets. This process of garbage collection can take place in parallel with other operations.

While in general it may be desirable that all processing units carry out all functions that can be carried out in the machine, it is possible to provide that processing units are limited or dedicated to specific or a limited number of functions. In particular, one or more processing units can include input and output arrangements.

There is no inherent limit to the size of a computer constructed as described with reference to FIG. 1. To increase the size of the computer all that is required is to increase the number of processing units and likewise the number of identifier stores in the two respective groups. Similarly, additional segments may be required in store 1. If desired, however, it is possible to arrange a computer embodying the invention in hierarchical form. Such an arrangement comprises a plurality of blocks each block corresponding to a computer illustrated in FIG. 1. The blocks need to be interconnected in two ways. Firstly, all the packet stores (stores 1) need to act as a single addressable store. An interconnecting network, which may be a crossbar-type switching mechanism or the equivalent, is required to which all the packet stores are connected. Additionally, corresponding groups of identifier stores in the individual blocks need to be interconnected to enable transfer of indentifiers from one corresponding group to another in different blocks.

A computer as described above is particularly suited to a wide variety of programming languages that express programs as a set of rules for rewriting expressions, although it is equally possible to execute programs written in more conventional languages of the kind conforming to the von Neumann architecture of computers.

In the above description the identifiers constitute the addresses of the packets in the packet store. However this is not essential and it is possible for the identifiers to be digital values other than addresses which uniquely identify packets, in which case an appropriate mechanism is required for locating an identified packet in the packet store.