Compensation Circuit and Method for Stabilization of a Circuit Node by Multiplication of Displacement Current

The present invention relates, in general, to the field of compensating circuits and methods for stabilization of a circuit node in an integrated circuit by multiplication of junction capacitance displacement current. More particularly, the present invention relates to a compensation circuit and method which multiplies junction capacitance displacement current to provide stabilization of a sensitive circuit node which might otherwise oscillate due to capacitive coupling of the substrate when used as an output in certain integrated circuit technologies.

In the utilization of an N type epitaxial layer or well in conjunction with a P+ substrate and isolation regions, a diode exists at the junctions between the epitaxial layer and the substrate/isolation regions. Moreover, these junctions exhibit an associated parasitic capacitance, or junction capacitance.

This junction capacitance can create problems with many newer technology integrated circuits which take advantage of large output devices utilizing the substrate as an output terminal. Exemplary of such new devices are power vertical PNPs as well as bottom collector NPNs and CMOS/TMOS.TM. devices. These new technologies are currently being developed by numerous semiconductor manufacturers, including Motorola Inc., assignee of the present invention and owner of the trademark TMOS.

In the utilization of such "bottom technology" devices, when the output, taken at the substrate, swings rapidly, large displacement currents may flow through the parasitic capacitance associated with the junction isolation. Such circuits may therefore become extremely susceptible to this capacitive current. In such instances, the output of the device, rather than turning off at the appropriate time may oscillate between the supply voltage level, V.sub.CC and circuit ground due to induced displacement current at a sensitive circuit node in the device control circuitry.

It is therefore an object of the present invention to provide an improved compensation circuit and method for stabilization of a circuit node by multiplication of displacement current.

It is further an object of the present invention to provide an improved compensation circuit and method for stabilization of a circuit node by multiplication of displacement current which provides stabilization to an integrated circuit output which might otherwise oscillate due to capacitive coupling of the substrate to the circuit node.

It is still further an object of the present invention to provide an improved compensation circuit and method for stabilization of a circuit node by multiplication of displacement current which is readily integrated and implemented utilizing a minimum of on-chip area.

The foregoing and other objects are achieved in the present invention wherein there is provided a compensation circuit and method for stabilization of a circuit node coupled to an integrated circuit substrate by a parasitic capacitance having a value C.sub.1 and having a displacement current to the substrate substantially equal to C.sub.1 dv/dt. The compensation circuit includes a switching device having a gain beta (.beta.) and first, second and third terminals thereof, the first terminal being coupled to a supply voltage line, the second terminal being coupled to the substrate by a parasitic capacitance of a value C.sub.2 and the third terminal thereof being connected to the circuit node. In operation, the switching device supplies a current to the circuit node substantially equal to C.sub.2 .beta. dv/dt which is greater than the displacement current. Alternative embodiments of the compensation circuit and method of the present invention include a diode having anode and cathode terminals thereof, the cathode terminal being coupled to the supply voltage line and the anode terminal being connected to the second terminal of the switching device. In some applications, the diode may comprise an NPN bipolar transistor.

In accordance with an alternative embodiment of the present invention a compensation circuit and method is provided which includes a switching device having a gain beta and first, second and third terminals thereof, the first terminal being coupled to a circuit node and the second and third terminals being coupled to the substrate by a parasitic capacitance of a value C.sub.2. A diode having anode and cathode terminals thereof has its cathode terminal coupled to a supply voltage line and its anode connected to the second and third terminals of the switching device. In this embodiment, incorporating an inverted phase, the switching device draws a current from a circuit node substantially equal to C.sub.2 .beta. dv/dt which is greater than the displacement current.

The above-mentioned, and other features and objects of the present invention and the manner of attaining them will become more apparent and the invention itself will be best understood by reference to the following description of an embodiment of the invention taken in conjunction with the accompanying drawings, wherein:

FIG. 1 is a simplified cross sectional view of a portion of a prior art integrated circuit useful in illustrating the parasitic capacitances inherent at the substrate and isolation region junctions with an epitaxial layer, and illustrating a vertical PNP transistor;

FIG. 2 is a generalized schematic and block diagram representation of a portion of a prior art power BIMOS circuit useful in illustrating the displacement current from a circuit node due to the parasitic capacitances shown in FIG. 1 which might result in oscillation of V.sub.OUT ;

FIG. 3 is an extension of the generalized schematic and block diagram representation of FIG. 2 utilizing a compensation circuit in accordance with the present invention and illustrating the use of a PNP transistor as a switching device of gain beta to stabilize a circuit node from the displacement current shown in FIG. 2.

FIG. 4 illustrates an alternative embodiment of the compensation circuit of FIG. 3 utilizing a split collector PNP transistor to control the device beta by ratioing the collector areas, as well as a shunt diode to provide a low impedance AC signal path under forward biased conditions; and

FIGS. 5A and 5B illustrate schematically, and by device layout, a further embodiment of the compensation circuit of FIG. 3 which operates with inverted phase to a different circuit node with respect to the embodiments above described and may be merged into a very compact two-terminal element .

Referring now to FIG. 1, a portion of a prior art integrated circuit 10 is shown. Integrated circuit 10 comprises, in major part, a P+ substrate 12 having N epitaxial layers 14, 16 separated by an isolation region 18. A vertical PNP transistor comprising P region 20, N epitaxial layer 16 and P+ substrate 12 is also shown. At the junction of, for example, N epitaxial layer 14 with P+ substrate 12 and the P+ isolation region 18, normally reverse biased diodes exist between the N and P+ materials. Moreover, an inherent parasitic capacitance also exists at these junctures. In the utilization of such vertical PNP transistors 22, when the substrate is utilized as V.sub.OUT, large displacement currents may flow through the capacitances associated with the junction capacitance.

Referring additionally now to FIG. 2, a BIMOS circuit 30 is shown which is useful in illustrating the displacement current from a circuit node due to the parasitic capacitances shown in FIG. 1 which might result in oscillation of V.sub.OUT. BIMOS circuit 30 comprises, in general, vertical PNP transistor 22 coupled between a supply voltage line, V.sub.CC and the device substrate utilized as V.sub.OUT. The base terminal of vertical PNP transistor 22 is connected to the output of a control circuit 30 having as input the collector terminal of PNP transistor 32. The emitter of PNP transistor 32 is also connected to V.sub.CC. Likewise, the base terminal of PNP transistor 32 is connected to V.sub.CC by resistor 36, and the base terminal of PNP transistor 32 defines a sensitive circuit node 40 at the epitaxial layer of the integrated circuit. Node 40 is connected to the drain of MOSFET 34 having its source connected to circuit ground. The gate terminal of MOSFET 34 is connected to V.sub.IN.

In operation, BIMOS circuit 30 functions such that when V.sub.IN is at a logic high level, MOSFET 34 turns on thus turning PNP transistor 32 on. When this happens, vertical PNP transistor 22 is saturated. When V.sub.IN is at a logic low level, MOSFET 34 turns off, thereby turning off PNP transistor 32 and, hence, vertical PNP transistor 22. At this time, the substrate begins to fall but a displacement current in the junction capacitance may turn PNP transistor 32 back on if the displacement current, C.sub.1 dv/dt through resistor 36 creates a voltage greater than the V.sub.BE of PNP transistor 32. In this instance, V.sub.OUT rather than turning off, may oscillate between V.sub.CC and ground. Such oscillation problems may be particularly noticeable with high impedance nodes where the output changes voltage very rapidly. In such instances, even more current may be pulled out of node 40 with the resultant oscillation of V.sub.OUT above described. It should be noted, that a parasitic capacitance exists between the substrate and every epitaxial region in the circuit, including those within control circuit 38 such that a displacement current develops each time the substrate moves with respect to V.sub.CC. While this phenomena has been shown with respect to node 40 only, it should be remembered that there exists a number of places within an integrated circuit where such displacement current may create a problem. For example, other areas of concern would include epitaxial tubs which are pulled down containing an MOS transistor and resistors which provide positive feedback to V.sub.OUT.

Referring additionally to FIG. 3 an expanded schematic of BIMOS circuit 30 is shown utilizing a compensation circuit in accordance with the present invention. In this embodiment, the compensation circuit comprises PNP transistor 42 functioning as a switching device of gain beta. PNP transistor 42 has its emitter connected to V.sub.CC and its collector connected to node 40. The base of PNP transistor 42 is the epitaxial layer of the integrated circuit itself and exhibits a parasitic capacitance to the substrate of C.sub.2. Thus, a displacement current of C.sub.2 dv/dt on the base of PNP transistor 42 would correspond to a collector current to node 40 of C.sub.2 .beta. dv/dt. Thus, the current supplied to node 40 is C.sub.2 .beta. dv/dt while the displacement current due to the capacitance between the base of PNP transistor 32 is C.sub.1 dv/dt. Resultantly, if C.sub.1 =C.sub.2, .beta. times more current will be placed into node 40 by PNP transistor 42 than is pulled out of node 40 by the parasitic capacitance C.sub.1 when the substrate voltage drops.

It should be noted, that while the compensation circuit of the present invention shows the current being injected into node 40, in many applications the compensation could be applied to a master shutdown point in the control circuit.

Referring additionally now to FIG. 4, a compensation circuit 50 is shown which may be utilized in place of the compensation circuit of FIG. 3 comprising PNP transistor 42. Compensation circuit 50 comprises in major part a split collector PNP transistor 44 functioning as a switching device of gain beta. The beta of split collector PNP transistor 44 is effectively the ratio of the areas of collectors A.sub.1 /A.sub.2. The emitter of split collector PNP transistor 44 is connected to V.sub.CC and collector A.sub.1 is connected to node 40. Collector A.sub.2 is connected to the base of split collector PNP transistor 44 which is the N epitaxial layer of the integrated circuit.

A diode 46 couples the base of split collector PNP transistor 44 to V.sub.CC. In the embodiment illustrated, diode 46 comprises an NPN transistor having its emitter connected to V.sub.CC and its base and collector terminals common connected to the base of split collector PNP transistor 44. Compensation circuit 50 has associated therewith a parasitic capacitance C.sub.2 to the substrate.

Compensation circuit 50 has advantages with respect to the compensation circuit of FIG. 3 in that should the substrate swing negative and pull current through the capacitance C.sub.2 it will charge that capacitance from positive to negative as current through the base emitter junction of PNP transistor 42 of FIG. 3 or split collector PNP transistor 44 of FIG. 4. However, when the substrate goes back up to V.sub.CC, there is no way for capacitor C.sub.2 to discharge in that a reverse bias diode is found in the base emitter of PNP transistor 42 or split collector PNP transistor 44. Thus, the charge stored on the capacitor will remain and no current will flow. Resultantly, on the next transition of the substrate, C.sub.2 is already charged. In order to discharge this capacitance a high value resistance could be placed on the base of either PNP transistor 42 or split collector PNP transistor 44 and tied to AC ground (V.sub.CC). Therefore, when the substrate moves positively towards V.sub.CC the capacitance C.sub.2 can discharge through the resistor. However, a disadvantage in the utilization of a resistor is that it must be quite large in value, and for that reason, current will be lost through it when the substrate transitions negatively. Therefore, diode 46 is utilized with split collector PNP transistor 44 in compensation circuit 50 and may likewise be utilized in conjunction with PNP transistor 42 of FIG. 3. Diode 46 provides a complete AC path for current to discharge capacitance C.sub.2. Diode 46 becomes reverse biased such that all of the current that flows into capacitor C.sub.2 as the substrate goes negative has to come through the base of split collector PNP transistor 44. On the other hand, when the substrate moves positively, current can flow through diode 46 to V.sub.CC. However, there could be leakage at the base of split collector PNP transistor 44, e.g. leakage of the diode forming C.sub.2 to the substrate. Thus, collector A.sub.2 is tied back to the anode of diode 46. Were this not done, the leakage current could appear as base current for split collector PNP transistor 44 and it would get multiplied by the gain of the device and would leak into the circuitry. This is, therefore, effectively controlled by tying collector A.sub.2 back to the base, which is the epitaxial layer, to effectively control the beta of the device. As above described, the beta of split collector PNP transistor 44 is effectively A.sub.1 /A.sub.2.

Referring additionally now to FIGS. 5A and 5B, an alternative embodiment for compensation circuit 50 is likewise shown. In this embodiment, compensation circuit 50 comprises split collector PNP transistor 44 having its emitter connected to node 60 requiring inverted phase to compensate for displacement current instead of V.sub.CC as shown in FIG. 4. Additionally, collector A.sub.1 is connected directly to substrate. All remaining connections of compensation circuit 50 are as previously described with respect to FIG. 4.

Utilizing the embodiments of compensation circuit 50 shown in FIGS. 5A and 5B the collector split of split collector PNP transistor 44 allows the gain of the device to be controlled by the ratio of the two collector areas as above described. This current gain control allows for the adjustment of injected current as well as leakage current. However, as above described, the embodiment of compensation circuit 50 shown in FIGS. 5A and 5B depicts an embodiment of the invention which operates with inverted phase with respect to the embodiment of FIG. 4. Thus, current will be pulled from node 60 to prevent inadvertent turn-on of a circuit where inverted phase is necessary. Utilizing this embodiment, a compact two-terminal network may be provided which takes up very little on-chip space as shown.

What has been provided therefore is an improved compensation circuit and method for stabilization of a circuit node by multiplication of displacement current which provides stabilization to an integrated circuit output which might otherwise oscillate due to capacitive coupling of the substrate to the voltage node. The compensation circuit and method of the present invention is readily integrated and utilizes a minimum of on-chip area.

While there have been described above the principles of the invention in conjunction with specific apparatus, it is to be clearly understood that these descriptions are made only by way of example and not as a limitation to the scope of the invention.