Digitalized Position Control for a D.C. Motor

The present invention relates to a position control system in a D.C. motor.

In order to precisely control the position in a D.C. motor, the D.C. motor is generally controlled in two modes. The first mode is the speed detection mode wherein the rotating speed of the motor is controlled so that the motor rotates to a desired position at a fast speed. The second mode is the position detection mode, which is conducted after the completion of the speed detection mode. In the position detection mode, the motor position is precisely controlled so that the motor stops at the desired position.

In the conventional system, the speed detection mode and the position detection mode are controlled in the analog fashion. Therefore, the conventional system is not suited for the LSI technique. Furthermore, in the conventional system, the motor speed control in the speed detection mode is conducted by the frequency control method. The frequency control method inevitably produces the steady-state deviation between the instructed rotating speed and the actual rotating speed of the D.C. motor. The steady-state deviation varies depending on the load connected to the D.C. motors. Thus, the conventional system can not ensure a stable oeration when the load connected to the D.C. motor varies.

Accordingly, an object of the present invention is to digitalize a control circuit for a position control system in a D.C. motor.

Another object of the present invention is to provide a D.C. motor position control system which precisely controls the position of the D.C. motor and stops the D.C. motor at a desired position.

Still another object of the present invention is to provide a D.C. motor position control system which ensures a stable operation even when the load connected to the D.C. motor varies.

Other objects and further scope of applicability of the present invention will become apparent from the detailed description given hereinafter. It should be understood, however, that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.

To achieve the above objects, pursuant to an embodiment of the present invention, a rotary encoder is associated with a D.C. motor so as to develop an approximate sinusoidal position indicating, analog signal in response to the rotation of the D.C. motor. The approximate sinusoidal position indicating, analog signal is introduced into a slice level determination circuit which develops two sliced position indicating, digital signals to a main control circuit. The following system is digitally controlled with reference to the sliced position indicating, digital signals.

In a preferred form, a phase-locked-loop (PLL) control is employed in the speed detection mode. The phase-locked-loop (PLL) control does not produce the steady-state deviation between the actual rotating speed of the D.C. motor and the instructed speed. Therefore, an accurate speed control is achieved even when the load connected to the D.C. motor varies.

The present invention will be better understood from the detailed description given hereinbelow and the accompanying drawings which are given by way of illustration only, and thus are not limitative of the present invention and wherein:

FIG. 1 is a block diagram of a D.C. motor position control system of the prior art;

FIGS. 2(A) and 2(B) are charts for explaining an operational mode of the conventional control system of FIG. 1;

FIG. 3 is block diagram of an embodiment of a D.C. motor position control system of the present invention;

FIG. 4 is a waveform chart showing various signals occurring within the embodiment of FIG. 3;

FIG. 5 is a block diagram of a slice level determination circuit included in the embodiment of FIG. 3;

FIG. 6 is a block diagram of an essential part of an arithmetic and logic unit included in the embodiment of FIG. 3;

FIGS. 7(A) and 7(B) are waveform charts showing signals occurring within the arithmetic and logic unit of FIG. 6;

FIG. 7(C) is a logic table for explaining an operational mode of the arithmetic and logic unit of FIG. 6;

FIG. 8 is a block diagram of another embodiment of a D.C. motor position control system of the present invention;

FIG. 9 is a waveform chart showing various signals occurring within still another embodiment of a D.C. motor position control system of the present invention;

FIG. 10 is a waveform chart for explaining yet another embodiment of a D.C. motor position control system of the present invention; and

FIG. 11 is a block diagram of a further embodiment of a D.C. motor position control system of the present invention.

In order to facilitate a complete understanding of the present invention, the conventional D.C. motor position control system will be first described with reference to FIG. 1.

The D.C. motor position control system generally operates in the speed detection mode, wherein the motor speed is controlled, and the position detection mode, wherein the D.C. motor position is accurately controlled so as to hold the D.C. motor at the target position. The speed detection mode ensures a high speed rotation of the D.C. motor, and the position detection mode ensures a precise positioning of the D.C. motor.

The conventional D.C. motor position control system includes a main control circuit 10, implemented by a microprocessor, which develops a speed instruction, digital signal D.sub.COM to a digital-to-analog converter 12. A rotary encoder 14 is associated with a D.C. motor 16 so as to develop an approximate sinusoidal position indicating, analog signal A', B' in response to the rotation of the D.C. motor 16. The approximate sinusoidal position indicating, analog signal A', B' is applied to a waveform shaping circuit 18 which functions to digitalize the approximate sinusoidal position indicating, analog signal A', B' so as to obtain a rectangular position indicating, digital signal A, B. The thus obtained rectangular position indicating, digital signal A, B is applied to the main control circuit 10. The main control circuit 10 calculates the system speed in accordance with the rectangular position indicating, digital signal A, B to update the speed instruction, digital signal D.sub.COM of predetermined bits. The digital-to-analog converter 12 develops a speed instruction, analog signal A.sub.COM to an error amplifier 20. The approximate sinusoidal position indicating, analog signal A', B' is further applied to a speed detection circuit 22, which develops a speed indicating, analog signal A.sub.V in accordance with the frequency of the approximate sinusoidal position indicating, analog signal A', B'. The speed indicating, analog signal A.sub.V functions as a feedback signal, and is applied to one input terminal of the error amplifier 20. The error amplifier 20 develops an analog error signal A.sub.ER to a pulse width modulation (PWM) circuit 24, which applies a control signal to a motor drive circuit 26.

Now assume that the D.C. motor 16 is in the stationary condition, and an instruction is applied to the system to place the D.C. motor 16 at a desired position. The system first operates in the open-loop mode because the feedback signal is not applied from the speed detection circuit 22 at the initial state. Accordingly, the motor drive circuit 26 supplies the maximum current to the D.C. motor 16 (see FIGS. 2(A) and 2(B), from T1 to T2). When the rotating speed of the D.C. motor 16 reaches the maximum speed at the time T2, the system functions to cut the speed instruction signal D.sub.COM (A.sub.COM) from the main control circuit 10 so as to reduce the accelerating torque. Therefore, the D.C. motor 16 is controlled in the closed-loop mode so that the D.C. motor 16 continues to rotate at the maximum speed.

When the current position of the D.C. motor 16 becomes near the target position, the main control circuit 10 reduces the speed value of the speed instruction signal D.sub.COM (A.sub.COM) (T3 in FIGS. 2(A) and 2(B)). The motor drive circuit 26 supplies the current of the opposite direction to the D.C. motor 16 in order to brake the D.C. motor 16. The braking force is progressively applied to the D.C. motor 16, and the D.C. motor 16 reaches the minimum speed (T4 in FIGS. 2(A) and 2(B)).

Thereafter, the system operation is shifted to the position detection mode in order to precisely position the D.C. motor 16 at the target position. In the position detection mode, the zero cross point of the approximate sinusoidal position indicating, analog signal A' (or B') is utilized to control the system operation. More specifically, the approximate sinusoidal position indicating, analog signal A' (or B') is introduced into the error amplifier 20 so as to form a high-gain feedback loop in connection with the position of the D.C. motor 16. The D.C. motor 16 holds the desired position by means of the electrical detent force thereof.

As discussed above, in the conventional system, the position control is conducted in an analog fashion. That is, the approximate sinusoidal position indicating, analog signal A' (or B') is applied to the error amplifier 20 in the position detection mode to precisely control the position of the D.C. motor 16.

Furthermore, the motor speed in the speed detection mode is controlled by the frequency control method. That is, the two approximate sinusoidal position indicating, analog signal A' and B' (which have the phase difference of 90.degree. from each other) is applied to the speed detection circuit 22. The speed detection circuit 22 develops the speed indicating, analog signal A.sub.V to the error amplifier 20. The rotating speed of the D.C. motor 16 is controlled by comparing the voltage level of the speed indicating, analog signal A.sub.V and the speed instructing, analog signal A.sub.COM at the error amplifier 20.

The pulse width modulation (PWM) circuit 24 is interposed between the error amplifier 20 and the motor drive circuit 26 so as to convert the analog error signal A.sub.ER into the pulse signal, thereby minimizing the power loss at the motor drive circuit 26.

The frequency control method of the prior art inevitably produces the steady-state deviation between the instructed motor speed and the actual rotating speed of the D.C. motor. The steady-state deviation varies depending on the load connected to the motor. Therefore, the conventional system can not ensure a stable operation when the load connected to the motor varies.

FIG. 3 shows an embodiment of the D.C. motor position control system of the present invention. Like elements corresponding to those of FIG. 1 are indicated by like numerals. The control system of the present invention operates in a digital manner both in the speed detection mode and in the position detection mode.

A main control circuit 30, implemented with a microprocessor, receives the rectangular position indicating, digital signal A, B from the waveform shaping circuit 18, and a sliced position indicating, digital signal E, F from a slice level determination circuit 32. The construction of the slice level determination circuit 32 will be described later with reference to FIG. 5. The main control circuit 30 develops the speed instruction, digital signal D.sub.COM, which is applied to an arithmetic and logic unit (ALU) 34. An essential part of the arithmetic and logic unit (ALU) 34 will be described later in detail with reference to FIG. 6. The rectangular position indicating, digital signal A, B developed from the waveform shaping circuit 18 is further applied to a speed monitoring circuit 36. The speed monitoring circuit 36 detects the period of the rectangular position indicating, digital signal A, B in a digital fashion, and develops a speed indicating, digital code signal D.sub.V.

In the speed detection mode, the speed instruction, digital signal D.sub.COM and the speed indicating, digital code signal D.sub.V are applied to the arithmetic and logic unit (ALU) 34. The arithmetic and logic unit (ALU) 34 compares the two signals, and develops a digitally coded error signal D.sub.ER. The digitally coded error signal D.sub.ER is applied to the motor drive circuit 26 via a pulse width modulation (PWM) circuit 38. The pulse width modulation (PWM) circuit 38 operates as an interface functioning to vary the duty cycle of the drive signal to be applied to the D.C. motor drive circuit 26 in response to the digitally coded error signal D.sub.ER.

When the motor position becomes close to the target position, the operation is changed to the position detection mode. In the position detection mode, the sliced position indicating, digital signal E, F is applied to the main control circuit 30, and the arithmetic and logic unit (ALU) 34 to control the system operation. FIG. 34 shows the relationship between the approximate sinusoidal position indicating, analog signal A', B', the rectangular position indicating, digital signal A, B, and the sliced position indicating, digital signal E, F. The sliced position indicating, digital signal E, F is obtained by detecting the voltage level of one of the approximate sinusoidal position indicating, analog signal A' and B'. In this example, the approximate sinusoidal position indicating, analog signal A' is used because the target position P is determined by the approximate sinusoidal position indicating, analog signal A'. The sliced position indicating, digital signal E, F have the phase difference from each other so that the direction of the motor rotation can be detected in the position detection mode by monitoring the sliced position indicating, digital signal E, F. FIG. 5 shows an example of the slice level determination circuit 32. The approximate sinusoidal position indicating, analog signal A' is introduced into an amplifier 320. An output signal of the amplifier 320 is introduced into 15 (fifteen) voltage comparators 322-1 through 322-15 in a parallel fashion. The first voltage comparator 322-1 receives a first reference voltage V.sub.7. The second voltage comparator 322-2 receives a second reference voltage V.sub.6. In a same manner the last voltage comparator 322-15 receives a fifteenth reference voltage -V.sub.7. That is, the voltage level of the approximate sinusoidal position indicating, analog signal A' is detected by the 15 (fifteen) voltage comparators 322-1 through 322-15, and the voltage level is divided into 16 (sixteen) levels. That is, the first voltage comparator 322-1 detects whether the voltage level of the output signal of the amplifier 320 is higher than the first reference voltage V.sub.7. The second voltage comparator 322-2 detects whether the voltage level of the output signal of the amplifier 320 is higher than the second reference voltage V.sub.6. Similarly, the last voltage comparator 322-15 detects whether the voltage level of the output signal of the amplifier 320 is higher than the last reference voltage -V.sub.7. Detection outputs of the first and third voltage comparators 322-1 and 322-3 are applied to a first exclusive-OR gate 324-1. The detection outputs of the second and fourth voltage comparators 322-2 and 322-4 are applied to a second excusive-OR gate 324-2. Similarly, detection outputs of the thirteenth and fifteenth voltage comparators 322-13 and 322-15 are applied to a seventh exclusive-OR gate 324-7. The output signal of the fourteenth voltage comparator 322-14 is applied to one input terminal of the last exclusive OR gate 324-8. The other input terminal of the last exclusive-OR gate 324-8 receives a signal which always bears the logic high. A first OR gate 326-1 receives output signals of the odd-number exclusive OR gates 324-1, 324-3, 324-5 and 324-7. An output signal of the first OR gate 326-1 operates as the sliced position indicating, digital signal E. A second OR gate 326-2 receives output signals of the even-number exclusive-OR gates 324-2, 324-4, 324-6 and 324-8. An output signal of the second OR gate 326-2 functions as the sliced position indicating, digital signal F.

The thus formed sliced position indicating, digital signal E, F is introduced into the arithmetic and logic unit (ALU) 34 in the position detection mode. The arithmetic and logic unit (ALU) 34 counts (up/down) the sliced position indicating, digital signal E, F to determine the separation of the current motor position from the target position P. In accordance with the degree of the separation, the returning force to the target position P is controlled.

FIG. 6 shows an essential part of the arithmetic and logic unit (ALU) 34 in the position detection mode. Like elements corresponding to those of FIG. 3 are indicated by like numerals.

The arithmetic and logic unit (ALU) 34 includes an up/down counter 340. The up/down counter 340 is the two-bits construction, and receives the sliced position indicating, digital signal E, F in order to determine the position of the D.C. motor 16 and the rotating direction of the D.C. motor 16. The up/down count operation is controlled by checking the phase relationship between the sliced position indicating, digital signal E, F. The count operation is conducted in response to the trailing edge of the sliced position indicating, digital signal F. The count output is two bits construction (a.sub.1 and a.sub.2) as shows in FIG. 7(C). The count output a.sub.1, a.sub.2 is applied to a sliced position detection circuit 342 which also receives the sliced position indicating, digital signal E, F. The sliced position detection circuit 342 develops a control signal to the pulse width modulation (PWM) circuit 38 for stopping the rotation of the D.C. motor 16 under the following logic condition.

(1) The count output a.sub.1, a.sub.2 of the up/down counter 340 is (0, 1), and the logic value of the sliced position indicating, digital signal E, F is (0, 0),

or

(2) The count output a.sub.1, a.sub.2 of the up/down counter 340 is (1, 0), and the logic value of the sliced position indicating, digital signal E, F is (0, 1).

It will be clear from FIGS. 7(A) through 7(C) that the returning force is controllable with different eight degrees in the positive and negative directions, respectively. In this way, the D.C. motor 16 is precisely stopped at the target position P.

FIG. 8 shows another embodiment of a D.C. motor position control system of the present invention, wherein the motor speed control in the speed detection mode is achieved by the phase-locked-loop (PLL) control. The position control in the position detection mode is conducted in a same manner as the embodiment of FIG. 3. Like elements corresponding to those of FIG. 3 are indicated by like numerals.

A main control circuit 40, implemented with a microprocessor, receives the rectangular position indicating, digital signal A, B from the waveform shaping circuit 18, and develops a speed instructing pulse signal S with a predetermined period (frequency) in accordance with the position information derived from the rectangular position indicating, digital signal A, B. A phase comparator 42 compares the phase of the speed instructing pulse signal S with the phase of the rectangular position indicating, digital signal A or B. The phase comparator 42 develops a phase difference signal D.sub.P (digital code signal) in accordance with the phase difference between the speed instructing pulse signal S and the rectangular position indicating, digital signal A or B. The phase difference signal D.sub.P is applied to an arithmetic and logic unit (ALU) 44, which develops the digitally coded error signal D.sub.ER in accordance with the phase difference signal D.sub.P. The following operation is similar to that described with reference to FIG. 3. That is, in the embodiment of FIG. 8, the motor speed control in the speed detection mode is achieved in the phase-locked-loop (PLL) manner, wherein the phase of the rectangular position indicating, digital signal A or B is compared with the phase of the speed instructing pulse signal S. The PLL control never produces the steady-state deviation between the actual speed of the D.C. motor 16 and the instructed motor speed.

Although in the embodiment of FIG. 8 the rectangular position indicating, digital signal A or B is used to perform the PLL control, the PLL control can be performed through the use of the sliced position indicating digital signal E.

The sliced position indicating, digital signal F is not suited for the PLL control because the sliced position indicating, digital signal F has a different pulse width at the peak of the approximate sinusoidal position indicating, analog signal A'. FIG. 9 shows another sliced position indicating, digital signal G which is obtained from the approximate sinusoidal position indicating, analog signal B'. The sliced position indicating, digital signal G is effective to perform the PLL control in the speed detection mode. The sliced position indicating, digital signal G can be formed by a slice level determination circuit having a similar construction as the slice level determination circuit 32 shown in FIG. 5, but having an input terminal receiving the approximate sinusoidal position indicating, analog signal B'.

The reference voltages V.sub.7 through --V.sub.7 should not be fixed to the foregoing embodiments. FIG. 10 shows another example of the relationship between the voltage level of the approximate sinusoidal position indicating, analog signal A' and the levels of the reference voltages V.sub.7 through -V.sub.7 which are applied to the voltage comparators 322-1 through 322-15 in the slice level determination circuit 32 shown in FIG. 5. By selecting the reference voltages V.sub.7 through -V.sub.7 as shown in FIG. 10, a further accurate control is ensured because the slice interval becomes short near the target position P. Moreover, the counting operation is ensured because the sliced position indicating, digital signal E, F does not change the logic value near the peak position of the approximate sinusoidal position indicating, analog signal A'. Furthermore, the system operation is ensured because an initializing period can be provided near the peak position of the approximate sinusoidal position indicating, analog signal A'.

FIG. 11 shows a further embodiment of a D.C. motor position control system of the present invention. Like elements corresponding to those of FIG. 8 are indicated by like numerals.

In this embodiment, the sliced position indicating, digital signal E, G is used to control the system operation. The embodiment of FIG. 11 includes a switching element 50 for selectively applying the rectangular position indicating, digital signal A, B and the sliced position indicating, digital signal E, G to the phase comparator 42 in the speed detection mode. A main control circuit 52 develops a first control signal in the speed detection mode in order to supply the rectangular position indicating, digital signal A or B when the motor rotates at a fast speed. The main control circuit 52 develops a second control signal in the speed detection mode in order to supply the sliced position indicating, digital signal E or G when the motor rotates at a lower speed.

The invention being thus described, it will be obvious that the same may be varied in many ways. Such variations are not to be regarded as a departure from the spirit and acope of the invention, and all such modifications are intended to be included within the scope of the following claims.