Tape Address Synchronizing Apparatus for Video Tape Recorder

The present invention relates to a tape address synchronizing apparatus for a video tape recorder (VTR) which equalizes a tape address of the VTR with that of another video tape recorder or with a reference.

Such tape address synchronizing operation is necessary for editing a video program, for example. When the video program is edited into a recording VTR by receiving the video program from a playing VTR, both the recording VTR and the playing VTR rewind their magnetic tape by a predetermined time (pre-roll time) from a certain edit point, first, and, then, both the VTRs turn on in the normal direction. After this, the editing starts at the edit point. However, the edit point in both the VTRs, i.e., the recording VTR and the playing VTR, frequently does not coincide with the tape address synchronizing operation because of a difference in pre-roll times actually set up into the recording VTR and the playing VTR and a difference in mechanical characteristics of the two VTRs. The tape address synchronizing operation equalizes the tape address, i.e., the edit point during the pre-roll time. One method of the tape address synchronizing operation is that a tape address of either the recording VTR or the playing VTR is employed as a reference, and the reference is transmitted to the other VTR which controls its tape speed in order to lock-in with the reference. Another method is that an external reference is applied to both the recording VTR and the playing VTR and the two VTRs control their tape speed in order to lock-in with the external reference. The following description is based on the latter method.

In a prior art tape address synchronizing apparatus for a VTR, a reference address generation circuit, which can be loaded with a preset address, produces a reference address in accordance with an external reference, and the reference address is compared with a tape address which is produced in response to actual tape transportation. The result from the comparison is fed into a capstan servo circuit and a feedback arrangement is used to ensure that the comparison result is driven to zero. In addition, the capstan servo circuit also controls a capstan motor to cause a control track (CTL) signal, which is recorded on a control track of a magnetic tape, coincide with the external reference. Accordingly, after the capstan servo circuit has operated so that there is no difference between the reference address and the tape address, it also makes the CTL signal coincident with the reference. However, since the servo response due to comparing the addresses is independent of the response based on comparing the CTL signal with the reference, the address difference is often changed after the servo operation which aligns the CTL signal with the reference. In such case, both servo operations must be repeated. In consequence the tape address synchronizing operation cannot be completed during the pre-roll time. As a result, accurate editing cannot be accomplished.

It is an object of the present invention to provide a tape address synchronizing apparatus for a VTR which can complete a precise tape address synchronizing operation during the pre-roll time period of synchronization step.

According to the present invention, there is provided a tape address synchronizing apparatus comprising an address comparator which compares a reference address with a tape address generated on the basis of actual tape transportation, and a phase detector means which can perform a comparison in 1/4 frame resolusion therewith, whereby a complete tape address synchronizing operation is completed during a predetermined time by making the servo lock-in range for comparing the addresses coincident with the servo lock-in range for comparing the CTL signal with the reference.

FIG. 1 is a schematic illustration of a prior art tape address synchronizing apparatus for a VTR;

FIG. 2 schematically shows one embodiment of the present invention;

FIG. 3 shows construction of a phase comparator of FIG. 2;

FIG. 4 is a timing chart indicating a tape address synchronizing operation according to the present invention; and

FIG. 5 shows a second embodiment of the present invention.

The prior art will now be described with reference to FIG. 1. Two timer pulses .phi..sub.1, .phi..sub.2 each having a different phase of 90.degree. are obtained from a tape timer roller 2. These pulses vary according to the movement of a magnetic tape 1. A tape timer circuit 3 detects the direction of movement of the magnetic tape 1 and produces a tape address for each frame by continuing these pulses. The tape address delivered from the tape timer circuit 3 is applied to an address comparator 4. Simultaneously, a control track (CTL) signal for each frame, which is recorded on a control track of the magnetic tape 1 is picked up by a readout head 5, is shaped by a shaping circuit 6, and is sent to the tape timer circuit 3 as a correction signal. A reference address generation circuit 7 is constructed of a counter which updates an address according to an external reference signal S.sub.r. It is initially loaded with a preset address A.sub.p from an external source. The updating of the reference address is started from the preset address A.sub.p by a start pulse P.sub.s, and the updated address is transmitted to an address comparator 4. The address comparator compares the address from the tape timer circuit 3 with the reference address from the reference address generation circuit 7, and, in response to the comparison result, generates an acceleration signal, a normal speed signal, or a deceleration signal. These signals are applied to a capstan servo circuit 8 to accelerate or decelerate the rotational speed of a servomotor 8a. The capstan servo circuit 8 drives the servomotor 8a so that the CTL signal from the shaping circuit 6 and the external reference signal S.sub.r are locked (actually, a signal S'.sub.r delayed from the reference signal S.sub.r by a certain value is used). However, the capstan servo circuit 8 reacts to synchronize the CTL signal with the external reference signal S.sub.r, only after it has first responded to the inputs that it receives from address comparator 4. That is, first it accelerates or decelerates to servomotor 8a to ensure that the addresses match. Later, after the tape speed has returned to normal it begins the CTL signal to external reference synchronization.

The operation of the prior art will now be further described. First, before the magnetic tape starts to move, a time reference value which is smaller than the edit point time reference by a so-called pre-roll time period is loaded into the reference address generation circuit 7. It is referred to as the preset address A.sub.p. For example, when the edit point time reference is 1 hour, 23 min., 00 sec., 00 frame and the pre-roll time is five seconds, the preset address A.sub.p is 1 hour, 22 minutes, 55 seconds, and 00 frame. When the tape transport started, the start pulse P.sub.s is input, and then the address is updated for each frame according to the reference signal S.sub.r (operating as a clock). Accordingly, when five seconds passes after the start pulse P.sub.s, the reference address becomes (1 hour, 23 minutes, 00 seconds, and 00 frame). The address comparator 4 compares the reference address with the tape address corresponding to the actual tape movement and derived from the rotation of the tape timer roller 2. When, the tape address is less than the reference address, the address comparator 4 sends the acceleration signal to the capstan servo circuit 8. In response to the acceleration signal, the capstan servo circuit 8 accelerates the servomotor 8a at a high speed, for example, 13% greater than the normal speed. Conversely, when the capstan servo circuit 8 receives the deceleration signal, the circuit 8 decelerates the servomotor 8a to a lower speed 13% less than the normal speed, for example. When the reference address coincides with the tape address, the tape speed is shifted to the normal speed according to the normal speed signal. Then the capstan servo operation based on the phase comparison between the CTL signal and the reference signal S'.sub.r is performed. As stated before, however, the lock-in operation resulting from the comparison between the reference address and the tape address is independent of the other lock-in operation preformed based upon the comparison between the CTL signal and the reference signal S.sub.r. That is, in other words, the two lock-in operations cover different lock-in tape ranges. Accordingly, when the servo is operated by the phase comparison between the CTL signal and the reference signal S.sub.r after the actual tape address is coincident with the reference address, the actual tape address frequently diverges from the reference address, again. In this instance, the tape address synchronizing operation is not completed, and precise editing cannot be achieved.

In FIG. 2 showing one embodiment of the present invention, a phase detection circuit 9 is provided between the address comparator 4 and the capstan servo circuit 8. It is different from the prior art circuit shown in FIG. 1. As shown in FIG. 3, the phase detection circuit 9 includes a comparator 10 and three gates 11, 12 and 13. An auxiliary address a from a tape timer circuit 3 is supplied to the phase detection circuit 9. The tape timer circuit 3 receives pulses having a frequency of 1920 Hz during normal tape speed from a timer roller 2. In the tape timer circuit 3, the frame timing is produced by frequency-dividing the pulses of 1920 Hz, and a tape address A is generated based thereon. The auxiliary address a comprises 2 bits and is produced by frequency-dividing the 1920 Hz pulses into 1/16 and 1/32, signals and therefore, each frame may be divided into 4 segments, i.e., (0 0), (0 1), (1 0) and (1 1), based on the 1/16 and 1/32 signals. In FIG. 3, the auxiliary address a is compared with a predetermined value .beta. (zero in this embodiment). When they are equal, an output is sent to a terminal T.sub.1 ; and when a>.beta., an output is sent to a terminal T.sub.2. The acceleration and deceleration signals from the address comparator 4 are sent to the capstan servo-drive circuit 8 directly and through an OR gate 11, respectively, and the normal speed signal is gated by an AND gate 12 to the servo-drive circuit 8. The output at the terminal T.sub.1 of the comparator 10 is supplied to the AND gate 12 for control, and AND output between the normal speed signal and the output from the terminal T.sub.2 of the comparator 10 is supplied to the OR gate 11. A AND gate 13 produces the AND output between the normal speed signal and the output from the terminal T.sub.2.

The principle of operation of the embodiment will be explained hereinafter. The magnetic tape starts to move after it has been rewound from the edit point by the pre-roll time value. First, since the tape address usually lags behind the reference address, the acceleration signal is delivered from the address comparator 4 so that the capstan rotates at a higher speed. When the tape address coincides with the reference address, the address comparator 4 delivers the normal speed signal, but because of the characteristics of the servo, the tape address leads the reference address so that the deceleration signal is then delivered from the address comparator 4. FIG. 4 is a timing chart showing the tape address synchronization. In FIG. 4, S.sub.r is the reference signal. A servo reference signal S'.sub.r, delayed by a predetermined time t.sub.1 (for example, a 1/4 frame) from the reference signal S.sub.r, is generated and the servo operates to synchronize the servo reference signal S'.sub.r with the CTL signal read out from the control track. The reference address A.sub.r is generated in accordance with the reference signal S.sub.r by the reference address generation circuit 7, and a tape address A.sub.T generated by the tape timer circuit 3 leads the reference address A.sub.r by t.sub.2 (for example, a 1/4 frame) in the synchronous coincident case. FIG. 4 shows an example in which the present invention is applied to a VTR of the SMPTE type C format. The 2 bit auxiliary address signal a indicates a resolution of a 1/4 frame, and is synchronized with the tape address A.sub.T. When the capstan servo has operated to align the servo reference signal S'.sub.r with the CTL signal, the auxiliary address a is (0 0). When the phase of the CTL signal leads that of the servo reference signal S'.sub.r, the auxiliary address becomes (0 1), (1 0) or (1 1), depending on the advance. In FIG. 4 R.sub.c is a lock-in range within which the servo reference signal S'.sub.r and the CTL signal can be locked by the capstan servo operation, and R.sub.a is a lock-in range within which the tape address A.sub.T and the reference address A.sub.r can be locked by the address comparison servo operation. The two ranges R.sub.c and R.sub.a do not coincide. Accordingly, in the prior art, even if the two addresses A.sub.T and A.sub.r match at a point P within the lock-in range R.sub.a, the capstan servo operation, in which the servo reference signal S'.sub.r and the CTL signal is phase-adjusted, can lead to an address modification, i.e., a between N and (N+1). In the present invention, when the reference address A.sub.r matches the tape address A.sub.T, the auxiliary address a is still used for address comparison in the comparator 10 (FIG. 3), and, then, the tape speed is reduced until the auxiliary address a becomes (0 0). Thus, even if the capstan servo is later activated in response to the comparison between the servo reference signal S'.sub.r and the CTL signal, a readjustment which can lead to an address mismatch between the tape address A.sub.T and the reference address A.sub.r is not possible anymore. In FIG. 4, R.sub.i is the lock-in region of the present invention within which the tape address synchronizing operation can be accurately completed. In the embodiment shown in FIG. 3, when the address comparator 4 outputs the normal speed signal and the auxiliary address a is (0 0), the tape address synchronizing operation is always completed.

In the description referring to FIGS. 3 and 4, the time delay t.sub.2 between the reference address A.sub.r and the tape address A.sub.T is considered as fixed (1/4 frame). In practice, however, this time delay t.sub.2 varies because a slip occurs between the tape timer roller 2 and the magnetic tape 1 (FIG. 2). When such slip occurs, if the phase detector circuit 9 (FIG. 2) transmits the normal speed signal to the capstan servo-drive circuit 8 under the condition of the auxiliary address a (0 0), the servo reference signal S'.sub.r and the CTL signal are not locked with each other at the same addresses of the reference address A.sub.r and the tape address A.sub.T. Therefore, a precise tape address synchronizing operation cannot be achieved. FIG. 5 shows a second embodiment of the present invention which can provide precise phase modification even when the slip occurs. The following description concentrates on the construction of a phase detection circuit 9. The second embodiment of FIG. 5 differs from that of FIG. 3 in that the value .beta., which is compared with the auxiliary address a in the comparator 10, is not fixed. In FIG. 5, the value .beta. can be selected as one of the four values (0 0), (0 1), (1 0) and (1 1). When the tape address synchronizing operation cannot be completed, that is, when the servo reference signal S'.sub.r is not locked with the CTL signal at the same addresses, the value .beta. is sequentially varied, and the tape address synchronizing operation is automatically completed. In FIG. 5, a block 14 produces the value .beta. to supply it to the comparator 10'. In the block 14, the value .beta. of (0 0) is initially set under the control of the start pulse P.sub.s, and the value .beta. is shifted to (0 1), (1 0) and (1 1) in response to the trailing edge of a normal speed signal delivered from a AND gate 15, i.e., the timing of disappearance of the normal speed signal. In FIG. 5, for example, if (0 1) is selected for value .beta., an acceleration signal is produced by an AND gate 16 and is supplied through an OR gate 17 to the capstan servo-drive circuit 8 when the auxiliary address a is (0 0). Further, a deceleration signal is produced by an AND gate 18 and is supplied through an OR gate 19 to the circuit 8 when the auxiliary address a is (1 0) or (1 1). If the tape address synchronizing operation cannot be accomplished by this, the value .beta. is changed to (1 0) and the synchronizing operation is repeated. In the present invention, even when the slip occurs between the tape timer roller 2 and the magnetic tape 1, it is always possible to determine an address point at which the servo reference signal S'.sub.r is locked with the CTL signal. As a result, precise editing can be achieved.