Binary Scaled Current Array Source for Digital to Analog Converters

This invention relates in general to binary scaled current sources and more particularly to such a source utilizing current switching. In a common approach to n-bit digital to analog (D/A) converters, a current source provides a set of dc currents of magnitude I.sub.k =2.sup.k-1 *I.sub.1 for k=1 to n, where I.sub.1 is the magnitude of the least significant current provided by the source. In response to an input binary number, a control section of the D/A converter directs to the output of the D/A converter selected ones of the currents I.sub.k. In general, the current I.sub.k is directed to the converter output if and only if the kth least significant bit of the binary number is a one. The sum of all of these currents directed to converter output is therefore proportional to the binary number.

In actual practice, the ratio between successive I.sub.k is not exactly 2 because there are small errors in the I.sub.k. Each of these errors should be small compared to the least significant current I.sub.1 so that the output current is generated to n-bits accuracy. As the number of bits of precision increases, the difficulty of producing correspondingly precise I.sub.k becomes increasingly difficult. In one type of binary scaled current source, the I.sub.k are generated by an R-2R ladder as shown in FIG. 13. The precision of each of the I.sub.k is determined by the precision of the resistance values of the elements in the R-2R ladder and by the uniformity of the voltage on the right hand side terminals of all 2R resistors. For D/A converters of resolution greater than 10 bits, precisely matched resistors are produced in a monolithic form of reasonable chip-area only with the use of expensive laser trimming or selective Zener diode shorting techniques after fabrication.

In a technique illustrated in FIG. 14 and presented by R. J. Van de Plassche in the article "Dynamic Element Matching for High Accuracy Monolithic D/A Converters", IEEE JSSC, pp. 795-800, vol. Sc-11, no.6, December 1976, the precision required for components of the current source is relieved somewhat by use of current switches that interleave currents to average out errors caused by imperfect matching of components. In that approach, a current of magnitude 2I is supplied to a first divider that is to produce two currents each of magnitude I. However, because of mismatch between components of the first divider, a first one of the currents has magnitude (1+e)*I and the second of the currents has magnitude (1-e)*I, where e is a measure of the error in the two resulting currents. These two currents are supplied to a first switch which is responsive to a clock having a 50% duty cycle. During the first half of a clock cycle, the first current is directed to an output a and the second of the currents is directed to an output b. In the other half of the clock cycle, the first current is directed to output b and the second current is directed to output a. If the duty cycle were exactly 50%, then the average current I.sub.a at output a and the average current I.sub.b at output b would each equal I.

In general, the duty cycle is 50% plus some fractional error f (i.e., the duty cycle is 0.5*(1+f)) so that the current I.sub.a is equal to (1+ef)*I and I.sub.b is equal to (1-ef)*I. Because the error is now ef instead of e, the precision of the components in the first switch and divider can be relaxed somewhat without reduction in the precision of I.sub.a and I.sub.b. A series of dividers and switches can be cascaded as in FIG. 14 to produce a set of binary scaled output currents for use in a D/A converter. Although this technique reduces somewhat the precision required for elements, the scheme is still inherently limited by such precision as well as the precision of the duty cycle. It would therefore be advantageous to have a new type of source of binary scaled currents that is not so limited.

In accordance with the illustrated preferred embodiments, a binary scaled current source is presented that utilizes a binary relation between the duty cycles of control signals to generate binary scaled currents. This scheme is referred to herein as the "weighted duty cycle" (WDC) scheme. A D/A converter is also shown that utilizes this current source.

The binary scaled current source utilizes an n-bit binary counter and decoding logic to generate a set of n+1 control signals B.sub.k for k=0, . . . ,n. The duty cycle for the kth control signal (for k=1 to n) is 2.sup.k-1 times the duty cycle of the zeroth control signal. A set of n+1 switches M.sub.0, . . . ,M.sub.n are connected in parallel to a dc current source of magnitude I. Each switch M.sub.k is controlled by control signal B.sub.k. The shapes of the control signals are selected so that at any given time, one and only one of the control signals B.sub.k is high. As a result of this, switch M.sub.k conducts the entire current I to its output when B.sub.k is high. Therefore, the current i.sub.k (for k=1 to n) at the output of M.sub.k has an average value I.sub.k equal to 2.sup.k-n-1 *I. Each output current i.sub.k is passed through an associated low pass filter to produce a dc current with total ripple negligible compared to I.sub.1 (e.g., less than one-eighth I.sub.1). These dc currents are the binary scaled currents suitable for use in a D/A converter.

To eliminate errors in the I.sub.k due to errors in the timing of the control signals, a pair of complementary switches M.sub.C0 and M.sub.C1 are connected between the source of current I and the switches M.sub.k. These switches act to supply the current I to the input of switches M.sub.k as a series of equal pulses. The timing of the pulses is such that none of the control signals makes a transition during one of these pulses. Therefore, the current i.sub.k is a series of these pulses of current I and the average rate of such pluses in i.sub.k is 2.sup.k-1 times the rates of pulses in i.sub.1.

There are two preferred embodiments of the weighted duty cycle scheme. In first of these, referred to herein as the "weighted pulse width" (WPW) scheme, each of the control signals is a periodic signal of period T and the shape of control signal B.sub.k (for k=1 to n) is such that it is high within each period T for one continuous pulse of width 2.sup.k-n-1 *T. In the other of these preferred embodiments referred to herein as the "weighted repetition-rate" (WRR) scheme, B.sub.k (for k=1 to n) is a periodic signal and consists of 2.sup.k-1 disjoint pulses of width 2.sup.-n *T where T is the group pattern repetition period for the set of all B.sub.k.

There are two primary sources of error in the WDC scheme. The first source of error is caused by the parasitic capacitance C.sub.p at the common input to switches M.sub.k. Field effect are a convenient choice for the switches M.sub.k. The application of pulses of current to the common input produces at this common input an alternation between high and low voltage values at the same frequency as the current pulses. Because of unavoidable differences in gate voltage and in threshold voltage between field effect transistor switches M.sub.k, these high and low values will not be identical. This results in a net transfer of charge to the parasitic capacitance during some of periods in which a single switch M.sub.k is conductive. This net transfer of charge to or from the parasitic capacitance causes a similar difference in the desired pulse through M.sub.k. The effect on I.sub.k is proportional to the number of transitions per unit time in control signal B.sub.k and therefore the problem is more serious in the weighted repetition-rate scheme in which the number of transitions per unit time in control signal B.sub.k is 2.sup.k-1 times the number of transitions per unit time in control signal B.sub.1. The second source of error is the residual ripple that appears in the outputs in addition to the dc currents I.sub.k. The low pass filters are selected to make this error in each I.sub.k be negligible compared to I.sub.1 (e.g., less than one-eighth of I.sub.1).

FIG. 1 is a block diagram of a binary scaled current source utilizing the weighted duty cycle (WDC) scheme.

FIG. 2 shows control signals suitable for use in the weighted pulse width (WPW) and weighted repetition-rate (WRR) embodiments of the WDC scheme.

FIG. 3 is a block diagram of a binary scaled current source in which a source current is pulsed to remove errors in the binary scaled currents due to timing errors in the control signals.

FIG. 4 illustrates timing relation between the control signals and the current pulses.

FIG. 5A illustrates the current errors that result from parasitic capacitance at the common input to the switches M.sub.k.

FIG. 5B illustrates a typical drain current versus gatesource voltage relationship of a MOSFET device.

FIG. 6 shows a low pass filter, suitable for use in the binary scaled current source.

FIG. 7 is an overall block diagram of a D/A converter utilizing the weighted duty cycle scheme.

FIG. 8 presents typical parameter values for the signal levels and the width to length ratios of transistors.

FIG. 9 is a block diagram of a binary counter and decoding logic to generate control signals for use in the WRR scheme.

FIG. 10 presents the signals involved in the circuit of FIG. 9.

FIG. 11 is a block diagram of a binary counter decoding logic to generate control signals for use in the WPW scheme.

FIG. 12 presents the signals involved in the circuit of FIG. 11.

FIG. 13 is an R-2R ladder used in the prior art to produce binary scaled currents.

FIG. 14 is a prior art binary scaled current source utilizing time multiplexing to reduce current errors due to mismatch of circuit components.

In the Figures, the first digit of the reference numerals will indicate the first figure in which that element is presented. In FIG. 1 is presented, for the special case n=3, a block diagram of an n-bit binary scaled current source illustrating the use of a weighted duty cycle (WDC) scheme for generating the binary scaled currents. A current source 11 supplies a current I to a rail 12 to which are connected the inputs of a set of switches M.sub.0, . . . , M.sub.n such as field effect transistors 13-16. The kth switch M.sub.k is turned on and off in response to a kth control signal such as control signal B.sub.k applied to the gate of transistor M.sub.k in FIG. 1. The duty cycle of the kth control signal B.sub.k is 2.sup.k-1 times the duty cycle of the zeroth control signal B.sub.0 and first control signal B.sub.1. The timing and shape of the control signals is selected so that one and only one of the control signals is high at a given time so that one and only one of the switches is conductive at a given time. As a result of this, in the output of the kth switch is produced a current i.sub.k that is equal to I during a fraction 2.sup.k-n-1 of the cycle and is zero during the remainder of the cycle.

Each current i.sub.k (for k=1 to n) is passed through a low pass filter that produces a dc current I.sub.k of magnitude 2.sup.k-n-1 *I. The currents I.sub.1 and I.sub.n represent the least significant bit (LSB) and the most significant bit (MSB) of binary scaled currents, respectively. The current i.sub.0 is not one of the binary scaled currents and therefore is not supplied to the control section of a D/A converter for production of the output of the D/A converter. Current i.sub.0 can be dumped, for example, to ground.

Two particular shapes of the control signals are particularly easy to produce and are presented in FIG. 2. These two schemes are referred to herein as the weighted pulse width (WPW) scheme and the weighted repetition rate (WRR) scheme. In both of these schemes, the control signals are periodic with a group pattern repetition period T in which all of the control signals repeat their patterns. In the WPW scheme, in a single period of the kth control signal B.sub.k (for k=1 to n), the control signal contains a single pulse of duration 2.sup.k-n-1 *T. In the WRR scheme, in a single group pattern repetition period T, the control signal B.sub.k (for k=1 to n) contains 2.sup.k-1 pulses of duration 2.sup.-n *T. The timing of the pulses in both types of signals is such that one and only one control signal is high at a given time. The generation of these control signals will be discussed below in respect to FIGS. 9-12.

The precision with which the I.sub.k are generated is dependent on the precision with which the duty cycles of the control signals are generated. The error in the duty cycle of each of the control signals should be small compared to the duty cycle of B.sub.0 and B.sub.1 so that the currents can be summed to produce a total D/A converter output current that is accurate to within a small fraction of the value of the least significant binary scaled current I.sub.1. This limitation can place a severe limit on the number n of bits of accuracy that can be produced by this scheme. Therefore, in FIG. 3 is shown an embodiment of a weighted duty cycle type binary scaled current source that eliminates this sensitivity to the precision of the duty cycle of the control signals.

In FIG. 3, a pair of switches M.sub.C0 and M.sub.C1 such as field effect transistors 315 and 316, are included in the circuit of FIG. 1. The purpose of these additional switches is to provide the current I to switches M.sub.0, . . . , M.sub.n in pulses that do not overlap any transition in a control signal. To distinguish reference to the two types of switches, M.sub.C0 and M.sub.C1 will be referred to as the pulse switches and M.sub.0, . . . , M.sub.n will be referred to as the binary switches. M.sub.C0 is responsive to a clock signal, CLK, and M.sub.C1 is responsive to the complement, -CLK, of the clock signal. In FIG. 4 is illustrated the relationship between the current pulses (which occur during the cross-hatched intervals) supplied to the binary switches and the control signals for the binary switches.

The pulse switches function to direct the current I to the binary switches only in those intervals in which the clock signal is high. As will be discussed in more detail in reference to FIG. 7, the control signals and the clock signal are generated in response to the output of the same crystal oscillator. Because current flows to the binary switches only during a pulse in CLK and no control signals make a transition during any of these pulses, the duration of current flowing through each of the binary switches is unaffected by small errors in the timing or shape of the transitions in the control signals B.sub.0, . . . , B.sub.n.

There are two main sources of error in the weighted duty cycle scheme. The first source of error arises due to a parasitic capacitance 317 at source rail 32 to which the inputs of the binary switches are connected. The value of this parasitic capacitance is represented by C.sub.p. The cause of this error can be understood by reference to FIG. 5A in which, for the weighted repetition rate scheme, are presented the clock signal CLK, the control signals B.sub.1, . . . , B.sub.3 for the case of a 3-bit binary scaled current source, the voltage V of source rail 32 and the current i to parasitic capacitance 317.

The time variation of the voltage V of source rail 32 can be understood by reference to FIG. 5B which presents a typical plot of drain current I.sub.D versus gate-to-source voltage V.sub.GS. In that figure, VT is the threshold gate-to-source voltage at which I.sub.D is substantially zero and V.sub.GS (I) is the value of the gate-to-source voltage at which I.sub.D equals the current I of current source 11. When pulse switch M.sub.C0 is off, capacitance 317 will be charged by the binary switch M.sub.k which has the only high control voltage B.sub.k until voltage V rises to the level at which switch M.sub.k becomes nonconductive. Therefore, the high voltage is V.sub.kh =V.sub.kG -V.sub.Tk and the low voltage is V.sub.k1 =V.sub.kG -V.sub.kGS (I), where M.sub.k is the binary switch with the high control voltage, V.sub.kG is the high value of the gate voltage for M.sub.k, V.sub.kT is the threshold voltage of M.sub.k and V.sub.kGS (I) is the gate-to-source voltage for which the drain current of M.sub.k is equal to I.

When these high and low values are not equal for all switches due to imperfect match between binary switches M.sub.k as shown in an exaggerated example in FIG. 5A, the parasitic capacitance will affect the net charge transferred through a switch while it is conductive. The charge transferred to parasitic capacitance 317 during a transition in the voltage on rail 32 is equal to the area under a current spike in the current i to the parasitic capacitance at the time of the transition. This area is proportional to the parasitic capacitance and is also proportional to the change in voltage V at that transition. During the first pulse in B.sub.3 from t=1 to t=5, there is no net transfer of charge to the parasitic capacitance because the voltage at t=1 is equal to the voltage at t=5. Because of this, the areas of the current spikes in i at t=2 and t=4 are equal in magnitude, but are of opposite sign so that no net charge is transferred to the parasitic capacitance between t=1 and t=5.

However, since at t=5, the voltage is not equal to the voltage at t=9, the net charge transferred to the parasitic capacitance during that interval is non-zero. Since switch M.sub.2 is conductive during that interval, this will result in an error in the value of I.sub.2. Since pulses in B.sub.2 always follow pulses in B.sub.3, this same error will occur in every transfer of charge through switch M.sub.2 and therefore the error in I.sub.2 will be proportional to the rate of occurrence of such pulses in B.sub.2. Therefore, this problem will be much more serious in the weighted repetition-rate scheme than in the weighted pulse width scheme because of the increased number of transitions in the weighted repetition-rate scheme.

The net error current I.sub.err for a kth output is:

where F.sub.k is the fundamental frequency of B.sub.k and v is the average value of the differences in voltage V between the time of beginning and end of the pulses in B.sub.k. For a 12-bit binary scaled current source (i.e., n=12), a parasitic capacitance of 10 pF, a value of 100 mV for v, and a current I.sub.n =10 mA, the weighted repetition rate scheme is limited to a clock rate of at most 1.2 MHz if I.sub.err is to be less than one-eighth of I.sub.1. For a 12-bit binary scaled current source, F.sub.n is 2048 times larger in the weighted repetition rate scheme than in the weighted pulse width scheme and therefore, under otherwise equal conditions, the clock rate can be 2048 times faster in the WPW scheme than in the WRR scheme.

The second source of error is the residual ripple in each output current after the i.sub.k associated with that output is filtered through its associated low pass filter. A low pass filter suitable for use in this binary scaled current source is the filter in FIG. 6. This filter consists of three RC filters in series. The resistance R in each filter is chosen to produce a convenient value (e.g., 1 volt) of dc drop V.sub.dc across each stage of that filter. The capacitance C is then chosen so that the peak-to-peak value of the residual ripple is negligible compared to I.sub.1 (e.g., less than one-eighth of I.sub.1). This requires that the value of the capacitance C in the filter for the most significant current i.sub.k be:

for the weighted repetition-rate scheme: 0.2*I*2.sup.-2n/3 *T/V.sub.dc

for the weighted pulse width scheme: 0.09*I*2.sup.n/3 *T/V.sub.dc

In FIG. 7 is an overall block diagram of a D/A converter that includes a binary scaled current source that utilizes the weighted duty cycle scheme. A current source 70 provides a current I that is controllably switched to produce binary weighted currents. A 2-phase clock generator 71 is responsive to an output signal from a crystal oscillator 72 to produce a pair of clock signals that are phase shifted by 90 degree with one another. A first of these clock signals is supplied to a clock buffer which produces a clock signal CLK and its complementary -CLK. Pulse switches 74 and 75 are responsive to CLK and -CLK respectively and are connected to current source 70 to provide pulses of current to the inputs of a set of binary switches 712. A pair of buffers 76 and 77 buffer the pulse switches so that the duty cycle of the pulses is not modulated by signals present at other points in the binary scaled current source.

The second of the clock signals CLK' is applied to an n-bit binary counter 710, decoding logic 79 and an n+1 bit data latch. In response to the output of binary counter 710, decoding logic 79 produces a set of n+1 digital control signals. In response to the second clock signal, data latch applies each of the 13 control signals through a buffer amplifier 711 to the gate of an associated one of the binary switches. The current of the switch M.sub.0 in FIG. 7 is dumped; the currents of the n switches M.sub.1 , . . . , M.sub.n in FIG. 7 feed a set of low pass filters 717. The resulting binary scaled currents are supplied on a set of n lines 716 to a control section 713 of the D/A converter. The kth least significant current I.sub.k is associated with the kth least significant bit of a binary number entered on an input 714 to control section 713. For those bits in the binary number that are ones, their associated binary scaled current is directed to an output 715 of the D/A converter so that the output current is proportional to the binary number.

In FIG. 8 are shown representative values of width-to-length ratios for various MOS transistors and voltage levels of various signals in an embodiment utilizing the weighted duty cycle scheme. In FIG. 9 is presented a circuit suitable for use as 2-phase clock generator 71, binary counter 710 and decoding logic 79 for the WRR scheme. This circuit utilizes a section 91 of n master slave toggle flip-flops connected in cascade. The output Q.sub.m and the output Q.sub.s of each of the flip-flops is the master output and the slave output, respectively. A NOT gate 92 and a set 93 of AND gates are each connected to master outputs to produce the control signals B.sub.k. The relations between the signals in this circuit are shown in FIG. 10. FIGS. 11 and 12 are analogous to FIGS. 9 and 10 for the WPW scheme.