Data Clock Recovery Circuit

This invention relates to digital communications systems and, more particularly, to the recovery of a clock signal for sampling a received data signal.

An essential function in a receiver of digital communication systems is the recovery of a clock signal needed for sampling a received data signal to recover the transmitted data. Typically, this clock recovery function has been obtained by employing a phase locked loop. Phase locked loops include a voltage variable frequency oscillator and a circuit for holding a frequency control voltage. In response to transitions of the received data signal, the phase locked loop corrects the frequency of the voltage variable oscillator and generates the clock signal used to sample the received data signal.

In certain systems data is transmitted using a so-called non-return to zero (NRZ) data system. The NRZ data stream may have long intervals during which there are no data transitions. In the absence of data transitions, the phase locked loop variable oscillator free runs at the last frequency established by the control voltage of the hold circuit. Because of instabilities in the variable frequency oscillator and the hold circuit, the phase of the oscillator drifts and errors result in the data recovery process. Consequently, in systems using phase locked loops for clock signal recovery the interval between data transitions must be restricted in order to minimize the phase drift and, hence, errors in the data recovery.

A further problem with phase locked loops is the need to use the variable frequency oscillator. In many systems this is an added expense.

Serial data clock recovery is realized by advantageously employing a digitally variable phase oscillator. The variable phase oscillator includes a fixed oscillator, phase coder and comparator. Clock recovery pulses are generated by comparing a coded phase value of the fixed oscillator output to a prescribed phase value.

In one data recovery application, the variable phase oscillator is employed in conjunction with a phase register to obtain the prescribed phase value. The stored prescribed phase value is the phase difference between an incoming data transition and the coded fixed oscillator phase value. That is to say, the stored phase value is the phase coder output at the occurrence of an input data transition. A constant phase value is added to the stored phase value to insure that the received data is sampled near the middle of the data eye pattern.

The invention will be more fully understood from the following detailed description of an illustrative embodiment taken in connection with the appended figures in which:

FIG. 1 shows in simplified block diagram form a digitally variable phase oscillator in accordance with the invention;

FIG. 2 graphically depicts waveforms that are useful in describing the operation of the embodiment of the invention shown in FIG. 1;

FIG. 3 shows in simplified block diagram form a data clock recovery pulse generator including the invention;

FIG. 4 graphically illustrates waveforms useful in describing the operation of the embodiment of the invention shown in FIG. 3;

FIG. 5 graphically depicts a relationship between a data bit and the recovered clock pulse useful in describing the limits of phase variation therebetween; and

FIG. 6 depicts in simplified block diagram form an implementation of a data clock recovery pulse generator in accordance with the invention.

A digitally controllable variable phase oscillator in accordance with the invention is shown in simplified block diagram form in FIG. 1. Accordingly, shown are fixed oscillator 101, phase coder 102 and comparator 103. Fixed oscillator 101 may be any of a number of known oscillators capable of generating a signal v.sub.L (t) having a frequency which is substantially the same as, for example, the nominal baud rate in a data transmission system. Oscillator 101 supplies output signal v.sub.L (t) having phase .phi..sub.L (t) as shown in FIG. 2 to phase coder 102. The continuous phase .phi..sub.L (t) of oscillator 101 output v.sub.L (t) is quantized and encoded by phase coder 102 into N states per input period to generate a digital output represented by periodic waveform [.phi..sub.L (t)].sub.N having period T.sub.L as shown in FIG. 2. Periodic waveform [.phi..sub.L (t)].sub.N is supplied in digital to one input (A) of comparator 102 while an arbitrary phase code value K is supplied to another input (B) of comparator 103. The output of comparator 103 is clock recovery pulse signal v.sub. R (t) (FIG. 2) and is generated when [.phi..sub.L (t)].sub.N (input A) equals K (input B). Clock recovery pulse signal v.sub.R (t) is also periodic with a period T.sub.L, and phase ##EQU1## where K provides, in accordance with an aspect of the invention, and in conjunction with phase coder 102 a phase shift control for clock recovery pulse signal v.sub.R (t) in quantum steps of 2.pi./N. The pulse width of v.sub.R (t) is T.sub.L /N and it is always preserved if K changes only during the zero portion of the waveform.

FIG. 3 shows in simplified block diagram form an embodiment of the invention for use in digital clock pulse recovery. The elements of the clock pulse recovery arrangement of FIG. 3 which are identical to those shown in FIG. 1 have been similarly numbered. Accordingly, shown are variable phase oscillator 100 including oscillator 101, phase coder 102 and comparator 103, transition detector 301, phase register 302 and summer 303. An incoming data signal, for example, a non-return to zero (NRZ) data signal, is supplied to transition detector 301 which generates pulse signals representative of the data transitions (T.sub.TRANS) as shown in FIG. 4. It is noted that the NRZ signal can have relatively long intervals of no transitions in the incoming data signal. The T.sub.TRANS pulses are supplied to one input of phase register 302. Additionally, digital output [.phi..sub.L (t)].sub.N from phase coder 102 is supplied to a second input of phase register 302. Register 302 in response to the T.sub.TRANS pulse stores the digital value of [.phi..sub.L (t)].sub.N occurring at the instant of the last data transition, namely [.phi. .sub.L (TRANS)].sub.N as shown in FIG. 4. This digital value is stored until the next data transition occurs. Adder 303 adds a constant value C to [.phi..sub.L (TRANS)].sub.N to obtain ##EQU2## Again where [.phi..sub.L (TRANS)].sub.N represents the digital phase code value appearing at the output of phase coder 102 at the occurrence of the last input data transition and where C is a fixed phase value offset added modulo-N to the phase value [.phi..sub.L (TRANS)].sub.N stored in phase register 302. The phase value offset C is chosen so that phase comparator 103 in response to the phase coder 102 output [.phi..sub.L (t)].sub.N and K generates a clock recovery pulse (v.sub.R (t)) C/N2.pi. radians from the beginning of the incoming data signal bit period, which corresponds substantially to the middle of the incoming data eye pattern as shown in FIG. 4. In applications where only the rising edges of the incoming data are sufficient for data recovery, transition detector 301 can be eliminated. In situations where the frequency of local oscillator 101 is the same as that of the incoming data after an initial adjustment, the phase of the recovered clock signal v.sub.R (t) remains constant over "long" intervals during which there are no transitions in the incoming data. Consequently, errors possible because of drift in voltage control variable oscillators are used in phase locked loops are eliminated. In situations where the local oscillator frequency differs from the incoming data frequency (bit rate), the phase of the recovered clock signal v.sub.R (t) is adjusted with respect to the phase of the incoming data signal upon occurrence of the incoming data transitions. Again, once the phase of v.sub.R (t) is adjusted it remains constant until the next incoming data transition and only changes then if the frequencies differ.

It is important to determine the maximum phase variation between the input data and the local oscillator output that can be tolerated so that no socalled cycle slipping occurs in the absence of input data transitions. This maximum phase variation is defined as the phase "lock limit". A cycle slip is a data bit deletion (or repetition) that results when the phase of the recovered clock v.sub.R (t) moves beyond the data bit boundary during a data transition free interval. FIG. 5 shows the relationship of the incoming data bit boundaries and a pulse of the recovered clock v.sub.R (t). If the recovered clock pulse has been adjusted to within one quantization step of the middle of the incoming data bit period, then .DELTA.t.sub.1 and .DELTA.t.sub.2 represent the maximum phase excursions of the recovered clock in the absence of input transitions so that the phase lock limit is not violated. If the frequency f.sub.L, of local oscillation 101 is less than the frequency, f.sub.B, of the incoming data, ##EQU3## where T.sub.B is the data bit period and J.sub.pp is the incoming peak to peak jitter. If the frequency of local oscillator 101 is greater than the frequency of the incoming data, ##EQU4## where T.sub.L is the period of the local oscillator output signal. Guard Bands 1 and 2 are margins determined by specific component propagation delays of a particular implementation.

The relative phase excursion .DELTA.t.sub.i, between two periodic waveforms with a fractional frequency difference, .eta., after an interval .tau. is given by the well known relationship

Therefore, for a given phase excursion constraint, .DELTA.t.sub.i, the maximum number of transition-free data bit periods, m, after an interval .tau.=mT.sub.B is given by, ##EQU5## where .DELTA.t.sub.i is either .DELTA.t.sub.1 or .DELTA.t.sub.2 of equation 3 and equation 4, respectively. For a fractional frequency difference ##EQU6## the maximum number of transition-free data bit periods is given by ##EQU7##

FIG. 6 shows in simplified block diagram form a specific implementation of the invention for a digital timing recovery application. Accordingly, shown are variable phase oscillator 100 including local oscillator 101, phase decoder 102, and comparator 103, transition detector 202 and phase register and adder 601. In this example, oscillator 101 is a stable fixed oscillator which generates an approximately 32 Mb/sec (32.768) local clock signal v.sub.L (t).

Phase coder 102 includes delay 603 having a delay interval of T.sub.L /4 where T.sub.L is the period of v.sub.L (t). Thus, in this example, phase coder 102 quantizes the local oscillator output v.sub.L (t) in four (4) phase steps. The resulting output [.phi..sub.L (t)] is two bits which represent each quarter of a cycle in a Gray-coded format. The two bit Gray-code output from phase coder 102 is supplied to phase register and adder 601 and to comparator 103.

Transition detector 301 includes delay 604 and Exclusive OR gate 605. Detector 301 generates a positive going output pulse T.sub.TRANS at the occurrence of each transition (positive and negative) of the input data in well-known fashion. Output T.sub.TRANS is supplied to the CLK input of flip-flop 603 in phase register and adder 601.

Phase register and adder 601 comprises dual D type flip-flop 603. The two bit Gray-code output from phase coder 102 is supplied to inputs D.sub.1 and D.sub.2. The T.sub.TRANS output from transition detector 202 is supplied to the CLK input of flip-flop 601. Again, as described above, phase register and adder 601 stores the phase output value [.phi..sub.L (TRANS)].sub.4 from phase coder 102 upon occurrence of a transition in the incoming data plus a constant C which in this example is 2. The complemented output Q.sub.1,Q.sub.2 of flip-flop 603 generates output K by providing an "automatic" modulo 4 addition of the fixed phase offset C which in this example is chosen to be one-half cycle (2 phase code steps). Additionally, since a Gray-code format is being used only one bit of the two bits changes from one phase step to the next. This allows phase register 601 to store the present phase value without any code uncertainties. That is to say, by using the Gray-code format race conditions in the circuit are eliminated because only one bit changes at a time. The complemented output from phase register and adder 601 is supplied to comparator 103.

Comparator 103 includes Exclusive OR gates 606 and 607 and NOR gate 608. As indicated above, comparator 103 operates to generate a positive recovered clock pulse v.sub.R (t) when the output from phase coder 102 [.phi..sub.L (t)].sub.4 equals K, where in this example, K=[.phi..sub.L (TRANS)].sub.4 +2.

By employing the instant invention it can be shown that the phase lock limit is not violated for extremely long input data transition free intervals. For example, with the frequency of local oscillation 101 being less than that of the incoming data and if the difference is 100 ppm (parts per million), it can be shown by using equation 6 that for a specific implementation the phase lock limit is not violated for approximately 1638 transition free data bit periods. Similarly, if the local oscillator frequency is greater than that of the incoming date, and if the difference is 100 ppm, it can be shown again by using equation 6 that the phase lock limit is not violated for approximately 1,114 transition free data bit periods. Moreover, if the local oscillator frequency is phase locked to a that data clock there should be no phase variation after the initial phase adjustment. Consequently, there can be an infinite number of no transition data bit periods without incurring an error.

The above-described arrangements are, of course, merely illustrative of the principles of this invention. Numerous other arrangements may be devised by those skilled in the art without departing from the spirit or scope of the invention. For example, the delay line phase coder may be replaced by a modulo-N Gray-code counter and by using a local oscillator frequency that is N times the incoming data rate.