Range Checking Comparator

1. Field of the Invention

The present invention relates to a comparator by which it can be determined whether a certain voltage is in a predetermined range with respect to a reference voltage.

3. Description of the Prior Art

For the purpose of increasing the integration density, mask read-only memory cells having multi-values, for example, four values, recently have frequently been used. In the case of a cell having four values, the four values correspond to the voltage width or range of the transistor, and the mid value of the width is used as the value of the reference cell. The value of the reference cell is read out, and the readout value is coded into binary information. In such a cell having four values, the deviation of the width of the transistor of the reference cell should be small because the width of the transistor is originally small. Therefore, detection of the value of the reference cell becomes very difficult because the flip-flop circuit which is conventionally used cannot be used to detect this value.

A single flip-flop circuit can be used to determine whether or not an input voltage is larger or smaller than the reference voltage. However, a flip-flop circuit cannot be used to determine whether or not the input voltage is in the predetermined range with respect to the reference voltage or in which direction the input voltage is shifted from the predetermined range. In such a case, a window comparator comprising two comparators is used. However, a window comparator requires two reference voltages and the circuit of the window comparator is complicated, thereby rendering the comparator unsuitable for forming an integrated circuit.

An object of the present invention is to form a comparator by which it can be determined whether a certain voltage is in a predetermined range with respect to a reference voltage.

Another object of the present invention is to provide a comparator which can be used to suitably determine the multi-values of a read-only memory cell.

According to the present invention, this object can be achieved with a comparator including a first terminal, a second terminal, a first flip-flop circuit which inverts when the voltage applied to the first terminal becomes larger by .DELTA.V.sub.1 than the voltage applied to the second terminal. Also included are a third terminal, a fourth terminal, a second flip-flop circuit which inverts when the voltage applied to the third terminal becomes smaller by .DELTA.V.sub.2 than the voltage applied to the fourth terminal, a first switching circuit and a second switching circuit which, respectively, connect the first terminal and the third terminal to voltage sources to be compared, a third switching circuit and a fourth switching circuit which, respectively, connect the second terminal and the fourth terminal to a reference voltage source. Further included is a fifth switching circuit which is commonly connected to the first flip-flop circuit and the second flip-flop circuit so that the result of the comparison is output from the first terminal and the third terminal or the second terminal and the fourth terminal.

Further, features and advantages of the present invention will be apparent from the ensuing description, with reference to the accompanying drawings, to which, however, the scope of the invention is in no way limited.

FIG. 1 is a circuit diagram of one embodiment of the comparator according to the present invention.

FIGS. 2A to 2D are waveform diagrams illustrating the operation of the comparator shown in FIG. 1.

FIG. 3 is a block diagram illustrating how the present invention is used for determining the four values of the read-only memory cell.

FIG. 4 is a circuit diagram of another embodiment of the comparator according to the present invention.

FIGS. 5A to 5D are waveform diagrams illustrating the operation of the comparator shown in FIG. 4.

FIG. 1 illustrates one embodiment of the present invention, and FIGS. 2A to 2D are diagrams illustrating the function of the present invention.

In FIG. 1, the transistors T.sub.1, T.sub.2, T.sub.5 and T.sub.6 are controlled by a phase clock pulse .phi..sub.0 and are turned on after the nodes Q.sub.1, Q.sub.1, Q.sub.2 and Q.sub.2 are precharged to the voltage V.sub.C and the reference voltage V.sub.R, respectively, to separate the input side and the reference voltage side from the comparator. The transistors T.sub.3 and T.sub.4 form a first flip-flop circuit FF.sub.1, and the transistors T.sub.7 and T.sub.8 form a second flip-flop circuit FF.sub.2. In the transistors T.sub.3, T.sub.4 and T.sub.7, T.sub.8, a difference of several hundred millivolts (.DELTA.V.sub.th) in the threshold values V.sub.th is created. That is, the threshold value V.sub.th of the transistors T.sub.4 and T.sub.7 is set several hundred millivolts higher than that of the transistors T.sub.3 and T.sub.8. In such a construction, when the voltage V.sub.C is in the range of several hundred millivolts with respect to the reference voltage V.sub.R, the nodes Q.sub.1 and Q.sub.2 (or Q.sub.1 and Q.sub.2) of the first flip-flop FF.sub.1 and of the second flip-flop FF.sub.2 have reverse relationships. When the voltage V.sub.C is several millivolts higher than the voltage V.sub.R, the nodes Q.sub.1 and Q.sub.2 both become a high level, and when the voltage V.sub.C is several millivolts lower than the voltage V.sub.R, the nodes Q.sub.1 and Q.sub.2 both become a low level. That is, when .phi..sub.0 is placed at a high level and .phi..sub.0 is placed at a low level, the nodes Q.sub.1, Q.sub.1, Q.sub.2 and Q.sub.2 are precharged. When .phi..sub.0 is placed at a low level and .phi..sub.0 is placed at a high level, the transistors T.sub.1, T.sub.2, T.sub.5 and T.sub.6 are placed in an off state, the transistor T.sub.10 is placed in an on state, and the flip-flops FF.sub.1 and FF.sub.2 are activated so that the comparator operation is commenced.

This operation is shown in FIGS. 2A, 2B, 2C, and 2D. FIG. 2A illustrates the case when the voltage V.sub.C is V.sub.C >V.sub.R +.DELTA.V.sub.th. In this case, the transistor T.sub.4 turns on and the transistor T.sub.3 turns off so that the node Q.sub.1 becomes a high level and the node Q.sub.1 becomes a low level. Further, the transistor T.sub.8 turns on and the transistor T.sub.7 turns off so that the node Q.sub.2 becomes a high level and the node Q.sub.2 becomes a low level.

FIG. 2B illustrates the case when V.sub.R +V.sub.th > V.sub.C >V.sub.R. In this case, the transistor T.sub.3 turns on, the transistor T.sub.4 turns off, the transistor T.sub.7 turns off, and the transistor T.sub.8 turns on so that the nodes Q.sub.1 and Q.sub.2 become a low level and the nodes Q.sub.1 and Q.sub.2 become a high level. FIG. 2C illustrates the case when V.sub.R >V.sub.C >.

V.sub.R -.DELTA.Vth in which the nodes Q.sub.1 and Q.sub.2 become a low level and the nodes Q.sub.2 and Q.sub.1 become a high level. FIG. 2D illustrates the case when V.sub.R -.DELTA.Vth>V.sub.C. In this case, the nodes Q.sub.1 and Q.sub.2 become a high level and the nodes Q.sub.2 and Q.sub.1 become a low level. The cases shown in FIGS. 2A, 2B, 2C, and 2D are shown in the Table.

As is shown in the Table, when the voltage V.sub.C is in the range of several hundred millivolts with respect to the reference voltage V.sub.R, the node Q.sub.1 becomes a low level but the node Q.sub.2 becomes a high level. Therefore, if the levels of the nodes Q.sub.1 and Q.sub.2 (or Q.sub.1 and Q.sub.2) are monitored, whether the voltage V.sub.C is in the range of several hundred millivolts with respect to the reference voltage V.sub.R or is higher or lower than this range can be determined. This range can be freely set by changing the difference .DELTA.V.sub.th between the transistors T.sub.3 and T.sub.4 and the transistors T.sub.7 and T.sub.8. Further, the difference .DELTA.V.sub.th can be easily changed by changing the threshold value of the transistors during ion implantation.

FIG. 3 illustrates the application of the comparator shown in FIG. 1. In FIG. 3, a cell array 1 includes a transistor T.sub.11, having four values, positioned close to a word line and a bit line. The word line and the bit line are selected by a word decoder 2 and a column decoder 3. The selected value of the transistor T.sub.11 is supplied via a transistor T.sub.12 to a transistor T.sub.13 which is used as a level generator which outputs four levels. The output of the transistor T.sub.13 is supplied to comparators 4a, 4b, 4c and 4d which correspond to the comparator shown in FIG. 1. The transistors T.sub.14, T.sub.15, T.sub.16, T.sub.17, T.sub.18, T.sub.19, T.sub.20 and T.sub.21 are used for supplying four reference voltages to the comparators 4a, 4b, 4c and 4d. The transistors T.sub.15, T.sub.17, T.sub.19 and T.sub.21 are used as dummy cells, and the width of the transistors corresponds to the four values of the transistors in the read-only memory cell. The data of only one of the comparators 4a to 4d which corresponds to the output of the transistor T.sub.13 is output as read data A, and this read data is converted to two-bit information in a logic circuit 5.

FIG. 4 is a circuit diagram of another embodiment of the present invention. In the embodiment of FIG. 4, the transistors T.sub.3a and T.sub.4a and the transistors T.sub.7a and T.sub.8a have the same threshold voltage V.sub.th, and a difference of voltage .DELTA.V is created between the transistors T.sub.3a and T.sub.4a and between the transistors T.sub.7a and T.sub.8a. In FIG. 4, C.sub.P1, C.sub.P2, C.sub.P3 and C.sub.P4 are stray capacitances in the nodes Q.sub.1, Q.sub.1, Q.sub.2 and Q.sub.2, respectively, and the value of the stray capacitances is substantially the same because the layout of the flip-flop circuit is usually symmetrical. Therefore, as is shown in FIG. 4, one terminal of the capacitors C.sub.1 and C.sub.2 is connected to the collectors of the transistor T.sub.4a and the transistor T.sub.7a and another terminal of the capacitors C.sub.1 and C.sub.2 receives the phase clock pulse input .phi..sub.1.

In the circuit shown in FIG. 4, at first, the phase clock pulse .phi..sub.0 is placed at V.sub.SS, the phase clock pulse .phi..sub.1 is changed from V.sub.SS to V.sub.CC, and the nodes Q.sub.1 and Q.sub.2 are placed at a high potential level. Thus, a difference potential .DELTA.V is created between Q.sub.1 and Q.sub.1 and Q.sub.2 and Q.sub.2. This is the same effect as the difference threshold levels in the transistors shown in FIG. 1. Next, the phase clock pulse .phi..sub.0 is applied so as to operate the flip-flop circuits FF.sub.1 and FF.sub.2. The raised voltage .DELTA.V is given as the value ##EQU1## and the value of the capacitance C.sub.1 can be suitably selected for the purpose of determining the value of .DELTA.V.

Timing charts showing the operation of the circuit shown in FIG. 4 are shown in FIGS. 5A, 5B, 5C and 5D. FIG. 5A shows the case when V.sub.C >V.sub.R +.DELTA.V. At the time t.sub.0, the value of .phi..sub.0 is placed at V.sub.SS, and the potentials of V.sub.C and V.sub.R are stored in the nodes Q.sub.1 and Q.sub.1 and the modes Q.sub.2 and Q.sub.2. Next, the phase clock pulse .phi..sub.1 is changed from V.sub.SS to V.sub.CC, and the potentials of the nodes Q.sub.1 and Q.sub.2 are raised to the value of .DELTA.V. Therefore, at the time t.sub.2, as originally V.sub.C >V.sub.R +.DELTA.V, even if the potential of Q.sub.1 is raised to .DELTA.V, VQ.sub.1 >VQ.sub.1. On the other hand, as the potential of Q.sub.2 is raised to .DELTA.V, VQ.sub.2 >VQ.sub.2. Next, the flip-flop circuits FF.sub.1 and FF.sub. 2 are operated at the time t.sub.3. FIG. 5B shows the case when V.sub.R +.DELTA.V>V.sub.C >V.sub.R.

In this case, at the time t.sub.2, the potential of the node Q.sub.1 is raised to .DELTA.V. Therefore, the values of the potentials of Q.sub.1 and Q.sub.1 are inverted so that they become VQ.sub.1 >VQ.sub.1. However, the values of the potentials of Q.sub.2 and Q.sub.2 remain VQ.sub.2 >VQ.sub.2. FIG. 5C shows the case when V.sub.R >V.sub.C >V.sub.R -.DELTA.V.

In this case, at the time t.sub.2, the values of the potentials of Q.sub.1 and Q.sub.1 remain VQ.sub.1 >VQ.sub.1. However, the potential of the node Q.sub.2 is raised to .DELTA.V by the phase clock pulse .phi..sub.1, and the relationship of the potentials of Q.sub.2 and Q.sub.2 is inverted from VQ.sub.2 >VQ.sub.2 to VQ.sub.2 >VQ.sub.2. FIG. 5D shows the case when V.sub.C <V.sub.R -.DELTA.V. In this case, if the potentials of the nodes Q.sub.1 and Q.sub.2 are raised, at the time t.sub.2, the relationships VQ.sub.1 >VQ.sub.1 and VQ.sub.2 >VQ.sub.2 do not change.

As is explained in detail above, in accordance with the present invention, whether or not the stored value is in the range of several hundred millivolts with respect to the reference voltage or is higher or lower than this range can be precisely determined by using this simple circuit. Further, this range can be freely set by changing the threshold voltages of the transistors used in the flip-flop circuit. Further, in the present invention, asymmetrical operation of the flip-flop due to the difference of the transistors used in the flip-flop is used. However, it should be understood that many methods can be used to make the operation of the flip-flop asymmetrical, in addition to the method in which a difference in the threshold values of the transistors is created.