Full Wave Rectifier Having an Operational Amplifier

This invention relates to a full wave rectifier suitable for construction in an integrated circuit form.

A typical example of full wave rectifiers for direct current (DC) to alternate current (AC) conversion is a diode bridge circuit. The full wave rectifier relying on the bridge circuit encounters a problem that sufficient rectification cannot be achieved due to the temperature dependency of the forward voltage drop caused by the four diodes of the circuit. To eliminate such an undesirable voltage drop, another full wave rectifier employing one operational amplifier (op-amp) is described in a paper entitled "Precision Rectification" by D. Bowers, published in the ELECTRONIC ENGINEERING, pp. 71-84, June, 1980.

The rectifier shown in FIG. 6 on page 77 of the Bowers paper, comprises an op-amp A1, a diode D1 connected with the output of the op-amp A1, resistors R.sub.1 and R.sub.2 for setting the gain of the op-amp A1, and a load resistor R.sub.L. However, since this rectifier still requires one diode D1, responsive to the output of the op-amp A1, for performing the switching operation, there is an appreciable amount of voltage drop across the diode, with an insufficient rectification. Besides, the use of the diode D1 prevents the manufacture of the entire circuit by an MOS (metal oxide semiconductor) IC technique, resulting in a bulky rectifier.

An object of the invention is, therefore, to provide a full wave rectifier which is suitable for MOS integration, to achieve a wide range of rectification.

According to an aspect of this invention, a full wave rectifier has an input terminal which is supplied with an AC signal and a rectifier output terminal for delivering a rectified DC signal. An operational amplifier amplifies the AC signal, the amplifier having an inverting input terminal, a non-inverting input terminal grounded and an output terminal. A rectifier gain setting means includes a first resistor which is connected between the inverting input terminal of the amplifier and the rectifier input terminal. A second resistor has the same resistance as that of the first resistor and is connected between the inverting input terminal of the amplifier and the rectifier output terminal. A depletion type MOS FET responds to the output of the amplifier for performing a switching operation.

The present invention will be described in detail with reference to the accompanying drawings in which:

FIG. 1 is a circuit diagram showing one embodiment of the invention;

FIG. 2 is a graph of a drain current (I.sub.D) vs. gate-source voltage (V.sub.GS) characteristic of an FET used in the embodiment of FIG. 1;

FIG. 3 is a graph of a rectification characteristic achieved with the embodiment; and

FIG. 4 is a graph showing a rectification characteristic achievable in a prior art rectifier.

Referring to FIG. 1, the embodiment includes a rectifier input terminal 1 supplied with an AC voltage; a rectifier output terminal 2 for delivering a rectified DC voltage; an op-amp 8 having an inverting input terminal 3, a non-inverting input terminal 4 which is grounded, and an output terminal 5. A depletion type MOS FET 10 responds to the output of the op-amp 8 for performing the switching operation. A rectifier gain setting means is provided in the form of resistors 9 and 11.

Referring to FIG. 2, a voltage (V.sub.GS) vs. current (I.sub.D) characteristic of the MOS FET 10 clearly indicates that the FET 10 causes a forward voltage drop only when voltage V.sub.GS becomes equal to or greater than zero to produce a drain current I.sub.D which is equal to or greater than I.sub.D1. For this reason, in the embodiment, the FET 10 is operated within the range of voltage negative V.sub.GS. The gain (or the ratio of the output to input) of the present full wave rectifier is set at "1" by employing the same resistance for the two resistors 9 and 11. The op-amp 8 receiver at its terminals 6 and 7, respectively, the operating voltages V.sub.DD and V.sub.SS shown in FIG. 3 the voltages being supplied from a DC power source (not shown).

The operation of the embodiment will be described with reference to FIGS. 1, 2, and 3.

Suppose that the voltages applied to the terminals 6 and 7 of the op-amp 8 are V.sub.DD and V.sub.SS, respectively; the input and output voltages of the (FIG. 3) rectifier are V.sub.in and V.sub.out, respectively; the voltage at a junction 3 between the resistors 9 and 11 is V.sub.1 ; the drain voltage of the MOS FET 10 is V.sub.DD ; the resistance of the resistors 9 and 11 is R; and the resistance of a load resistor 12 is R.sub.L. Assuming that the gain and input impedance of the op-amp 8 are infinite, the output voltage V.sub.2 of the op-amp 8 reaches a corresponding negative level which is smaller than a gate-source voltage (-V.sub.TH) shown in FIG. 2, when the input voltage V.sub.in is positive (V.sub.in .gtoreq.0), so that the MOS FET 10 is turned off. Therefore, if the load resistance R.sub.L is sufficiently larger than the gain setting resistance R, the input voltage V.sub.in appears directly as the output voltage V.sub.out ; i.e. V.sub.in =V.sub.out.

On the other hand, when the input voltage V.sub.in is negative (V.sub.in <0), the op-amp output voltage V.sub.2 reaches a corresponding positive level to turn on the MOS FET 10. In this case, due to the infinite input impedance of the amplifier 8, the Kirchhoff's law applies to the junction 3 to give the following equation. ##EQU1## where I.sub.A and I.sub.B represent currents flowing through the resistors 9 and 11, respectively.

Because the current V.sub.out -V.sub.1 /R flowing through the resistor 11 is equal to the sum of currents flowing through the MOS FET 10 and the load resistor 11, equation (1) is modified as: ##EQU2##

As described at page 125 of a text book entitled "MOS Field Effect Transistors and Integrated Circuits", by Paul Richman, published in 1973 by John Willey & Sons, Inc., I.sub.T is expressed as: ##EQU3## where A is the gain of an op-amp, .mu., C.sub.ox, W, L, and V.sub.T are the charge mobility, gate capacity per unit area, gate width, gate length and threshold voltage of an MOS FET, respectively. It should be noted that equation 3 is applicable to both of the depletion type and enhancement type MOSFETs. Supposing R.sub.L >>R, equation (2) may be modified as: ##EQU4##

If the gain A in equation (4) is infinite, equation (4) is rewritten as: ##EQU5##

From equation (5), the output voltage V.sub.out is obtained as:

Equation (6) teaches that the rectifier of FIG. 1 produces a rectified voltage, at the output terminal 2, which is equal to the input voltage even when the input voltage may be negative.

It will be readily apparent that the present invention is adaptable to rectify an AC current given as the input to the terminal 1.

The advantage of the present invention will become clear from FIG. 4 which shows a rectification characteristic which is achievable with the rectifier described in the Bowers paper, previously mentioned. In FIG. 4, due to the forward voltage drop V.sub.DF of the diode, the rectified output voltage becomes saturated as the input voltage V.sub.in increases beyond the sum (V.sub.SS +V.sub.DF) of the negative operating voltage V.sub.SS and voltage drop V.sub.DF. Thus, the rectification range achieved with the rectifier shown in the paper is limited.

As has been described above, the present invention provides a full wave rectifier suited for the MOS IC fabrication using a depletion type MOS FET to achieve a wider range of rectification.