Modulation Circuit of a Digital-to-Analog Converter

The present invention relates to a modulation circuit of a digital-to-analog converter.

When conventional digital-to-analog conversion (D/A conversion) is executed, digital codes are converted to a pulse or a pulse train having a predetermined pulse width in a predetermined conversion period.

In FIG. 1, a digital circuit 1 outputs bit data D.sub.N -D.sub.1 each bit of which is generated from each of terminals D.sub.NT -D.sub.1T, and this bit data D.sub.N -D.sub.1 to be converted to analog data is input to a modulation circuit 3 of a digital-to-analog (D/A) converter 10. Each bit of digital data (digital codes) D is each output from the terminals D.sub.NT -D.sub.1T. For example, when N=5 (bits), D=D.sub.5 D.sub.4 D.sub.3 D.sub.2 D.sub.1. A binary counter 2 outputs signals Q.sub.N -Q.sub.1 for preparing timing signals for the D/A conversion, and the signals Q.sub.N -Q.sub.1 are input to the modulation circuit 3. A clock signal .phi. is inputted to the binary counter 2 to decide a minimum unit time of the D/A conversion. The modulation circuit 3 outputs an output voltage V.sub.P comprising a pulse or a pulse train having a predetermined pulse width as a whole in a predetermined conversion period in accordance with the bit data D.sub.N - D.sub.1 and the signals Q.sub.N -Q.sub.1. The level of the output voltage V.sub.P is converted to the level of an output voltage V.sub.L by a level conversion circuit 4 to finally obtain an output voltage V.sub.A as analog data having a proper voltage level through an integration circuit 5.

FIG. 2 shows a relationship between a clock signal .phi. and signals Q.sub.N -Q.sub.1 of the binary counter 2 when N=5 (bits). In this example, N is set to 5 for convenience in explaining the D/A conversion system of the present invention. When N=5 (bits), a conversion period T is 32t(=2.sup.5 t). (t: a minimum unit time for the D/A conversion)

Pulse width modulation (PWM) and pulse number modulation (PNM) are known as conventional methods for preparing the output voltage V.sub.P as shown in FIG. 3. Pulse width modulation enables the output voltage V.sub.P to output as a continuous pulse. Pulse number modulation enables output voltage V.sub.P to output as a combination of pulse trains with the minimum unit time t as a unit width. In pulse number modulation, though the pulse number of the output voltage V.sub.P increases between D=00001 and D-10000, the pulse number of the output voltage V.sub.P decreases between D=10001 and D=11111 because the waveform of the output voltage V.sub.P of D=00001-D32 01111 are superimposed on the waveform of the output V.sub.P of D=10000.

The high level period T.sub.P of the output voltage V.sub.P of the same digital data D within the conversion period T in the above methods occupies a same period, so that the value of analog data V.sub.A in the both methods is identical. The high level period T.sub.P is expressed as follows.

Accordingly, in the both methods, the same digital data is converted as a pulse or a pulse train with an identical pulse width as a whole within the conversion period T.

However, the above methods have problems as follows. In the pulse width modulation, if a time constant of the integration circuit 5 is not large, a ripple is added to the waveform of the output voltage V.sub.A as analog data. Conversely, if the time constant is set large, a response against the bit data D.sub.N -D.sub.1 become improper.

In the pulse number modulation, on the contary, a time constant may be selected to be smaller than the time constant of the integration circuit 5 in the pulse width modulation except the maximum region and the minimum region of the digital data D. But, as shown in FIG. 4, an actual waveform (a) of the output voltage V.sub.P shows a rise time (tr) and a fall time (tf). When the level of the actual waveform (a) of the output voltage V.sub.P is converted by 50% of an amplitude, the level converted waveform (b) (the actual waveform (b) of the output voltage V.sub.L) is output. Width error (.DELTA.t) between the actual waveform (b) and a theoretical waveform (c) of the output voltage V.sub.L is inevitably produced and expensed as follows. ##EQU1## As this width error (.DELTA.t) becomes an error of one pulse, the width error of the digital data at D=10000 becomes a maximum as shown in FIG. 5. The width error (.DELTA.t) varies in accordance with the digital data value. If the value of the width error (.DELTA.t) shows an identical value, the width error can be compensated externally. On the contary, the width of the pulse width modulation shows as an identical value regardless of the digital data value.

An object of the present invention is to provide an improved modulation circuit of a D/A converter for modulating digital data by using a combination of pulse number modulation and a pulse width modulation.

An another object of the present invention is to provide an improved modulation circuit of D/A converter which produces only a constant width error in normal operation.

Other objects and further scope of applicability of the present invention will become apparent from the detailed description give hereinafter. It should be understood, however, that the detailed description of and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.

According to an embodiment of the present invention, a modulation circuit of a D/A converter comprises pulse number modulation means for modulating some bits of digital data and for dispersing one or more resultant pulses, pulse width modulation means for modulating the remaining bits of the digital data and for dividing pulses in a resultant pulse train and combination means for combining and positioning at least one pulse in the pulse train formed by the pulse width modulation means adjacent the resultant pulse or pulses formed by the pulse number modulation means.

The present invention will be better understood from the detailed description given hereinbelow and the accompanying drawings which are given by way of illustration only, and thus are not limitative of the present invention and wherein:

FIG. 1 is a block diagram of a fundamental D/A conversion system;

FIG. 2 is a relationship between a clock signal .phi. and signals Q.sub.N -Q.sub.1 of a binary counter when N=5 (bits);

FIG. 3 is a timechart of waveforms of an output voltage V.sub.P of the conventional conversion methods;

FIG. 4 is a timechart of signals in the conventional D/A conversion system;

FIG. 5 shows a graph representative of width error in pulse number modulation;

FIG. 6 is a circuit diagram of an embodiment of a modulation circuit of a D/A conversion circuit of the present invention;

FIG. 7 is a timechart of waveforms of an output voltage V.sub.P of an embodiment of the present invention; and

FIG. 8 shows a graph representative of width error in a modulation circuit of a D/A converter of the present invention.

FIG. 6 is a circuit diagram of a modulation circuit of a D/A converter of the present invention. FIG. 7 is a timechart of waveforms of an output voltage V.sub.P.

The following is an explanation of the D/A conversion when N=5 (bits). In the embodiment of the present invention, lower 2 bits in 5 bits of digital data (digital codes) are modulated by a pulse mumber modulation, and upper 3 bits are modulated by a pulse width modulation, and then these modulated results are combined to convert to anlog data.

In FIG. 6, the signals Q.sub.1 -Q.sub.5 and the clock signal .phi. as shown in FIG. 2 are used. AND gates A.sub.1 and A.sub.2 modulate bit data D.sub.1 and D.sub.2 as the lower 2 bits by the pulse number modulation. The bit data D.sub.1 and the signals Q.sub.5, Q.sub.4, Q.sub.3, Q.sub.2 and Q.sub.1 are inputted to the AND gate A.sub.1. The bit data D.sub.2 and the signals Q.sub.4, Q.sub.3, Q.sub.2 and Q.sub.1 are inputted to the AND gate A.sub.2. The outputs of the AND gates A.sub.1 and A.sub.2 are output as an output voltage V.sub.P via an OR gate O.sub.1.

Bit data D.sub.3, D.sub.4 and D.sub.5 of the upper 3 bits are inputted to an OR gate O.sub.2. When either of the bit data D.sub.3, D.sub.4 and D.sub.5 is high, the OR gate O.sub.2 outputs as output at a timing when Q.sub.3 Q.sub.2 Q.sub.1 ="HIGH" under the control by an AND gate A.sub.3. The output of the AND gate A.sub.3 is inputted to a D-type flip-flop F/F having a clock signal .phi. via an OR gate O.sub.3, so that the output of the AND gate A.sub.3 is delayed by a single clock. The delayed output of the D-type flip-flop F/F is entered into the OR gate O.sub.1, so that the OR gate O.sub.1 outputs the output voltage V.sub.P. The outputs from the D-type flip-flop F/F at t=1, 9, 17, 25 are used as the base of the pulse width modulation of the upper 3 bits. At least one of pulses from D-type flip-flop F/F is neighbored with a pulse or pulses dispersed within a period T by the pulse number modulation of the lower 2 bits. When the bit data D.sub.1 =D.sub.2 =0, the OR gate O.sub.1 outputs only the output from the D-type flip-flop F/F as the output voltage V.sub.P.

Initially, at t=0, (or 8, 16, 24), when D.sub.3 or D.sub.4 or D.sub.5 =1, the output of the AND gate A.sub.3 is inputted into the OR gate O.sub.3, so that the OR gate O.sub.3 receives the high level signal from the AND gate A.sub.3 and the low level signal from an AND gate A.sub.4. The OR gate O.sub.3 outputs the high level signal, so that the D-type flip-flop F/F is set and the set condition of the D-type flip-flop F/F is continued until the AND gate A.sub.4 outputs the next low level signal. The D-type flip-flop F/F outputs an output delayed by a single clock. The AND gate A.sub.4 outputs the low level signal when the AND gate A.sub.4 receives the low level signal from an NAND gate NA.sub.1. Then, the OR gate O.sub.3 receives the low level signal from the AND gate A.sub.4 and the low level signal from the AND gate A.sub.3, so that the OR gate O.sub.3 outputs to low level signal into the D-type flip-flop F/F. Responsive to the low level signal fom the OR gate O.sub.3, the D-type flip-flop F/F is reset, so that the D-type flip-flop F/F outputs the low level signal until the AND gate A.sub.3 outputs the next high level signal. Thus, the output of the NAND gate NA.sub.1 defines the reset timing of the D-type flip-flop F/F and the width of the high level interval of the output voltage V.sub.P. When t=0, 8, 16, 24, the same operations are repeated at four times. Accordingly, the pulse train within the period T is divided to four pulses for the pulse width modulation of the upper 3 bits. Exclusive NOR gates X.sub.1, X.sub.2 and X.sub.3, the NAND gate NA.sub.1 and the AND gate A.sub.4 control the input of the D-type flip-flop F/F after the level of the signals Q.sub.3 Q.sub.2 Q.sub.1 ="HIGH"(t=0,8,16,24).

The signal Q.sub.1 and the bit data D.sub.3 are inputted to the exclusive NOR gate X.sub.1, and the signal Q.sub.2 and the bit data D.sub.4 are inputted to the exclusive NOR gate X.sub.2, and the signal Q.sub.3 and the bit data D.sub.5 are inputted to the exclusive NOR gate X.sub.3.

The outputs of the exclusive NOR gates X.sub.1, X.sub.2 and X.sub.3 are inputted to the NAND gate NA.sub.1 to detect a predetermined timing after the level of the signalsQ.sub.3 Q.sub.2 Q.sub.1 ="HIGH". The timing signals are output in accordance with the contents of the bit data D.sub.3, D.sub.4 and D.sub.5. When all pairs of the bit data D.sub.3 and the signal Q.sub.1, the bit data D.sub.4 and the signal Q.sub.2, the bit data D.sub.5 and the signal Q.sub.3 are equal, respectively, the level of the timing signal is low. When at least one pair of the bit data D.sub.3 and the signal Q.sub.1, the bit data D.sub.4 and the signal O.sub.2, the bit data D.sub.5 and Q.sub.1 are not equal, the level of the timing signal is high. For example, the output of the NAND gate NA.sub.1 is low only when D.sub.5 D.sub.4 D.sub.3 =001(t =1,9,17,25),=010(t=2, 10, 18, 26), and =011(t=3, 11, 19, 27) and the like. The output of the NAND gate NA.sub.1 is inputted to the AND gate A.sub.4 with the output of the D-type flip-flop F/F. The output of the AND gate A.sub.4 is inputted to the input terminal of the D-type flip-flop F/F via the OR gate O.sub.3.

As described above, when the level of either of the bit data D.sub.3, D.sub.4 and D.sub.5 as the upper 3 bits shows high, the high level signal of the output voltage V.sub.P is delayed by a single clock of the D-type flip-flop F/F, and after that, the input terminal of the D-type flip-flop F/F is controlled according to the contents of the bit data D.sub.3, D.sub.4 and D.sub.5. The high level of the output voltage V.sub.P is continued until the D-type flip-flop F/F receives a low signal by the clock signal .phi..

A pulse chain is divided to 4 parts to modulate the upper 3 bits by the pulse width modulation. The pulse width of the 4 pulses increase or decrease by the bit data D.sub.3, D.sub.4 and D.sub.5, based on the first delayed output (the high level signals from the D-type flip-flop F/F at t=1, 9, 17, 25).

Pulses produced by the pulse number modulation with the lower 2 bits generates from the OR gate O.sub.1 in accordance with the timing before delayed. This pulse number modulation results are connected and combined with any four pulses modulated by the pulse width modulation, depending on the form of the lower 2 bits. The pulse width of the combined pulses which are defined by the lower 2 bits is increased as such.

FIG. 8 shows a graph representative of width error property when N=5 (bits). The pulse number is constant except the minimum region and the maximum region of the digital data D, for example, when N=5 (bits), the pulse number 4. The width error is a constant error 4.times..DELTA.t in a normal condition. Four dispersed pulses are present within the period T, and the time constant of the integrated circuit may be small.

A tuning voltage for supplying to a tuner of the television set needs to be high precise voltage about 13 bits. Accordingly, the modulation circuit of the D/A converter of the present invention can be usefully used as an electronic tuning technique.

In the present invention, all of N bit data are not needed to divide to upper m bits and lower n bits (N=n+m), for example, some bits can be used as fixed bit data.

The invention being thus described, it will be obvious that the same may be varied in many ways. Such variations are not to be regarded as a departure from the spirit and scope of the invention, and all such modifications are intended to be included within the scope of the following claims.