Power Supply Switching Circuit

1. Field of the Invention

This invention generally relates to a semiconductor circuit and particularly to a power supply switching circuit suitable for use in a device which requires a high supply voltage only during programming, such as an erasable programmable read only memory (EPROM) and an electrically erasable programmable read only memory (EEPROM).

2. Description of the Prior Art

In EPROMs and EEPROMs, a high voltage V.sub.pp of 20-21 V is typically required during programming as an internal supply voltage and a voltage V.sub.cc of typically 5 V is required as an internal supply voltage during read out operation. A V.sub.pp pin provided as one of the terminals of a packaged semiconductor device, such as an EPROM and EEPROM, was first used exclusively for application of V.sub.pp voltage to be used for programming and it was not used for application of a signal having other voltage levels. Moreover, the EPROM ordinarily had an N-channel MOS (Metal-Oxide-Semiconductor) structure and thus its internal power supply switching circuit was also constructed by N-channel MOS transistors. However, with an improvement in density and an increase of memory capacity, there has recently been developed an EPROM having a CMOS (Complementary MOS) structure so as to reduce the amount of power consumption. In order to prevent the number of pins from increasing due to such an increase in memory capacity, it has come to use the same single pin for the application of programming voltage V.sub.pp and mode control signal, which is called V.sub.pp /READ pin. During programming or write operation, high voltage V.sub.pp is applied to the V.sub.pp /READ pin; on the other hand, during read out operation, a mode control signal of 0-5 V is applied to this pin. With the adoption of CMOS structure, an internal power supply switching circuit must also be constructed in the form of CMOS structure.

FIG. 1 illustrates a prior art power supply switching circuit having a CMOS structure. As shown, the circuit includes an input terminal 11 to which a supply voltage of V.sub.cc is applied. The terminal 11 is connected to a drain electrode of N-channel enhancement transistor 20. The circuit includes another input terminal 12 for receiving another supply voltage of V.sub.pp. The terminal 12 is connected to a drain electrode of N-channel enhancement transistor 19. The source electrodes of transistors 19 and 20 are commonly connected to an output terminal 14. The circuit of FIG. 1 includes a further input terminal 13 to which a power supply switching control signal PRG is applied. This terminal 13 is connected to a gate electrode of transistor 20 which is thus turned on if PRG signal is high thereby causing the voltage level at the terminal 14 to be V.sub.cc '. On the other hand, the terminal 13 is also connected to a gate electrode of N-channel transistor 18 through a reverse current preventing transistor 15 and a CMOS inverter comprised of a pair of P-channel and N-channel transistors 17 and 18, and, thus, if PRG signal is low, the transistor 17 is turned on thereby causing the gate voltage of transistor 19 to be V.sub.pp, so that the transistor 19 is also turned on to set the voltage level at the terminal V.sub.pp to be V.sub.pp '.

The CMOS inverter is comprised by the transistors 17 and 18 which are series-connected, and the transistor 17 has its source electrode connected to the V.sub.pp supply voltage with the source electrode of transistor 18 connected to ground. The transistors 17 and 18 defining a CMOS inverter have their gate electrodes commonly connected to the source electrode of N-channel transistor 15 and also to the drain electrode of P-channel transistor 16. The transistor 16 has its source electrode connected to receive the V.sub.pp supply voltage and its gate electrode connected to the drain electrode of each of transistors 17 and 18. Thus, if PRG signal is high, the voltage at the gate electrode of each of the transistors 17 and 18 is set at V.sub.pp thereby causing the transistor 17 to be turned off and the transistor 18 to be turned on. That is, the voltage at the gate electrode of transistor 19 is set at 0 V to have the transistor 19 turned off.

The transistor 15 has its source electrode connected to the input terminal 13 and its gate electrode connected to receive the supply voltage V.sub.cc, and it serves to prevent a reverse current, corresponding to V.sub.cc level or more, from being supplied to the terminal 13. The above-described circuit is typically constructed on a P-conductivity type substrate, which is to be connected to ground while operation, using the well-known CMOS process. Thus, the voltage at the substrate of N-channel transistors 15, 18, 19 and 20 is at ground level. On the other hand, the P-channel transistors 16 and 17 are formed in an N-well and the substrate voltage of these transistors 16 and 17 is set at V.sub.pp by having the source electrode connected to the substrate in each of these transistors 16 and 17.

In the circuit of FIG. 1, output voltages at the output terminal 14 may be switched by controlling the conditions of transistors 19 and 20 depending on the state of PRG signal. However, the output voltage from each of the transistors 20 and 19 becomes reduced from V.sub.cc and V.sub.pp by the amount of threshold voltage drop. That is, if PRG signal is high, the voltages at the gate and drain electrodes of transistor 20 are both at V.sub.cc and its source voltage V.sub.cc ' as an output voltage becomes V.sub.cc '=V.sub.cc -V.sub.T1, where V.sub.T1 is a threshold voltage of transistor 20. On the other hand, if PRG signal is low, the gate and drain voltages of transistor 19 are both at V.sub.pp so that its source voltage V.sub.pp ' as an output voltage becomes V.sub.pp '=V.sub.pp -V.sub.T2, where V.sub.T2 is a threshold voltage of transistor 19. Furthermore, since the substrates of transistors 19 and 20 are connected to ground, the threshold voltages V.sub.T1 and V.sub.T2 of these transistors contain the so-called body effect components V.sub.T1 and V.sub.T2. Since these body effect components increase more as the output voltage becomes higher, so that the effects of voltage drop, in particular, at the transistor 19 which carries out switching of high voltage V.sub.pp cannot be neglected.

FIG. 2 shows another prior art circuit directed to prevent the occurrence of a voltage drop in output voltage as described above. As shown, the circuit of FIG. 2 is constructed by substituting the transistor 19 of FIG. 1 with a P-channel transistor 19' whose source electrode is connected to the substrate and to the input terminal 12 and whose drain electrode is connected to the output terminal 14 with the gate electrode connected to the drain electrode of transistor 17. The circuit of FIG. 2 includes an input terminal 13' to which PRG signal is applied. In such a structure, it is true that a voltage drop may be prevented from occurring; however, if 0 V is applied to the terminal 12 as a mode control signal with the PRG signal being low ( during read out operation ), a forward bias is established between the drain electrode and the N-well substrate of P-channel transistor 19' because the voltage at the drain electrode of transistor 19' becomes V.sub.cc even though the source electrode and N-well susbtrate of transistor 19' are set at 0 V, so that there appears a problem of current flow toward the terminal 12.

It is therefore a primary object of the present invention to obviate the disadvantages of the prior art as described above and to provide an improved power supply switching circuit.

Another object of the present invention is to provide a semiconductor power supply switching circuit capable of supplying two or more supply voltages different in level selectively without producing a voltage drop.

A further object of the present invention is to provide a semiconductor power supply switching circuit capable of supplying two or more supply voltages different in level selectively without producing leakage current.

A still further object of the present invention is to provide a semiconductor device having at least one pin which is used for application of two or more voltages different in level selectively.

Other objects, advantages and novel features of the present invention will become apparent from the following detailed description of the invention when considered in conjunction with the accompanying drawings.

FIGS. 1 and 2 are circuit diagrams showing typical prior art power supply switching circuits;

FIGS. 3 through 6 are circuit diagrams showing various embodiments of the present invention when applied to a programming voltage switching circuit of EPROM; and

FIG. 7 is a graph showing a wave form of V.sub.pp /READ signal.

Referring now to FIG. 3, there is shown a power supply voltage switching circuit embodying the present invention, which is constructed in the form of CMOS structure and which includes separate pins for programming voltage V.sub.pp and mode control signal PRG. Thus, with this structure, switching between internal power supply voltages is carried out by the mode control signal PRG under the condition that high voltage V.sub.pp is being applied to the V.sub.pp pin. It is to be noted that a programming mode is established by the PRG signal being high and a read out mode is established by the PRG signal being low. In the circuit of FIG. 3, there is provided a mode control signal input terminal 44 which is connected to a mode control signal pin (not shown) and which is connected to a switching signal input terminal 23 of power supply switching circuit 30 through an inverter 42 and also to another switching signal input terminal 24 through a composite inverter circuit 43 indicated by the dotted line.

If the input signal PRG applied to the mode control signal input terminal 44 is high, the low state is established at the terminals 23 and 24 so that the power supply switching circuit 30 supplies V.sub.pp at its output terminal 25. On the other hand, if the PRG signal applied to the terminal 44 is low, then a power supply voltage of V.sub.cc is supplied to the output terminal 25. It is to be noted that with respect to the elements of the composite inverter circuit 43 in FIG. 3, those elements which are identical to those shown in FIG. 1 are indicated by the identical numerals. Thus, the transistor 15 is provided to prevent reverse current and the transistor 16 is provided to turn the transistor 18 off, which defines, together with the transistor 17, a CMOS inverter.

The power supply switching circuit 30 includes a V.sub.cc power supply terminal 21 and a V.sub.pp power supply terminal 22 which are electrically connected to a V.sub.cc pin and a V.sub.pp pin (not shown) of EPROM, respectively. Between the V.sub.cc terminal 21 and output terminal 25 is provided a pair of P-channel transistors 35 and 33 as connected in series, and similarly between the V.sub.pp terminal 22 and output terminal 25 is provided a pair of P-channel transistors 31 and 32 as connected in series. Since the EPROM of the present embodiment is constructed in a substrate of P conductivity type, the P-channel transistors 31, 32, 33 and 35 mentioned above are formed in N-wells. N-wells 31c and 35c of transistors 31 and 35 are electrically connected to V.sub.pp power supply terminal 22 and V.sub.cc power supply terminal 21, respectively, through their respective source electrodes 31a and 35a. Moreover, the transistors 32 and 33 have their N-wells 32c and 33c commonly connected to the output terminal 25 through their respective drain electrodes 32b and 33b.

The transistor 31 has its gate electrode connected to the terminal 24 and the transistor 32 has its gate electrode connected to the terminal 23, which is also connected to the gate electrode of N-channel transistor 34. The transistor 31 has its drain electrode 31b connected to the source electrode 32a of transistor 32, to the drain electrode of transistor 34 and also to the gate electrode of transistor 33. There is also provided an N-channel transistor 36 which has its drain and gate electrodes connected to the V.sub.cc power supply terminal 21 and its source electrode connected not only to the output terminal 25 but also to an inverter 37 at its input terminal. The inverter 37 has its output terminal connected to the gate electrode of transistor 35.

Now, the operation of the power supply switching circuit shown in FIG. 3 will be described. In the first place, the state of each of the transistors and the voltage level at each of the terminals in each mode of operation will be shown in Table I below.

During write (programming) mode, the terminals 23 and 24 are maintained low thereby causing the transistors 31 and 32 to be turned on and the transistor 34 to be turned off, so that the voltage at the drain electrode 31b of transistor 31 becomes V.sub.pp, which causes the transistor 33 to be turned off to supply the power supply voltage V.sub.pp to the output terminal 25. In this case, since a voltage difference between the gate and source electrodes of transistor 31 remain unchanged at V.sub.pp, there is produced no threshold voltage drop at the transistor 31.

On the other hand, a voltage difference between the gate and source electrodes of transistor 32 gradually increases until V.sub.pp is reached passing beyond the threshold voltage, there is produced no threshold voltage drop at the transistor 32, either. Moreover, since the transistors 31 and 32 have their N-wells 31c and 32c connected to their source electrode 31a and drain electrode 32b, respectively, the body effect does not come into play.

During read mode of operation, the terminals 23 and 24 are maintained high to have the transistors 31 and 32 turned off and the transistor 34 turned on, so that the voltage at the drain electrode 31b of transistor 31 is at 0 V level, which causes the transistor 33 to be turned on thereby permitting the power supply voltage V.sub.cc to appear at the output terminal 25. Also in this case, a voltage difference between the gate and source electrodes at the transistors 33 and 35 remain unchanged at V.sub.cc, there is produced no threshold voltage drop at the transistors 33 and 35. Furthermore, the transistors 33 and 35 have their N-wells 33c and 35c connected to the drain electrode 33b and source electrode 35a, respectively, so that these transistors 33 and 35 are free of the so-called body effect.

When switching from the write mode to the read mode, even if the high state is established at the terminals 23 and 24, the transistor 32 remains on until the voltage at the terminal 25 due to the remaining charge becomes lower than a voltage determined by V.sub.cc +threshold voltage of transistor 32 while the remaining charge at the output terminal 25 flows to ground GND through the transistors 32 and 34. When the transistor 32 is turned off, the transistor 33 is turned on, so that current flows from the terminal 21 to the output terminal 25 thereby establishing the power supply voltage V.sub.cc at the output terminal 25. Moreover, even if 0 V is applied to the V.sub.pp terminal 22 during read out mode, since the transistor 32 remains off, the voltage at the drain electrode 31b of transistor 31 remains 0 V, so that there will be no reverse current flowing from the N-well 31c of transistor 31 to the V.sub.pp terminal 22 through the drain electrode 31b.

It is to be noted that in the circuit shown in FIG. 3, the output terminal 25 is at the low state at the time of application of power supply voltage V.sub.cc. When the power supply voltage V.sub.cc is applied, current starts to flow toward the output terminal 25 through the transistor 36 thereby gradually increasing the voltage at the output terminal 25. However, since the output terminal 25 is an internal power supply terminal which has a relatively large capacity, it takes time in increasing the voltage at the output terminal 25. The inverter 37 retains the high state at its output terminal thereby maintaining the transistor 35 cut off until the voltage at the output terminal 25 reaches a predetermined level. With this structure, a charge-up operation is carried out for the output terminal 25 by the transistor 36 until the voltage at the output terminal 25 increases to a predetermined level. This is because, since the voltage at the N-well 33c of transistor 33 is unstable while the voltage at the terminal 25 is unstable, it is preferable for the transistor 33 to receive no current during this unstable time period. Such a structure allows to effectively prevent the occurrence of latch-up phenomenon.

FIG. 4 illustrates another embodiment of the present invention, in which like numerals are used to indicate like elements in FIG. 3. The circuit of FIG. 4 is generally similar to the circuit of FIG. 3 excepting that use is made of an N-channel transistor 33' as a switching transistor for V.sub.cc in the embodiment shown in FIG. 4. As shown, in the present embodiment, the transistor 33' has its drain electrode connected to the V.sub.cc power supply terminal 21, its source electrode connected to the output terminal 25 and its gate electrode connected to the input terminal 23. With such a structure, if the high state is established at the terminal 23, the transistor 33' is turned on, but a voltage difference between its gate and source electrodes becomes smaller as the source voltage increases. And, since the drain voltage becomes saturated when the threshold voltage is reached, the output voltage V.sub.cc ' supplied at the output terminal 25 is lower than the original supply voltage V.sub.cc by the amount of threshold voltage. Thus, the circuit of FIG. 4 is directed to the situation in which a voltage drop in the path for supplying V.sub.cc may be neglected while preventing the occurrence of voltage drop in the path for supplying V.sub.pp. The circuit of FIG. 4 is also provided with the transistor 32 which serves to prevent the occurrence of reverse current even if 0 V is applied to the V.sub. pp terminal 22.

FIGS. 5 and 6 show other embodiments of the present invention, in which the V.sub.pp and mode control signal pins of an EPROM having a CMOS structure are consolidated into a single pin (V.sub.pp /READ pin). FIG. 7 is a graph showing the relation between the voltage level of V.sub.pp /READ signal and the mode of operation. As shown, the read out mode a is established when the voltage level of V.sub.pp /READ signal is at V.sub.L, the stand-by mode b is established when the voltage level is at V.sub.H, and the write mode c is established when the voltage level is at V.sub.pp. It is to be noted that the voltage level between V.sub.L and V.sub.H ranges between 0 and 5 V. The circuit indicated by the dotted line in each of FIGS. 5 and 6 is a high voltage detecting circuit 40 and it detects the level of the voltage at the V.sub.pp power supply terminal 22 which is connected to the V.sub.pp /READ pin. Since the high voltage detecting circuit 40 does not form part of the present invention, its detailed description will be omitted.

In either of the circuits shown in FIGS. 5 and 6, the write mode is maintained as long as power supply voltage V.sub.pp is applied to the terminal 22. The circuits shown in FIGS. 5 and 6 are constructed from the circuits shown in FIGS. 3 and 4, respectively, such that the terminals 23 and 24 are consolidated into a single terminal 28 which is connected to the output terminal of an inverter 41 defining the final stage of high voltage detecting circuit 40 with the omission of the composite inverter circuit 43. This is because, in the circuits shown in FIGS. 5 and 6, it is not necessary to have the transistor 31 turned off while voltage V.sub.pp is applied to the V.sub.pp terminal 22. It is to be noted that, in the circuits shown in FIGS. 5 and 6, like numerals are used to indicate like elements in the circuits shown in FIGS. 3 and 4.

As described above, in accordance with the present invention, there is provided a power supply switching circuit having a CMOS structure, which is capable of supplying two power supply voltages different in level, e.g., V.sub.pp and V.sub.cc, selectively as an internal power supply voltage. Moreover, in the power supply switching circuit embodying the present invention, there will be produced no reverse or leakage current even if the voltage at the V.sub.pp terminal becomes lower than V.sub.cc.

While the above provides a full and complete disclosure of the preferred embodiments of the present invention, various modifications, alternate constructions and equivalents may be employed without departing the true spirit and scope of the invention. Therefore, the above description and illustration should not be construed as limiting the scope of the invention, which is defined by the appended claims.