US 4,564,901 AGrant
Method of Performing a Sequence of Related Activities via Multiple Asynchronously Intercoupled Digital Processors
Issue Date:1986-01-14
•10 Claims
•9 Drawing Sheets
Abstract
A method of performing a sequence of related activities in multiple digital processors includes the steps of: executing a portion of a first activity of the sequence in a first processor and then executing an INTERPROCESSOR CALL instruction to a second activity in a second processor; suspending execution of the first activity in response to the CALL and signaling the second processor that the second activity has been called by the first activity; completely executing the second activity in the second processor and then executing an INTERPROCESSOR NEXT instruction to a third activity in a third processor; signaling the third processor in response to the NEXT instruction that the third activity has been called not by the second activity but by the caller of the second activity; and completely executing the third activity in the third processor and, upon completion thereof, signaling the third activity's caller to resume execution of the suspended activity.
Metadata
Assignee
- Burroughs Corporation
Inventors
- Christopher J. Tomlinson
- Howard H. Green
Application Information
Application Number:US 5158524
Filing Date:1983-07-21
Priority Date:1983-07-21
Art Unit:232
Classifications
IPC:
G06F 942G06F 946G06F 1516
Field of Search:
364900 MS File;200 MS File;300
Patent Drawings (9 sheets)
Description
Background of the Invention
This invention relates to digital computers, and more particularly, it relates to digital computer systems in which a plurality of independent processors interact to perform respective activities within various tasks.
Conventionally, a data processing task is performed in its entirety by a single computer. That task, for example, may be the solving of a scientific problem, the calculation of a payroll, etc. But in any case, the speed at which the task is performed by the single computer depends directly upon the number of data bits that the computer can process in a single cycle and the speed of that cycle.
Thus, the computing power of a single computer conventionally is increased by either increasing the number of bits which the computer can operate on in a single cycle or by shortening the computer's cycle time. However, the extent to which the cycle time can be shortened is limited by the speed at which integrated circuits operate. And increasing the number of bits on which a computer can operate in a single cycle also causes the complexity of the computer's design and maintenance to increase.
Alternatively, the speed at which a data processing task is performed may be increased by providing a plurality of independent processors each of which performs one or more activities within the task. In such a multiprocessor system, the individual processors can be tailored to perform their respective activities which decreases the execution time of the overall task. Further, the individual processors of the system inherently make the system modular, which reduces the complexity of the system's design and maintenance.
Also, in the multiprocessor system, the various processors can perform activities for several unrelated tasks at the same time. This allows for more parallelism within the system, which further increases the system's computing power.
However, in the multiprocessor system, some means must be provided for coordinating the various activities that the processors perform. That is, a means must be provided for keeping the execution of activities within a task in the correct sequence. And a means must be provided for keeping many processors active at the same time. But this becomes very complicated as the number of processors, number of tasks, and number of activities within each task increases.
Accordingly, a primary object of the invention is to provide a method of performing a task as a sequence of called activities in multiple independent digital processors, some of which are not returned to after the sequence is complete.
Brief Summary of the Invention
In the present invention, a method of performing a sequence of called activities in multiple independent processors such that some of the activities are not returned to when the sequence is complete includes the steps of: executing a portion of a first activity of the sequence in a first processor and then executing an INTERPROCESSOR CALL instruction to a second activity in a second processor; suspending execution of the first activity in response to the CALL and signaling the second processor that the second activity has been called by the first activity; completely executing the second activity in the second processor and then executing an INTERPROCESSOR NEXT instruction to a third activity in a third processor; signaling the third processor in response to the NEXT instruction that the third activity has been called not by the second activity but by the caller of the second activity; and completely executing the third activity in the third processor and, upon completion thereof, signaling the third activity's caller to resume execution of the suspended first activity.
Brief Description of the Drawings
Various features and advantages of the invention are described in the Detailed Description in conjunction with the accompanying drawings wherein:
FIG. 1 illustrates a system in which sequences of activities in digital processors are synchronized according to the invention;
FIG. 2 illustrates an exemplary arrangement of the processor records and activity records in the shared memory of the FIG. 1 system;
FIGS. 3, 4, 5, and 6 illustrate examples of how the pointers in the processor records and activity records of the FIG. 1 system change in response to the execution of INTERPROCESSOR CALL instructions, INTERPROCESSOR RETURN instructions, and INTERPROCESSOR NEXT instructions;
FIG. 7 illustrates another system for synchronizing sequences of activities within digital processors according to the invention; and
FIGS. 8A and 8B illustrate the detailed logic of a file access controller in the FIG. 7 system.
Detailed Description of the Invention
In FIG. 1, a plurality of "n" independent digital processors are represented by several boxes labeled P.sub.1, P.sub.2, . . . P.sub.n. These processors may be of any programmable type; and they may be the same or different from each other. Suitably, processors P.sub.1 through P.sub.n are of the type described in U.S. Pat. No. 4,346,438 entitled "Digital Computer Having Programmable Structure" by H. Potash et al and assigned to Burroughs Corporation, or of the type described in U.S. Pat. No. 4,327,355 entitled "Digital Device with Interconnect Matrix" by H. Potash et al and assigned to Burroughs Corporation.
Processors P.sub.1, P.sub.2, . . . P.sub.n are coupled to memories M.sub.1, M.sub.2, . . . M.sub.n respectively. These memories may be any digital type memory. For example, they may be static or dynamic type semiconductor memories; and they may be made of MOS or bipolar circuitry. Also, the storage capacity and operating speed of the memories may be the same or different from each other.
One portion of memory M.sub.1 contains the data that processor P.sub.1 operates on; while another portion of memory M.sub.1 contains the intraprocessor activities that processor P.sub.1 performs. As used herein, an intraprocessor activity is comprised of a program or set of programs which direct a processor to perform a particular task by using only the resources of that processor. Such resources include the processor's own internal hardware, the processor's memory, and any peripheral equipment such as disks, tapes, etc. (not shown) connected to the processor. In FIG. 1, the respective intraprocessor activities that processor P.sub.1 performs are symbolically indicated as A.sub.1 P.sub.1, A.sub.2 P.sub.1, . . . , etc.
Similarly, a portion of memory M.sub.2 contains the data that processor P.sub.2 operates on; and another portion of memory M.sub.2 contains the intraprocessor activities that processor P.sub.2 performs. Those activities are indicated in FIG. 1 as A.sub.1 P.sub.2, A.sub.2 P.sub.2, . . . , etc. In like fashion, memory M.sub.n contains the data that processor P.sub.n operates on; and it contains the intraprocessor activities A.sub.1 P.sub.n, A.sub.2 P.sub.n, . . . that processor P.sub.n performs.
Each of the memories M.sub.1, M.sub.2, . . . M.sub.n also contains interprocessor instructions. They are an INTERPROCESSOR CALL, an INTERPROCESSOR RETURN, and an INTERPROCESSOR NEXT instruction. In general, these interprocessor instructions provide the means by which the processors P.sub.1, P.sub.2 . . . P.sub.n communicate with one another. More specifically, they provide the means by which all of the intraprocessor activities A.sub.1 P.sub.1, A.sub.1 P.sub.2 . . . A.sub.1 P.sub.n, etc. are linked together and performed in an orderly synchronized sequence as is explained in much greater detail below.
Processors P.sub.1, P.sub.2, . . . P.sub.n are coupled via a single time-shared bus to an intelligent memory controller IMC; and controller IMC is coupled to a shared memory SM. Controller IMC preferably is a programmable computer of the type referenced above; and memory SM may be any type of read/write memory.
Memory SM contains one separate processor record for each of the processors; and each such record is herein indicated as PR.sub.i. Memory SM also contains a separate activity record for each of the intraprocessor activities in the processors; and each such record is indicated as AR.sub.x P.sub.i. Further, memory SM contains parameters that are shared and passed from one processor to another via the interprocessor instructions.
Included in each processor record PR.sub.i are flags which indicate whether processor P.sub.i is currently BUSY performing an activity or NOT BUSY. Processor record PR.sub.i also contains a CURRENT entry which points to the current intraprocessor activity that processor P.sub.i is performing if the processor is BUSY.
Processor record PR.sub.i further includes a PROCESSOR QUEUE HEAD entry (PQH), and a PROCESSOR QUEUE TAIL entry (PQT). These two entries respectively point to the head and tail of a queue of activity records for the different kinds of intraprocessor activities that processor P.sub.i is to perform. That is, a pointer to the same kind of activity is entered into the processor queue only once even though that activity may be called several times. Processor record PR.sub.i may also include other entries, as a matter of design choice, in addition to those described above.
Activity record AR.sub.x P.sub.i includes a set of flags indicating when the corresponding activity is DORMANT, or ACTIVE, or SUSPENDED. An activity is ACTIVE when a processor is actually being used to execute that activity. An activity remains ACTIVE but in a SUSPENDED state when it has executed partway to completion and then stopped while it awaits the results of another activity in another processor. Such results are requested and obtained via the INTERPROCESSOR INSTRUCTIONS. In all other cases, an activity is DORMANT.
Activity record AR.sub.x P.sub.i also includes a CALLER entry which is a pointer to the activity record of the activity which is first to call activity A.sub.x P.sub.i. Any subsequent callers of activity A.sub.x P.sub.i are kept track of by means of an ACTIVITY QUEUE TAIL entry (AQT) and ACTIVITY QUEUE HEAD entry (AQH) in the activity record.
Specifically, pointers to the subsequent callers of activity A.sub.x P.sub.i are placed in a queue of that activity. Entry AQH points to the activity record of the second caller of activity A.sub.x P.sub.i ; and entry AQT points to the activity record of the last caller of activity A.sub.x P.sub.i. Intermediate entries in either the activity queue or the processor queue are linked together by a NEXT IN QUEUE entry (NIQ) in the activity records of the various callers of an activity.
Activity record AR.sub.x P.sub.i also has a PARAMETER entry (PARAM) which contains a pointer to parameters that are passed between two activities via the INTERPROCESSOR INSTRUCTIONS. For example, when activity A.sub.x P.sub.i calls activity A.sub.y P.sub.j, then the PARAM entry of activity record AR.sub.x P.sub.i points to parameters in the shared memory SM on which activity A.sub.y P.sub.j is to operate. Conversely, when activity A.sub.y P.sub.j completes, then the PARAM entry in activity record AR.sub.x P.sub.i points to parameters in the shared memory that are being passed by activity A.sub.y P.sub.j to activity A.sub.x P.sub.i.
One example of a complete set of the processor records and activity records for a FIG. 1 system is illustrated in FIG. 2. In this example, there are eleven processor records PR.sub.1 through PR.sub.11 which respectively represent eleven physical processors P.sub.1 through P.sub.n. Also in this example, the number of activities that each processor performs varies from processor to processor.
FIG. 2 shows that processor 1 performs five intraprocessor activities; and the above-described pointers for those activities are respectively in activity records AR.sub.1 P.sub.1 through AR.sub.5 P.sub.1. In like manner, FIG. 2 shows that processor 2 performs eleven intraprocessor activities, processor 3 performs nine intraprocessor activities, processor 4 performs three intraprocessor activities, etc. Again, these activity records and processor records each have their own pointers that keep track of which activity is calling which; and resolve the order by which the various processors perform their respective intraprocessor activities.
Consider now the details of the operations that are performed by the controller IMC in response to the INTERPROCESSOR CALL instruction. TABLE 1 below lists those operations for the generalized case where activity A.sub.x P.sub.i in processor P.sub.i calls activity A.sub.y P.sub.j in processor P.sub.j.
If activity A.sub.y P.sub.j is DORMANT and processor P.sub.j is NOT BUSY, then controller IMC performs the following tasks. First it makes activity A.sub.y P.sub.j ACTIVE by setting the ACTIVE flag in activity record AR.sub.y P.sub.j. Then it loads a pointer to activity record AR.sub.x P.sub.i into the CALLER entry of activity record AR.sub.y P.sub.j. Also, a pointer to activity record AR.sub.y P.sub.j is loaded into the CURRENT entry of processor record PR.sub.j. Then the BUSY flag for processor record PR.sub.j is set, and a message is sent to processor P.sub.j which notifies it to start performing activity A.sub.y P.sub.j.
If, however, activity A.sub.y P.sub.j is DORMANT and processor P.sub.j is BUSY at the time of the INTERPROCESSOR CALL, then controller IMC operates as follows. First it sets the ACTIVE flag in activity record AR.sub.y P.sub.j. Then it loads a pointer to activity record AR.sub.x P.sub.i into the CALLER location of activity record AR.sub.y P.sub.j. Then it loads a pointer to activity record AR.sub.y P.sub.j into the queue of processor record PR.sub.j. This latter operation involves loading a pointer to activity record AR.sub.y P.sub.j into the NEXT IN QUEUE entry of the activity record that is pointed to by the PROCESSOR QUEUE TAIL of processor record PR.sub.j ; and then changing the PROCESSOR QUEUE TAIL entry of processor record PR.sub.j such that it also points to activity record AR.sub.y P.sub.j.
Finally, if activity A.sub.y P.sub.j is ACTIVE at the time of the INTERPROCESSOR CALL, then the intelligent memory controller loads a pointer to activity record AR.sub.x P.sub.j into the queue of activity record AR.sub.y P.sub.j. This involves loading a pointer to activity record AR.sub.x P.sub.i into the NEXT IN QUEUE entry of the activity record that is pointed to by the ACTIVITY QUEUE TAIL of activity record AR.sub.y P.sub.j ; and then changing the ACTIVITY QUEUE TAIL in activity record AR.sub.y P.sub.j to point to activity record AR.sub.x P.sub.i.
Note that the above operations only affect the CALLED activity record and CALLED processor record. But in addition, various operations must also be performed on the CALLING activity record and CALLING processor record. These operations are as follows.
If the queue in the CALLING processor record PR.sub.i is NOT EMPTY, then one entry is removed from that queue and loaded into the CURRENT entry of processor record PR.sub.i. This unloading operation involves moving the PROCESSOR QUEUE HEAD entry of processor record PR.sub.i into the CURRENT entry of processor record PR.sub.i ; and then the NEXT IN QUEUE entry from the activity record that is pointed to by the PROCESSOR QUEUE HEAD in processor record PR.sub.i is loaded into the PROCESSOR QUEUE HEAD of processor record PR.sub.i. Also, a message is sent by the controller IMC to processor P.sub.i which notifies that processor of the new activity that is pointed to by the CURRENT entry in the processor record PR.sub.i.
If, on the other hand, the queue in processor record PR.sub.i is EMPTY, then the flags in that processor record are set to indicate that processor P.sub.i is NOT BUSY. Also, under those conditions, the CURRENT entry in processor record PR.sub.i is set to a null value. Note further that in both this and the above case, the ACTIVE flag in the calling activity record AR.sub.x P.sub.i remains set, even though the calling activity is in a suspended state.
Next, consider the operations that are performed by the controller IMC in response to an INTERPROCESSOR RETURN instruction from one of the processors. Specifically, consider the case where activity A.sub.y P.sub.j in processor P.sub.j RETURNS to activity A.sub.x P.sub.i in processor P.sub.i. These operations are listed in TABLE 2 below.
If the queue of activity record AR.sub.y P.sub.j is NOT EMPTY when the RETURN occurs, then the controller IMC performs the following operations. Firstly, one entry is removed from the queue of activity record AR.sub.y P.sub.j. This is achieved by moving the pointer in the ACTIVITY QUEUE HEAD of activity record AR.sub.y P.sub.j into the CALLER location of activity record AR.sub.y P.sub.j ; and moving the NEXT IN QUEUE entry of the activity record that is pointed to by the ACTIVITY QUEUE HEAD of activity record AR.sub.y P.sub.j into the ACTIVITY QUEUE HEAD of activity record AR.sub.y P.sub.j.
Thereafter, a message is sent to processor P.sub.j to re-execute activity A.sub.y P.sub.j for the new caller of that activity.
On the other hand, if the queue of activity A.sub.y P.sub.j is EMPTY but the queue of processor P.sub.j is NOT EMPTY when the RETURN instruction is sent to the controller IMC, then that controller performs the following operations. Firstly, the flags in activity record AR.sub.y P.sub.j are changed to indicate a DORMANT state. Then one entry is removed from the queue of the processor record PR.sub.j and the CURRENT entry in that processor record is updated with that entry that is removed from the queue. Then a message is sent to processor P.sub.j which informs the processor of the new activity record that is being pointed to by the CURRENT entry in processor record PR.sub.j.
Finally, if the queue of activity record AR.sub.y P.sub.j and the queue of processor record PR.sub.j are both EMPTY when the RETURN instruction is sent to the controller IMC, then there are no other activities for processor P.sub.j to currently perform. Consequently, the flags in processor record PR.sub.j are set to indicate that processor P.sub.j is NOT BUSY; and the CURRENT entry in processor record PR.sub.j is set to a null state.
All of the above operations for the RETURN instruction are performed on the CALLED activity record AR.sub.y P.sub.j and CALLED processor record PR.sub.j. In addition, the following operations are performed in response to the RETURN instruction on the CALLING activity record AR.sub.x P.sub.i and CALLING processor record PR.sub.i.
If the flags in the CALLING processor record PR.sub.i indicate that processor P.sub.i is BUSY, then the intelligent memory controller loads a pointer to activity record AR.sub.x P.sub.i into the queue of processor record PR.sub.i. This is performed, when the queue of processor record PR.sub.i is not empty, by loading the pointer to activity record AR.sub.x P.sub.i into the NEXT IN QUEUE entry of the activity record that is pointed to by the PROCESSOR QUEUE TAIL in processor record PR.sub.i ; and by changing the PROCESSOR QUEUE TAIL entry to also point to activity record AR.sub.x P.sub.i. And it is achieved, when the queue of processor record PR.sub.i is empty, by loading the pointer to activity record AR.sub.x P.sub.i into the PROCESSOR QUEUE HEAD and PROCESSOR QUEUE TAIL of processor record PR.sub.i.
If, however, processor P.sub.i is NOT BUSY, then the pointer to activity record AR.sub.x P.sub.i is loaded into the CURRENT entry of processor record PR.sub.i ; and the flags of processor record PR.sub.i are set to indicate that processor P.sub.i is BUSY. Then a message is sent to processor P.sub.i to notify the processor of the new activity that it is to perform as indicated by the new CURRENT entry in processor record PR.sub.i.
Consider now the operations that are performed by the controller IMC in response to an INTERPROCESSOR NEXT instruction from one of the processors. Specifically, consider the actions that are taken in the generalized case where activity A.sub.y P.sub.j in processor P.sub.j performs a NEXT instruction to activity A.sub.z P.sub.k in processor P.sub.k. These operations are listed in TABLE 3 below.
Those operations which are performed on activity record AR.sub.y P.sub.j and processor record PR.sub.j in response to the NEXT instruction are the same as the operations which are performed on activity record AR.sub.y P.sub.j and processor record PR.sub.j in response to the RETURN instruction as described above. But the operations that are performed in response to the NEXT instruction on activity record AR.sub.z P.sub.k and processor record PR.sub.k are as follows.
If activity A.sub.z P.sub.k is ACTIVE, then a pointer to activity record AR.sub.x P.sub.i gets loaded into the activity queue of activity record AR.sub.z P.sub.k. This is achieved by moving the CALLER entry of activity record AR.sub.y P.sub.k into the activity queue of activity record AR.sub.z.
If, however, activity A.sub.z P.sub.k is DORMANT and processor P.sub.k is BUSY at the time the NEXT instruction is sent to controller IMC, then that controller performs the following operations. First, a pointer to activity record AR.sub.z P.sub.k is loaded into the queue of processor record PR.sub.k. Then, the CALLER entry of activity record AR.sub.y P.sub.j (which is a pointer to
activity record AR.sub.x P.sub.i) is moved to the CALLER entry of activity record AR.sub.z P.sub.k. Then, the flags in activity record AR.sub.z P.sub.k are set to an ACTIVE state.
On the other hand, if processor P.sub.k is NOT BUSY at the time that the NEXT instruction is sent to the intelligent memory controller, then that controller performs the following operations. The pointer to activity record AR.sub.z P.sub.k is loaded into the CURRENT entry of processor record PR.sub.k. Also, the CALLER entry of activity record AR.sub.y P.sub.j (which is a pointer to activity record AR.sub.x P.sub.i) is loaded into the CALLER entry of activity record AR.sub.z P.sub.k. Then the flags in activity record AR.sub.z P.sub.k are set to an ACTIVE state.
Reference should now be made to FIG. 3. It illustrates an exemplary sequence of the above-described changes that occur to the processor records and activity records during a CALL and corresponding RETURN operation. That sequence occurs during time instants t.sub.1 through t.sub.5 ; and TABLE 4 below outlines the events which occur at each time instant.
In this example, there are two processors P.sub.x and P.sub.y ; and they have processor records PR.sub.x and PR.sub.y respectively. Initially, processor P.sub.x is BUSY performing an activity A.sub.b P.sub.x which has an activity record AR.sub.b P.sub.x. Also, another activity A.sub.a P.sub.x which has an activity record AR.sub.a P.sub.x is waiting in the PR.sub.x processor queue to be performed; and Processor P.sub.y is BUSY performing an activity A.sub.c P.sub.y. These initial conditions are indicated in FIG. 3 by the pointers having reference numeral 1.
Specifically, the CURRENT entry with reference numeral 1 in processor record PR.sub.x points to activity record AR.sub.b P.sub.x to indicate that processor P.sub.x is initially performing activity A.sub.b P.sub.x. Also, the PROCESSOR QUEUE HEAD entry and PROCESSOR QUEUE TAIL entry with reference numeral 1 in processor record PR.sub.x point to activity record AR.sub.a P.sub.x to indicate that activity A.sub.a P.sub.x is initially in the queue of processor record PR.sub.x.
Further, the CURRENT entry with reference numeral 1 of processor record PR.sub.y points to activity record AR.sub.d P.sub.y to indicate that initially processor P.sub.y is performing activity A.sub.d P.sub.y. And, the PROCESSOR QUEUE HEAD entry with reference numeral 1 of processor record PR.sub.y has a null value to indicate that no other activities are waiting to be performed on processor P.sub.y.
Subsequently, as indicated by the poilters in the records having reference numeral 2, activity A.sub.b P.sub.x CALLS activity A.sub.c P.sub.y. As a result, the CALLER entry in activity record AR.sub.c P.sub.y is written such that it points to activity record AR.sub.b P.sub.x ; and the PROCESSOR QUEUE HEAD and PROCESSOR QUEUE TAIL entries in processor record PR.sub.y are written such that they point to activity record AR.sub.c P.sub.y.
Also, since activity A.sub.b P.sub.x was a CALLER, processor P.sub.x suspends execution of that activity and begins execution of another activity which it gets from its queue. Consequently, the CURRENT entry in processor record PR.sub.x is written to point to activity record AR.sub.a P.sub.x ; and the PROCESSOR QUEUE HEAD entry of processor record PR.sub.x is written to a null value.
Subsequently, as indicated by the record entries having reference numeral 3, processor P.sub.y completes the execution of activity A.sub.d P.sub.y ; and thus it starts the execution of another activity in its queue. Thus, the CURRENT entry in processor record PR.sub.y is written to point to activity record AR.sub.c P.sub.y and the PROCESSOR QUEUE HEAD entry of processor record PR.sub.y is written to a null value.
Thereafter, as indicated by the record entries having reference numeral 4, processor P.sub.y completes the execution of activity A.sub.c P.sub.y. Thus, the activity that CALLED activity A.sub.c P.sub.y can resume execution; and so a pointer to activity record AR.sub.b P.sub.x is loaded into the PROCESSOR QUEUE HEAD and PROCESSOR QUEUE TAIL entries of processor record PR.sub.x. Also, processor P.sub.y is free to perform another activity; but since its processor queue is EMPTY, the CURRENT pointer of processor record PR.sub.y is written to a null value.
Processor P.sub.x continues with the execution of activity A.sub.a P.sub.x until that activity completes or calls another activity. That occurs at time t.sub.5. Then, processor P.sub.x resumes execution of activity A.sub.b P.sub.x since activity record AR.sub.b P.sub.x is pointed to by the processor queue of processor record PR.sub.x.
Referring now to FIGS. 4 and 5, another example of a sequence of the changes that occur to the processor records and activity records during several CALL and RETURN operations will be described. In this example, an activity A.sub.1 P.sub.x which processor P.sub.x performs is CALLED three times and another activity A.sub.2 P.sub.x which processor P.sub.x also performs is CALLED two times.
All of this calling occurs while processor P.sub.x is busy performing another activity; so the queues in processor records PR.sub.x and activity records AR.sub.1 P.sub.x and AR.sub.2 P.sub.x get loaded while the calling occurs. Subsequently, processor P.sub.x finishes the task that it was performing; and then it performs the activities which are pointed to in the queues of the processor and activity records. TABLE 5 below lists the sequence by which the various events occur.
FIG. 3 illustrates the sequence by which the processor and activity record queues get loaded; while FIG. 4 illustrates the sequence by which the queues get unloaded. In both of these figures, the pointers having reference numerals 1 through 11 respectively indicate the various entries in the processor and activity records at sequential time instants which correspond to those numbers.
Inspection of FIG. 4 shows that during time instants t.sub.1 -t.sub.6, the CURRENT entry of processor record PR.sub.x is pointing to an activity record which processor P.sub.x is currently performing. But at time instant t.sub.2, an activity A.sub.a P.sub.1 in processor P.sub.1 CALLS activity A.sub.1 P.sub.x in processor P.sub.x. As a result, the CALLER entry of activity record AR.sub.1 P.sub.x is written such that it points to activity record AR.sub.a P.sub.1 ; and the PROCESSOR QUEUE HEAD and PROCESSOR QUEUE TAIL entries of processor record PR.sub.x are written such that they point to activity record AR.sub.1 P.sub.x.
Thereafter, at time instant t.sub.3, an activity A.sub.b P.sub.2 in processor P.sub.2 CALLS activity A.sub.2 P.sub.x in processor P.sub.x. As a result of this CALL, the CALLER entry in activity record AR.sub.2 P.sub.x is written to point to activity record AR.sub.b P.sub.2. Also, the PROCESSOR QUEUE TAIL entry of processor record PR.sub.x is changed to point to activity record AR.sub.2 P.sub.x ; and the NEXT IN QUEUE entry of activity record AR.sub.1 P.sub.x is written to point to activity record AR.sub.2 P.sub.x.
Subsequently, at time instant t.sub.4, an activity A.sub.c P.sub.3 in processor P.sub.3 CALLS activity A.sub.1 P.sub.x. This CALL of activity A.sub.1 P.sub.x does not reload activity record AR.sub.1 P.sub.x into the queue of processor record PR.sub.x ; but instead, a pointer to activity record AR.sub.c P.sub.3 is written into the activity queue of activity record AR.sub.1 P.sub.x. This is achieved by writing the ACTIVITY QUEUE HEAD and ACTIVITY QUEUE TAIL entries of activity record AR.sub.1 P.sub.x such that they point to activity record AR.sub.c P.sub.3.
Next, at time instant t.sub.5, an activity A.sub.d P.sub.4 in a processor P.sub.4 CALLS activity A.sub.2 P.sub.x. Again, since the activity record AR.sub.2 P.sub.x is already in the processor queue of processor record PR.sub.x, a pointer to activity record AR.sub.d P.sub.4 is simply loaded into the activity queue of activity record AR.sub.2 P.sub.x. This is achieved by writing the ACTIVITY QUEUE HEAD and ACTIVITY QUEUE TAIL entries of activity record AR.sub.2 P.sub.x such that they point to activity record AR.sub.d P.sub.4.
Then, at time instant t.sub.6, an activity A.sub.e P.sub.5 in a processor P.sub.5 CALLS activity A.sub.1 P.sub.x. As a result, activity record AR.sub.e P.sub.5 is loaded into the activity queue of activity record AR.sub.1 P.sub.x. This is achieved by changing the ACTIVITY QUEUE TAIL entry of activity record AR.sub.1 P.sub.x such that it points to activity record AR.sub.e P.sub.5 ; and by writing the NEXT IN QUEUE entry of activity record AR.sub.c P.sub.3 such that it also points to activity record AR.sub.e P.sub.5.
Turning now to FIG. 5, the unloading of the queues in processor record PR.sub.x, activity record AR.sub.1 P.sub.x, and AR.sub.2 P.sub.x will be described. In FIG. 5, those pointers having reference numeral 6 are the same as the pointers having reference numeral 6 in FIG. 4.
At time instant t.sub.7, processor P.sub.x completes the activity which it was working on at time instants t.sub.1 through t.sub.6. Thus it performs an INTERPROCESSOR RETURN instruction. In response thereto, the controller IMC removes an activity record from the queue in processor record PR.sub.x and notifies processor record PR.sub.x of that removed activity. This removal operation is achieved via controller IMC by moving the PROCESSOR QUEUE HEAD entry in processor record PR.sub.x to the CURRENT entry in that processor record; and by moving the NEXT IN QUEUE entry of activity record AR.sub.1 P.sub.x to the PROCESSOR QUEUE HEAD entry of processor record PR.sub.x.
Thereafter, at time instant t.sub.8, processor P.sub.x completes activity A.sub.1 P.sub.x. Thus it performs another INTERPROCESSOR RETURN instruction. In response to that RETURN instruction, controller IMC removes one activity record from the activity queue of activity record AR.sub.1 P.sub.x. This it achieves by moving the ACTIVITY QUEUE HEAD entry in activity record AR.sub.1 P.sub.x to the CALLER entry of that record; and by moving the NEXT IN QUEUE entry of activity record AR.sub.c P.sub.3 into the ACTIVITY QUEUE HEAD entry of activity record AR.sub.1 P.sub.x. Then processor P.sub.x is notified that it should re-execute activity A.sub.1 P.sub.x for the second caller of that activity.
At time instant t.sub.9, processor P.sub.x again completes the execution of activity A.sub.1 P.sub.x. Thus, it again executes an INTERPROCESSOR RETURN instruction. In response thereto, the controller IMC removes another activity record from the activity queue of activity record AR.sub.1 P.sub.x. This it achieves by moving the ACTIVITY QUEUE HEAD entry of activity record AR.sub.1 P.sub.x into the CALLER entry of that activity and by setting the ACTIVITY QUEUE HEAD entry of activity record AR.sub.1 P.sub.x to a null value. Then, controller IMC informs processor P.sub.x to re-execute activity A.sub.1 P.sub.x for the third caller of that activity.
Thereafter, at time instant t.sub.10, processor P.sub.x completes the execution of activity A.sub.1 P.sub.x ; and so it again executes an INTERPROCESSOR RETURN instruction. In response thereto, controller IMC removes another activity record from the processor queue of processor record PR.sub.x ; and it informs processor P.sub.x of the new activity that it is to perform. This removal operation is achieved by moving the PROCESSOR QUEUE HEAD entry of processor record PR.sub.x into the CURRENT entry of that record and by changing the PROCESSOR QUEUE HEAD entry in processor record PR.sub.x to a null value.
Next, at time instant t.sub.11, processor P.sub.x completes the execution of activity A.sub.2 P.sub.x. Thus it again executes an INTERPROCESSOR RETURN instruction. In response thereto, controller IMC removes an entry from the activity queue of activity record AR.sub.2 P.sub.x and informs processor P.sub.x to re-execute activity A.sub.2 P.sub.x for the second caller of that activity. This removal operation is achieved by moving the ACTIVITY QUEUE HEAD entry of activity record AR.sub.2 P.sub.x to the CALLER entry of that activity and by setting the ACTIVITY QUEUE HEAD entry of activity record AR.sub.2 P.sub.x to a null value.
After processor P.sub.x completes the execution of activity A.sub.2 P.sub.x, it will again execute an INTERPROCESSOR RETURN instruction. At that point, there are no other activities for processor P.sub.x to perform; and so controller IMC merely resets the BUSY flag in processor record PR.sub.x and sets the CURRENT entry of that record to a null value.
From the above sequence of operations, it can be seen that the order in which processor P.sub.x performed activities A.sub.1 P.sub.x and A.sub.2 P.sub.x was entirely different than the order in which those activities were called. Specifically, the activities were called in the following order: A.sub.1 P.sub.x, A.sub.2 P.sub.x, A.sub.1 P.sub.x, A.sub.2 P.sub.x, and A.sub.1 P.sub.x ; but the order in which the activities were performed was: A.sub.1 P.sub.x, A.sub.1 P.sub.x, A.sub.1 P.sub.x, A.sub.2 P.sub.x, and A.sub.2 P.sub.x.
In other words, activity A.sub.1 P.sub.x was performed once for every one of its callers; and then activity A.sub.2 P.sub.x was performed once for every one of its callers. And this occurs regardless of the order in which those activities are called. Such re-ordering of the activities is important because it minimizes the number of times that a processor switches from performing one activity to another.
Each time a switch occurs, the code for the new activity must be read into the memory of the processor which is to perform the activity. Also, space must be re-allocated in the memory for data on which the activity performs. These resource-allocating operations are time-consuming; and thus they detract from the overall performance of the system.
Reference should now be made to FIG. 6 which illustrates the operation of the INTERPROCESSOR NEXT instruction. In this figure, as in the previous FIGS. 3-5, the pointers having reference numerals 1 through 9 indicate respective entries in the activity records and processor records at time instants which correspond to those reference numerals.
TABLE 6 below lists the sequence of events that occur in FIG. 6 in outline form. This outline shows a sequence in which an activity A.sub.a P.sub.1 calls another activity A.sub.b P.sub.2 ; then activity A.sub.b P.sub.2 executes a NEXT instruction to an activity A.sub.c P.sub.3 ; then activity A.sub.c P.sub.3 executes a NEXT instruction to an activity A.sub.d P.sub.4 ; then activity A.sub.d P.sub.4 returns directly to A.sub.a P.sub.1 without reentering activities A.sub.b P.sub.2 or A.sub.c P.sub.3.
Inspection of FIG. 6 shows that at time t.sub.1, processor P.sub.1 is executing an activity A.sub.a P.sub.1. That is because at time t.sub.1, the CURRENT entry in processor record PR.sub.1 is pointing to activity record AR.sub.a P.sub.1.
Next, at time t.sub.2, activity A.sub.a P.sub.1 SUSPENDS its execution by CALLING activity A.sub.b P.sub.2 in processor P.sub.2. As a result, the CALLER entry in activity record AR.sub.b P.sub.2 is written by controller IMC such that it points to activity record AR.sub.a P.sub.1. Also, since processor record PR.sub.2 indicates that processor P.sub.2 is currently busy performing another activity at time instant t.sub.2, the PROCESSOR QUEUE HEAD and PROCESSOR QUEUE TAIL entries of processor record PR.sub.2 are written by controller IMC to point to activity record AR.sub.b P.sub.2.
Subsequently, at time t.sub.3, processor P.sub.2 completes the execution of its current activity by performing an INTERPROCESSOR RETURN instruction. As a result, controller IMC moves the PROCESSOR QUEUE HEAD entry of processor record PR.sub.2 to the CURRENT entry of that record; and so the execution of activity A.sub.b P.sub.2 begins.
Subsequently, at time t.sub.4, another activity A.sub.x P.sub.y CALLS activity A.sub.b P.sub.2. Accordingly, since activity A.sub.b P.sub.2 is in an ACTIVE state, a pointer to activity record AR.sub.x P.sub.y is written by controller IMC into the activity queue of activity record AR.sub.b P.sub.2.
Next, at time t.sub.5, activity A.sub.b P.sub.2 performs an INTERPROCESSOR NEXT instruction to activity A.sub.c P.sub.3. As a result, controller IMC moves the CALLER entry of activity record AR.sub.b P.sub.2 to the CALLER entry of activity record AR.sub.c P.sub.3. Thus, the pointers in activity record AR.sub.c P.sub.3 are exactly as if activity A.sub.c P.sub.3 had been called directly by activity A.sub.a P.sub.1.
As a result of the above moving of the CALLER entry, activity A.sub.b P.sub.2 will not receive any parameters from activity A.sub.c P.sub.3. Instead, those parameters will be passed directly to activity A.sub.a P.sub.1. Thus, upon execution of the INTERPROCESSOR NEXT instruction, activity A.sub.b P.sub.2 is free to be re-executed by additional callers of that activity. Accordingly, at time t.sub.5, controller IMC moves the ACTIVITY QUEUE HEAD entry of activity record AR.sub.b P.sub.2 into the CALLER entry of that activity record; and it notifies processor P.sub.2 to re-execute activity A.sub.b P.sub.2 for its new caller.
At time t.sub.6, processor P.sub.3 completes the execution of the activity that it was previously executing; and so it performs an INTERPROCESSOR RETURN instruction. As a result, controller IMC moves the pointer to activity record AR.sub.c P.sub.3 from the PROCESSOR QUEUE HEAD entry to the CURRENT entry of processor record PR.sub.3. Processor P.sub.3 then begins execution of activity A.sub.c P.sub.3.
Upon completion of activity A.sub.c P.sub.3 at time t.sub.7, processor P.sub.3 has the option to perform either an INTERPROCESSOR RETURN instruction or another INTERPROCESSOR NEXT instruction. In FIG. 6, an INTERPROCESSOR NEXT instruction is performed to activity A.sub.d P.sub.4. As a result, controller IMC moves the CALLER entry of activity record AR.sub.c P.sub.3 to the CALLER entry of activity record AR.sub.d P.sub.4. Also, since processor P.sub.4 is not busy, the CURRENT entry of processor record PR.sub.4 is loaded by controller IMC with a pointer to activity record AR.sub.d P.sub.4 ; and processor P.sub.4 is notified to begin execution of activity A.sub.d P.sub.4.
At time t.sub.8, processor P.sub.4 completes execution of activity A.sub.d P.sub.4. Thus, processor P.sub.4 has the option of performing either an INTERPROCESSOR RETURN instruction or an INTERPROCESSOR NEXT instruction. In FIG. 6, processor P.sub.4 performs an INTERPROCESSOR RETURN instruction.
Due to the INTERPROCESSOR RETURN, controller IMC loads the CALLER entry of activity record AR.sub.d P.sub.4 into the processor queue of processor record PR.sub.1. Thereafter, at time t.sub.9, processor P.sub.1 completes the execution of the activity that it was previously performing; and it resumes the execution of activity A.sub.a P.sub.1 which it had previously suspended back at time t.sub.2.
This resumption of the execution of activity A.sub.a P.sub.1 is possible since the parameters which that activity was waiting for from the CALLED activity A.sub.a P.sub.2 were made available at time t.sub.8. But from the above, it is evident that those parameters did not merely come from the CALLED activity A.sub.b P.sub.2. Instead, they were the result of the sequential execution of three activities A.sub.b P.sub.2, A.sub.c P.sub.3, and A.sub.d P.sub.4.
But all of this sequential execution was completely hidden from activity A.sub.a P.sub.1 due to the operation of the INTERPROCESSOR NEXT instruction. Consequently, the linking of activity A.sub.a P.sub.1 to the other activities A.sub.c P.sub.3 and A.sub.d P.sub.4 was greatly simplified. Further, since activities A.sub.b P.sub.2 and A.sub.c P.sub.3 did not have to be re-executed as parameters where passed from activity A.sub.d P.sub.4 to activity A.sub.a P.sub.1, that parameter passing occurred very quickly.
Reference should now be made to FIG. 7 which illustrates another system in which the plurality of processors P.sub.1, P.sub.2, . . . P.sub.n access and change multiple processor records, activity records, and parameters in a shared memory SM. This system differs primarily from the above-described FIG. 1 system in that it includes a file access controller 20 which authorizes the processors to access and change the records directly by conventional memory read and memory write commands.
That is, the records in the FIG. 7 system are stored in a conventional memory; they are accessed through a conventional nonintelligent memory controller MC; and the processors of the FIG. 7 system execute the INTERPROCESSOR instructions by sending sequences of one-word memory read and memory write commands directly to a nonintelligent memory controller MC. But before any processor sends such commands to the nonintelligent memory controller to read or write the records in the shared memory SM, it must receive authorization to do so from the file access controller 20.
FIG. 8 illustrates the details of one preferred embodiment of the file access controller 20. It includes a plurality of "n" flip-flops 21-1 through 21-n. In one embodiment, each flip-flop corresponds to one record in the shared memory SM. That is, each flip-flop corresponds to one processor record or one activity record. Alternatively, as a design choice, each flip-flop corresponds to one processor record and all of the corresponding activity records for that one processor record.
Initially, all of the flip-flops are reset. Then, before a processor is permitted to access any record it must first interrogate the flip-flops to determine whether those which correspond to the records that it wants to access are presently reset. To that end, the requesting processor sends a message over the bus to a module 22 within the controller. Suitably, module 22 is a microprocessor.
That message which is sent to module 22 identifies the requesting processor; and it also identifies all of the records of which access is sought. For example, four processor records PR.sub.a, PR.sub.b, PR.sub.c, and PR.sub.d and all of the corresponding activity records may be identified by four encoded fields F.sub.a, F.sub.b, F.sub.c, and F.sub.d in the message.
Upon receiving the message, module 22 passes it over an internal bus 23 to a register 24. From there, fields F.sub.a, F.sub.b, F.sub.c, and F.sub.d are sent to the control input terminals of multiplexers 25a, 25b, 25c, and 25d respectively. Each multiplexer also has its data input terminals coupled to the Q outputs of all of the flip-flops 21-1 through 21-n.
Thus, field F.sub.a of register 24 causes the Q output of the one flip-flops which corresponds to field F.sub.a to be gated to the output of multiplexer 25a. Similarly, field F.sub.b of register 24 causes the Q output of the one flip-flop which corresponds to that field to be gated to the output of multiplexer 25b; etc. All of those Q outputs are then ANDed together by an AND gate 26; and the result is sent back to module 22 where it is sensed.
If the signal from AND gate 26 is a logic ONE, then module 22 sends a message over the bus authorizing the requesting processor to change the contents of the identified records. Internal bus 23 provides a means for sensing the requesting processor's identification so this message can be sent to it.
Also, if the signal from AND gate 26 is a ONE, module 22 sends a single clock pulse to all of the flip-flops 21-1 through 21-n. Those flip-flops are JK flip-flops; and which of them have an active signal on their J input is controlled by the F.sub.a, F.sub.b, F.sub.c, and F.sub.d fields in register 24. Thus, those flip-flops that correspond to the fields F.sub.a, F.sub.b, F.sub.c, and F.sub.d are all set in response to the single clock pulse.
More specifically, the F.sub.a, F.sub.b, F.sub.c, and F.sub.d fields in register 24 are sent to decoders 27a, 27b, 27c, and 27d respectively. Each of those decoders generates multiple output signals; but only one of those signals goes high at a time. That output signal which goes high corresponds to the code which the decoder receives from register 24.
In other words, the first output of decoder 27a goes high when field F.sub.a in register 14 equals a binary one; the second output of decoder 27a goes high when field F.sub.a in register 24 is a binary two; etc.
Also, the first output of decoders 27a, 27b, 27c, and 27d are all connected together in a WIRED-OR fashion. Thus, if any of the fields F.sub.a, F.sub.b, F.sub.c, or F.sub.d in register 24 equal a binary one, it will cause flip-flop 21-1 to be set. Similarly, the second output of decoders 27a, 27b, 27c, and 27d are connected together in a WIRED-OR fas-hion; etc.
Suppose now that module 22 receives a request from a processor to access various records as specified by fields F.sub.1 through F.sub.4 ; but the output of gate 26 is a ZERO which indicates that at least one of the corresponding flip-flops is set. In that case, module 22 loads the contents of register 24 into a first-in-first-out (FIFO) queue 28; and it adds one to a counter which is internal to module 22.
Next, suppose that one of the processors which previously was granted authorization to interrogate some records has completed its task. In that case, the processor must send module 22 a message indicating which records it has finished interrogating. Preferably, those records are identified in the message by multiple encoded fields.
That message is then sent by module 22 to a register 29. From there, the fields which contain the numbers of the records that were interrogated are sent to respective decoders. For example, four decoders 30a, 30b, 30c, and 30d are provided if the message in register 29 contains four encoded fields F.sub.a ', F.sub.b ', F.sub.c ', and F.sub.d '.
Decoders 30a through 30d all have their first outputs connected together in a WIRED-OR fashion; and they also connect to the K input of flip-flop 21-1. Thus, if any of the four fields in register 29 contains a binary one, flip-flop 21-1 will be reset when all of the flip-flops are clocked.
Similarly, the second output of decoders 30a-30d are all connected together; and they are connected to the K input of flip-flop 20-2; etc. Thus, to reset the flip-flops which correspond to the records that were interrogated, module 22 merely clocks all of the flip-flops with a single pulse after it loads register 29.
Then module 22 examines its internal counter to determine how many entries are in the FIFO 28. If the count is not zero, module 22 moves the queue entries one at a time into register 24. After each such move, it examines the output of AND gate 26 to determine if it is in a ONE state.
If AND gate 26 is in a ONE state, then module 22 reads the requester portion of register 24 onto bus 23 and sends that requester a message indicating that it may now modify the records it requested. Also, all of the flip-flops 21-1 through 21-n are clocked by module 22 with a single pulse which sets them as directed by the outputs of decoders 27a through 27d. Further, the counter that is internal to module 22 is decremented by one.
Conversely, if the output of AND gate 26 is in a ZERO state, then module 22 merely reloads the contents of register 24 back into FIFO 28.
In FIG. 8, a set of six dashed lines represent respective conductors on which respective control signals are sent by module 22 to cause the above-described operations to occur. Specifically, a clock pulse is sent on conductor A to load a word into FIFO 28; and a clock pulse is sent on conductor B to unload a word from FIFO 28.
Also, a control signal is sent on conductor E to select the input data to register 24 to be from FIFO 28 or bus 23; and a clock pulse is sent on conductor F to load the selected input data into register 24. Further, a clock pulse is sent on conductor L to clock the flip-flops 21-1 through 21-n; and a clock pulse is sent on conductor M to load register 29.
One feature of the above-described file access controller 20 is that it enables several of the processors P.sub.1, P.sub.2, . . . P.sub.n to access and change various records in the shared memory at the same time. The only restriction on this is that no two processors can change the same record. Thus, for example, processor P.sub.1 could be changing records 1, 15, 30 and 56, while processor P.sub.2 is changing records 2, 12, 31 and 40, while processor P.sub.3 is changing records 3, 11, 20 and 31.
Another feature of the FIG. 7 system is its flexibility. Once a processor obtains authorization from the file access controller 20 to interrogate and change particular records, it can do so by any sequence of memory read and memory write commands. Therefore, records may be first read; and then the processor may CALL one activity or another based on contents of the records that it read. This implements a CONDITIONAL INTERPROCESSOR CALL instruction.
As one example of the usefulness of a CONDITIONAL INTERPROCESSOR CALL instruction, suppose that two processors perform the same activities. Both processors, for example, may perform high-speed floating point mathematical activities. In that case, by performing a CONDITIONAL INTERPROCESSOR CALL instruction, the caller can first examine the activity records of the two processors that perform the floating point activities; and then it can CALL an activity in one processor or the other depending upon which processor was not presently busy.
Another feature of the FIG. 7 system is the speed at which a processor can acquire access to the records in the shared memory SM. To send a control word to the file access controller 20 over the bus takes one cycle; to pass that message to register 24 takes a second cycle; to wait for the test condition from AND gate 26 to stabilize takes a third cycle; and to send a message back to the requesting processor authorizing it to access the requested records based on AND gate 26 plus send a clock pulse to set the corresponding flip-flops 21-1 through 21-n takes a fourth cycle. Thus, with a cycle time of 100 nanoseconds, for example, access to the records is acquired in only 400 nanoseconds.
Various embodiments of the invention have now been described in detail. In addition, however, many changes and modifications can be made to these details without departing from the nature and spirit of the invention. Accordingly, it is to be understood that the invention is not limited to said details but is defined by the appended claims.
Claims
What is claimed:
1. A method of performing a task as a sequence of called activities in multiple digital processors which operate asynchronously to each other; said method including the steps of: executing a portion of a first activity of said sequence in a first processor, said portion including and ending with an INTERPROCESSOR CALL instruction; suspending execution of the first activity in response to said INTERPROCESSOR CALL and signaling a second processor that a second activity has been called by the first activity; completely executing the second activity in the second processor in response to said INTERPROCESSOR CALL and further executing an INTERPROCESSOR NEXT instruction which references a third activity in a third processor; signaling the third processor in response to said INTERPROCESSOR NEXT instruction that said third activity has been called not by said second activity but by whatever activity happened to call the second activity; and completely executing said third activity in said third processor and, upon completion thereof, signaling said third activity's apparent caller as indicated by said INTERPROCESSOR NEXT instruction, to resume execution.
2. A method according to claim 1 and further including the step of signaling said second processor in response to said INTERPROCESSOR NEXT instruction to re-execute said second activity if it is called again by yet another activity even while said third activity is being executed by said third processor.
3. A method according to claim 1 and further including the steps of: providing each activity with a queue containing pointers to the respective caller of that activity; and moving the caller pointer from the queue of the second activity into the queue of the third activity in response to said INTERPROCESSOR NEXT instruction.
4. A method according to claim 3 and further including the step of limiting access to said queues such that said pointers are loaded and unloaded during multiple cycles by only one of said processors at a time.
5. A method according to claim 1 and further including the step of executing another activity in said first processor while said first activity is suspended.
6. A data processing system including first, second and third digital processors which operate asynchronously to each other; said system being adapted to perform a task as a sequence of called activities of which some are not returned to when the sequence is complete, including: means for directing said first processor to execute a portion of a first activity in said sequence, said portion including and ending with an INTERPROCESSOR CALL instruction; means for signaling a second processor in response to said INTERPROCESSOR CALL instruction that a second activity has been called by said first activity and also suspending execution of said first activity; means for directing said second processor to completely execute said second activity and further execute an INTERPROCESSOR NEXT instruction which references a third activity in a third processor; means for signaling said third processor in response to said INTERPROCESSOR NEXT instruction that said third activity has been called not by said second activity but by whatever activity happened to call said second activity; and means for directing said third processor to completely execute said third activity, and upon completion thereof, to signal said third activity's apparent caller as indicated by said INTERPROCESSOR NEXT instruction to resume execution.
7. A system according to claim 6 and further including means for signaling said second processor to re-execute said second activity if it is called again by yet another activity even while said third activity is being executed by said third processor in response to said INTERPROCESSOR NEXT instruction.
8. A system according to claim 6 and further including: a queue means for each activity containing pointers to the respective caller of that activity; and means for moving the caller pointer from the queue of said second activity into the queue of said third activity in response to said INTERPROCESSOR NEXT instruction.
9. A system according to claim 8 and further including a means for limiting access to said queues such that said pointers are loaded and unloaded during multiple cycles by only one of said processors at a time.
10. A system according to claim 6 and further including means for executing another activity in the first processor while said first activity is suspended.