Startup Circuit for a Switched Power Supply

The invention relates to a startup circuit for a switched power supply having an undervoltage monitor and pulse width modulator as a control portion that has at least one immediate start input and one inable input.

Switched power supplies usually have a monitoring unit that disconnects the power supply via a control and regulating unit given downward movement of a specific value of the output voltage. In order to enable the startup operation of the power supply, an undervoltage monitoring unit must be disabled simultaneously with the startup instruction.

This usually occures in such manner that a one-shot multivibrator is started with the startup instruction. The one-shot multivibrator disables the undervoltage monitoring unit and thus enables the control and regulating unit of the power supply. After the lapse of a time defined by the wiring of the one-shot multivibrator, the undervoltage monitoring unit is reconnected. In addition to the high susceptibility of one-shot multivibrators to disruption, the disadvantage of this principle is that the time constants ofthe one-shot multivibrator and soft start circuit must be very precisely matched to one another in order to guarantee a reliable startup of the power supply.

An object of the present invention is to create a startup circuit for a switched power supply having an undervoltage monitoring unit and a pulse width modulator as the regulating portion thereof and which disables the undervoltage monitoring unit during the startup operation of the switched power supply by simple techniques.

In order to achieve this object, the startup circuit for a switched power supply is designed such that the outputs of two comparators are connected by a NAND gate to the enable input of the pulse width modulator. Each of the comparators exhibit two respective inputs. A chargeable capacitor is applied to the first input of the first comparator via a resistor, a controllable electronic switch is connected parallel to the chargeable capacitor, and a first reference voltage is connected to the second input of the first comparator. A second reference voltage equal to or lower than the first reference voltage is connected to the first input of the second comparator and the output voltage of the switched power supply is connected to its second input. The voltage generated at the capacitor is connected to the soft start input of the pulse width modulator via a biased rectifier whose bias voltage is equal to or lower than the first reference voltage. A control circuit having an input for startup instructions and having an input for switch-off instructions is connected at its output side to the control input of the electronic switch, and the enable input of the pulse width modulator is connected to the input for the connect instruction.

The difficult matching of time constants of different circuits to one another is avoided by means of these techniques.

The controllable electronic switch can thus advantageously be a transistor having a resistor lying in its collector circuit. The bias voltage of the rectifier can be set via a voltage divider in a simple manner.

The drawing FIGURE shows a schematic diagram of a start-up system for a switched power supply according to the invention.

The FIGURE shows the regulating portion and the startup circuit for a switched power supply. The regulating portion thus consists of the pulse width modulator PBM that has two inputs E1 and E2. The input E2 is the so-called soft start input that guarantees a soft "startup" of the overall switched power supply since a constant voltage slowly increasing at this input slowly changes the pulse duration ratio and thus the output voltage U.sub.a of the overall power supply.

The input E1 is the so-called enable input at which an enable or inhibit of the overall power supply is achieved by means of applying specific signals.

The enable input is connected to the output of the NAND gate G whose two inputs are connected to the outputs of two comparators K1, K2.

A voltae U.sub.S that can be generated at the capacitor C.sub.S is supplied to the first comparator at its x-input whereas the voltage U.sub.ref1 is present at its y-input. The comparator K2 likewise has a reference voltage U.sub.ref2 at its x-input whereas the output voltage U.sub.a of the switched power supply is supplied to its y-input. The transistor V having a resistor R.sub.C in its collector circuit lies parallel to the capacitor C.sub.S. The transistor V is driven at its base by a control circuit ST to whose input E the startup instructions are supplied. A connection is simultaneously provided from the enable output E1 to the input responsive for supplying switchoff instructions.

The functioning of the circuit shall now be explained in detail.

Dependent on the level of the constant voltage at the soft start input E2 of the pulse width modulato PBM, the pulse-duty factor of the switched power supply is varied and, thus, the output voltage of the switched power supply is varied. The maximum pulse-duty ratio is defined via the resistance divider R.sub.T1, R.sub.T2. A voltage generated at the capacitor C.sub.S is connected to the soft start input E2 of the pulse width modulator by a biased rectifier G1 having a bias voltage applied thereto equal to or smaller than the reference voltage U.sub.ref1. Diode G1 is biased via a diode G2 connected to the voltage divider R.sub.T1, R.sub.T2 fed from a DC supply U.sub.B. The first reference voltage must therefore be selected at U.sub.ref1 32U.sub.T in order to guarantee a sure startup of the switched power supply. The pulse duration modulator is enabled over the soft start input E2. When the transistor V is inhibited with a startup instruction by the control circit ST, then the voltage at the input E2 begins to rise in accordance with the time constant R.sub.S .multidot.C.sub.S, as does the voltage of the switched power supply. When the voltage at the capacitor C.sub.S exceeds the value U.sub.ref1, then the output of the comparator K1 assumes the Hi level and thus connects the comparator K2 for the undervoltage monitoring unit to the enable input of the control and regulating unit through the NAND gate G. If no fault condition of the power supply existed during the runup operation of the output voltage U.sub.a, then the output of the comparator K2 has assumed the low level in the meantime since the output voltage U.sub.a has exceeded the value U.sub.ref2. The pulse duration modulator remains switched on. Should the output voltage U.sub.a not have reached the value U.sub.ref2 --due, for example, to a short--then the H level is retained at the output of the second comparator K2, and the pulse duration modulator is then inhibited over the enable input E1 and the control circuit ST is reset.

Depending on the design of the gate G, the circuit can be adapted to various types of pulse duration modulators. The first reference voltage U.sub.ref1 must thus always be greater than or equal to the second reference voltage U.sub.ref2.

In the preferred embodiment of the invention, the control circuit ST is an RS flip-flop having the inputs E and A shown in the drawing figure.

Although various minor modifications and variations might be proposed by those skilled in the art, it will be understood that I wish to include within the claims of the patent warranted hereon all such changes and modifications as reasonably come within my contribution to the art.