Transition Detector Circuit

The present invention relates to a MOS (MetalOxide-Silicon) integrated circuit provided on a semiconductor substrate, and more particularly to a transition detector circuit for sensing a change of an input signal of the MOS circuit, thereby producing pulse signals responsive thereto.

Heretofore, there have been proposed some conventional transition detector circuits. One is a circuit including a feedback network for effecting input control. The other is a circuit which does not include such a feedback network.

The problems with the transition detector circuit including a feedback network are that the circuit design thereof is complicated and there occurs undesirable time delays in the operation thereof.

On the other hand, the transition detector circuit without a feedback network is preferable in that the circuit design is simple and operates at a high speed. However, it happens that this circuit operates erroneously due to the difference of operation timing of each circuit component, when input signals vary slowly.

With the above in mind, an object of the present invention is to provide a transition detector circuit making it possible to operate at a high speed with a simplified circuit construction and to effect a normal operation, even if there exists a limited timing relationship or timing limitation between an input signal and an output signal.

In order to achieve this object, according to the present invention, there is provided a transition detector circuit capable of producing output pulse signals each having a desired pulse width by means of a circuit which is simplified and operates at a high speed, in which a feedback network is eliminated and a plurality of invertor trains are provided, and capable of effecting a normal operation even if there exists a timing limitation between an input signal and an output signal on the basis of the circuit construction that an invertor or some invertors among invertors for limiting a pulse width of the output pulse is in common with respective invertor trains for producing in-phase and antiphase outputs and that a predetermined relationship holds between threshold levels of these invertors.

FIGS. 1 and 2 are circuit diagrams illustrating prior art transition detectors, respectively;

FIG. 3 is a timing chart for explaining a timing limitation between an input signal and an output signal of FIG. 2 circuit;

FIG. 4 is a circuit diagram illustrating an embodiment of the present invention;

FIGS. 5 and 6 are timing charts showing operations of the FIG. 4 circuit, respectively; and

FIG. 7 is a circuit diagram illustrating another embodiment of the invention.

Prior to the description of the invention, reference will be first made to the conventional transition detectors in conjunction with FIGS. 1 to 3. Thereafter, the preferred embodiments of a transition detector circuit according to the present invention will be referred to in conjunction with FIGS. 4 to 7.

The prior art transition detector in a MOS integrated circuit is now described with reference to FIGS. 1 to 3.

FIG. 1 shows an example of circuit of a conventional device, as shown in U.S. Pat. No. 4,039,858. An output signal 1 of the transition detector is utilized in order to effect input control for an input signal 2. The transition detector is designed so as to produce pulse signals at an output terminal 3 with the feedback looped network thus formed. However, since the circuit construction shown in FIG. 1 requires the feedback network, its circuit design becomes complicated. Further, with this circuit, output signals 4 and 5 except for pulse signals are output through a transfer gate controlled by the pulse signal 1, thereby resulting in large time delays.

FIG. 2 is a circuit diagram illustrating another conventional device. A feature of this embodiment is that the feedback network as employed in FIG. 1 circuit is not used, and time interval adjustment is effected depending on the stage number of an invertor train. Between a signal input terminal 6 and an in-phase output terminal 7, there is provided an invertor train comprising an even number of invertor I.sub.1 and I.sub.2. On the other hand, between the input terminal 6 and an antiphase (180.degree. out-of-phase) output terminal 8, there is provided an invertor train comprising an odd or uneven number of invertors I.sub.3, I.sub.4 and I.sub.5. A first pair of Field Effect Transistors (which will be called "transistors" hereinafter) T.sub.01 and T.sub.02 connected in series, and a second pair of transistors T.sub.03 and T.sub.04 connected in series are connected to one reference power supply V.sub.SS, respectively. These pairs of transistors are further connected commonly to a pulse output terminal 9 through an invertor I.sub.6. Another reference power supply V.sub.DD is connected to the input of the invertor I.sub. 6 through a load 10. Further, an invertor train comprising I.sub.7, I.sub.8, I.sub.9 and I.sub.10 is connected to the signal input terminal 6. The outputs of invertors I.sub.7, I.sub.9 and I.sub.10 are fed to the gate terminals of transistors T.sub.03, T.sub.02 and T.sub.04, respectively. Further, a signal being propagated from the signal input terminal 6 is supplied to the gate terminal of the transistor T.sub.01.

With the circuit construction shown in FIG. 2, a time interval of the pulse output C is determined due to signal delays occurring when the signal input A is propagated through three stages of invertors comprising either of invertors I.sub.7, I.sub.8 and I.sub.9 and invertors I.sub.8, I.sub.9 and I.sub.10 with respect to a change of the signal input A. As a result, this makes it possible to effect an adjustment of the time interval depending on the stage number of the invertor train, thereby making it easy to design the circuit. Further, signal propagating routes for the in-phase output B and the antiphase output B are different from that of the pulse output C. Consequently, this ensures that the circuit operates at a high speed.

However, as described above, in regard to the circuit construction shown in FIG. 2, the signal paths for the in-phase output B and the antiphase output B are different from that of the pulse output C. Accordingly, the circuit of FIG. 2 cannot properly operate when the following relationship is required in connection with the timing relationship between the in-phase and antiphase outputs B and B and the pulse output C. The reason therefore will be described with reference to FIG. 3.

As shown in FIG. 3, suppose the relationship in connection with time is as follows: It is to be noted that "H" or "L" showing a logical level is referred to in terms of usual logical expression. The designation t.sub.1 denotes a time interval from a time when the signal input A changes from "L" to "H" to a time when the pulse output C rises, t.sub.2 a time interval from the same time to a time when the antiphase output B changes to "L", t.sub.3 a time interval from the same time to a time when the in-phase output B changes to "H", and t.sub.4 a time interval from the same time to a time when the pulse output C falls. Likewise, t.sub.5 denotes a time interval from a time when the signal input A changes from "H" to "L" to a time when the pulse output C rises, t.sub.6 a time interval from the same time to a time when the in-phase output B changes to "L", t.sub.7 a time interval from the same time to a time when the antiphase output B changes to "H", and t.sub.8 a time interval from the same time to a time when the pulse output C falls. Further, suppose that the threshold voltages of invertors I.sub.1, I.sub.3 and I.sub.7 and the transistor T.sub.01 are V.sub.1, V.sub.3, V.sub.7 and V.sub. 01, respectively. In this instance, when an inequality t.sub.1 <t.sub.2 <t.sub.3 <t.sub.4 and an inequality t.sub.5 <t.sub.6 <t.sub.7 <t.sub.8 must hold, an inequality V.sub.01 <V.sub.1 <V.sub.7 is required from the former (t.sub.1 <t.sub.2 <t.sub.3 <t.sub.4), and an inequality V.sub.3 <V.sub.7 and an inequality (the time delay of invertors I.sub.3 to I.sub.5)<(the time delay of invertors I.sub.7 to I.sub.10) are required from the latter (t.sub.5 <t.sub.6 <t.sub.7 <t.sub.8).

Assume now that the signal input A varies slowly from "H" to "L". Since the output of the invertor I.sub.7 changes and then the output of the invertor I3 changes, the relationship t.sub.5 <t.sub.6 is satisfied. However, in this instance, care must be taken. When the signal input A slowly changes and reaches the threshold level of the invertor I.sub.7. After the change of the output of the invertor I.sub.7 is propagated to the invertor I.sub.10, the signal input A reaches the threshold level of the invertor I.sub.3. Taking into account these conditions, the information in connection with the output change of the invertor I.sub.7 is propagated to the invertor I.sub.10. As a result, after the pulse output C has fallen, the output of the invertor I.sub.3 changes. Consequently, the relationship t.sub.7 <t.sub.8 cannot be satisfied.

The preferred embodiments according to the invention is now described with reference to FIGS. 4 to 7. FIG. 4 shows a circuit diagram illustrating an embodiment of the invention wherein like components in FIG. 2 are designated by like reference numerals. The in-phase output being propagated from the invertor I.sub.2 is fed to the gate of an n-channel transistor T.sub.12 through the invertor I.sub.11. The antiphase output being propagated from the invertor I.sub.5 is fed to the gate of an n-channel transistor T.sub.14 through the invertor I.sub.12. The signal input A is fed to the gate of an n-channel transistor T.sub.11, and is also fed to an n-channel transistor T.sub.13 through the invertor I.sub.7, respectively. The capacity of each invertor serving as a driver and the load 10 is determined so that the relationship V.sub.7 >V.sub.1 >V.sub.3 V.sub.11 holds between the threshold voltages V.sub.1, V.sub.3 and V.sub.7 of invertors I.sub.1, I.sub.3 and I.sub.7 and the threshold voltage V.sub.11 of the transistor T.sub.11. In order to obtain the relationship in regard to such threshold voltages, the dimension of the p-channel and n-channel of the transistors constituting invertors and that of transistors constituting a switching circuit are determined.

The operation when the signal input A changes to "L" for a second time after the signal input A changes from "L" to "H" in FIG. 4 circuit will be described with reference to FIG. 5.

When the signal input A is "L", outputs of invertors I.sub.7 and I.sub.11 or "H", and the output of inverter I.sub.12 is "L". Accordingly, transistors T.sub.11, T.sub.12, T.sub.13 and T.sub.14 are placed in OFF, ON, ON and OFF states, respectively. As a result, the pulse output C is "L".

On the contrary, when the signal input A is changed to "H", the transistor T.sub.11 turns on. As a result, the pulse output C changes from "L" to "H". Further, after the delay time T.sub.1 determined by the invertors I.sub.1, I.sub.2 and I.sub.11 is passed, the output of the invertor I.sub.11 changes from "H" to "L". As a result, since the transistor T.sub.12 turns off, the pulse output C is returned to "L" from "H". Thus, a pulse having a time interval (T.sub.1) determined by invertors I.sub.1, I.sub.2 and I.sub.11 is output from the terminal 9.

Further, when the signal input A changes from "H" to "L", the invertor I.sub.7 changes from "L" to "H" in a predetermined time delay inherent in the invertor I.sub.7, with the result that the transistor T.sub.13 turns on. As a result, the output C changes from "L" to "H". Further, after the delay time determined by invertors I.sub.3, I.sub.4, I.sub.5 and I.sub.12 is passed, the output of the invertor I.sub.12 changes from "H" to "L", with the result that the transistor T.sub.14 turns off. As a result, the pulse output C changes from "H" to "L". Thus, a pulse having a time interval (T.sub.2) determined by invertors I.sub.7, I.sub.3, I.sub.4, I.sub.5 and I.sub.12 is output from the terminal 9.

As stated above, a pulse width of the pulse output C is determined by the delay time of each invertor. Accordingly, it is possible to set the desired value of the pulse widths T.sub.1 and T.sub.2 by increasing or decreasing the stage number of the invertor, or changing the delay time thereof.

The operation will be described with reference to FIG. 6 when the signal input A varies slowly from "L" to "H", and then varies slowly from "H" to "L" for a second time. In this instance, the above-described relationship V.sub.7 >V.sub.1 >V.sub.3 >V.sub.11 holds in connection with the respective threshold voltages V.sub.7, V.sub.1, V.sub.3 and V.sub.11 of invertors I.sub.7, I.sub.1 and I.sub.3, and the transistor T.sub.11.

When the signal input A approaches gradually from "L" to "H", and then reaches the level of V.sub.11, the transistor T.sub.11 turns on and the pulse output C changes from "L" to "H".

When the signal input A further approaches "H" and then reaches the level of V.sub.3, the output of the invertor I.sub.3 becomes "L". Accordingly, the antiphase output B becomes "L" in a predetermined time delay determined by PG,11 invertors I.sub.4 and I.sub.5. Further, since the output of the invertor I.sub.12 becomes "H", the transistor T.sub.14 turns on.

When the signal input A further approaches "H" and then reaches the level of V.sub.1 the output of the invertor I.sub.1 becomes "L". Accordingly, the in-phase output B becomes "H" in a predetermined time delay of the invertor I.sub.2. Further, since the output of the invertor I.sub.11 becomes "L", the transistor T.sub.12 turns off. However, since transistors T.sub.13 and T.sub.14 have already turned on, the pulse output C is maintained "H".

When the signal input A further approaches "H" and then reaches the level of V.sub.7, the output of the invertor I.sub.7 becomes "L", with the result that the transistor T.sub.13 turns off. As a result, the pulse output C becomes "L". Thus, a pulse having a time interval T.sub.1 is obtained.

Then, after a predetermined time is passed, when the signal input A approaches from "H" gradually to "L" and then reaches the level of V.sub.7, the output of the invertor I.sub.7 is inverted into "H". Accordingly, the transistor T.sub.13 turns on, with the result that the pulse output C becomes "H".

When the signal input A further approaches "L" and then reaches the level of V.sub.1, the output of the invertor I.sub.1 becomes "H" while the output of the in-phase output B becomes "L". Since the invertor I.sub.11 becomes "H", the transistor T.sub.12 turns on.

When the signal input A further approaches "L" to reach the level of V.sub.3, the output of the invertor I.sub.3 becomes "H". As a result, the antiphase output B becomes "H". Since the output of the invertor I.sub.12 becomes "L", the transistor T.sub.14 turns off. However, since transistors T.sub.11 and T.sub.12 are maintained on, the pulse output C is also maintained "H".

Finally, when the signal input A further approaches "L" to reach the level of V.sub.11, the transistor T.sub.11 turns off. As a result, the pulse output C becomes "L". Thus, a pulse having a time interval T.sub.2 is obtained.

Referring to FIG. 7, there is shown another embodiment of the invention, wherein like components in FIG. 4 are designated by like reference numerals. A p-channel transistor T.sub.21 and a p-channel transistor T.sub.23 are connected in parallel. A p-channel transistor T.sub.22 and a p-channel transistor T.sub.24 are also connected in parallel. These parallelly-connected pairs are connected in series. The signal input A is fed to the gate of the transistor T.sub.21. The outputs of invertors I.sub.7 I.sub.11 and I.sub.12 are fed to gates of transistors T.sub.22, T.sub.23 and T.sub.24, respectively.

The threshold levels V.sub.1 V.sub.3 and V.sub.7 of invertors I.sub.1, I.sub.3 and I.sub.7 and the threshold level V.sub.21 of the transistor T.sub.21 are determined such that the relationship V.sub.21 <V.sub.3 <V.sub.1 <V.sub.7 holds. This is accomplished by changing the channel dimension of the transistor, as stated above. Thus, the circuit shown in FIG. 7 normally operates when there exists a timing limitation as shown in FIG. 3 in connection with input and output signals.

As is apparent from the foregoing description, according to the present invention, the feedback network as employed in the prior art device is not used, and a pulse width is determined based on invertor trains. Accordingly, this makes it possible to embody a transition detector which is easy to design and which operates at a high speed. Further, the transition detector of the invention determines a pulse width of the pulse being output on the basis of the delay time of an invertor. Accordingly, this makes it possible to adjust a pulse width and to stabilize the pulse width as desired.

Further, according to the present invention, invertors for limiting a pulse width form a part of invertors for obtaining the in-phase and antiphase outputs. A predetermined relationship is given between the threshold levels of invertors and switching elements (for example, transistor) constituting the switching circuit. Thus, it is possible to obtain the transition detector circuit which operates desirably, even if there exists a timing limit as shown in FIG. 3 between input and output signals.