Digital Frequency Synthesizer Circuit

The invention relates to digital frequency synthesis, and more particularly, to a high-resolution, programmable digital frequency divider.

In electronic position-fixing systems such as those having transmitters carried in earth-orbitting satellites, it is necessary for a receiver to determine the magnitude of the Doppler shift component of the signal received from the satellite, including contribution to the Doppler shift from the user's motion. In one such position-fixing system, the carrier signals are modulated with pseudo-random noise codes. The codes facilitate satellite identification (each satellite having a unique code), and measurement of the signal propagation time from satellite to user. The receiver synchronizes with the code of a particular satellite by generating within the receiver the code for the satellite, and then correlating the locally generated code with the received signal. After synchronization, both the phase of the carrier signal and the code sequence timing are continuously tracked. One such pseudo-random noise code utilized in the Navstar-Global Positioning System (GPS) is termed a P (Precision) code. The P code operates at 10.23 megabits per second and has a complete cycle of 267 days, each satellite generating an exclusive 7-day long segment of the code. Accordingly, the code generator in the receiver must be capable of extremely fine resolution in order to maintain track and synchronization of the code sequence timing in an environment where the Doppler shift of a 10.23 Mhz signal due to the user's vehicle motion may range from only a few Hertz to several hundred Hertz.

In accordance with the present invention, a first adder/accumulator circuit operating at the code clock frequency controls a dual modulus divider circuit to divide an input digital pulse signal by a fractional quantity to generate a nominal 10.23 MHz code clock. A binary signal representative of the desired Doppler shift is iteratively added it itself in a binary adder/accumulator circuit until a positive or negative overflow signal is generated. The overflow signal, coupled to the first adder/accumulator circuit, controls that circuit to alter the division ratio of the dual modulus divider circuit, thereby altering the code clock frequency by the desired amount.

The invention is pointed out with particularity in the appended claims; however, other objects and features will become more apparent and the invention itself will best be understood by referring to the following descriptions and embodiments taken in conjunction with the accompanying drawing in which:

FIG. 1 is a block diagram of a circuit in accordance with the present invention;

FIG. 2 is a detailed logic diagram showing the accumulator and associated circuitry of the present invention;

FIG. 3 is a logic diagram of the dual modulus divider of the circuit in accordance with the present invention; and

FIGS. 4 and 5 are timing diagrams useful in explaining the operation of the invention.

Referring now to the various views of the drawing for a detailed description of the operation, construction, and other features of the invention by characters of reference, FIG. 1 shows a dual modulus divider circuit 10 which in the presently described embodiment of the invention is implemented in emitter-coupled logic (ECL), and an ECL to CMOS level converter circuit 12. The horizontal broken line bifurcating FIG. 1 indicates a division between the kinds of circuit technology utilized in the implementation of the instant embodiment of the invention, the circuits above the broken line being ECL, and circuits below the line being large-scale integration complementary metal-oxide-semiconductor (LSI CMOS). The dual modulus divider circuit 10 receives via a line 14 an input signal having a frequency of (137/16) F.sub.o or 87.59 MHz from a pulse-digital external signal source (not shown), F.sub.o being 10.23 MHz. The dual modulus divider circuit 10 generates on a line 16 an output signal CODCLK having a nominal frequency of 10.23 MHz, the frequency of the CODCLK signal being a fractional submultiple by 16/137 of the input signal frequency. The dual modulus divider circuit 10 is implemented as a counter with D-bistables as shown in FIG. 3 to count 8 or 9 cycles of the input signal (137/16) F.sub.o in accordance with the count sequence shown in Table 1. A commercially available integrated circuit may be utilized for the dual modulus divider circuit 10; for example, the circuit 10 of the presently described embodiment is an SP8691A integrated circuit manufactured by Plessey Semiconductors. An extra logic state of the dual modulus divider circuit 10, indicated by an asterisk in Table 1, occurs when a control signal MOD89F, generated by a four-bit adder/accumulator circuit 18 (FIG. 1) and coupled to the dual modulus divider circuit 10 via a line 20 is enabled. The MOD89F signal thus controls the division ratio of the dual modulus divider circuit 10 in accordance with Table 2.

FIG. 4 shows the code clock signal output of the dual modulus divider circuit 10 with respect to the (137/16) F.sub.o input signal, the latter having a pulse period of 11.416 nanoseconds. The periods of the code clock signal shown in FIG. 4 corresponding with the .div.8 and .div.9 cycles and designated A and B in FIG. 4 have periods, respectively, of 45.665 and 57.081 nanoseconds. The code clock signal output thus is comprised of 4/8 duty cycle balanced square waves having a period of 91.33 nanoseconds, and 5/9 duty cycle unbalanced square waves with a period of 102.746 nanoseconds. The four-bit adder/accumulator circuit 18 is implemented as shown in FIG. 2 to add 9.sub.10 to itself each clock period, when two input signals thereto designated EIGHT and TEN are both enabled. When a nominal 10.23 MHz signal is being generated by the dual modulus divider 10, the four-bit adder/accumulator circuit 18 has a fixed addend of 9.sub.10 and counts as shown in Table 3, generating carries as the MOD89F control signal. During a period of 16 nominal cycles of the CODCLK signal, the 4-bit adder/accumulator circuit 18 generates nine MOD89F signals, resulting in nine .div.9 cycles and seven .div.8 cycles of the dual modulus divider circuit 10 yielding a fractional divisor of 137/16 and a nominal code CODCLK signal having a frequency F.sub.o or 10.23 MHz.

With respect to the dual modulus divider circuit 10, the bit values of the four-bit adder/accumulator are fractional, the most-significant bit having a value of 2.sup.-1 ; the least-significant bit, 2.sup.-4. The four-bit adder/accumulator circuit 18 thus generates fractional partial divisors 9/16 and 8/16 of the (137/16) F.sub.o input signal over a period of 16 cycles of the code clock, when the MOD89F signal is, respectively, enabled and disabled. A carry signal, i.e., the MOD89F signal, is thus generated at a rate which results in a nominal code clock signal of exactly 10.23 MHz with minimal phase noise.

A data item comprising a 16-bit fractional binary number representative of a desired Doppler shift to be imparted to the CODCLK signal generated by the dual modulus divider circuit 10 is strobed into a 16-bit holding register 22 via a data bus 24 coupled thereto from a computer (not shown) associated with the equipment utilizing the instant invention which may be, for example, a GPS receiver. The 16-bit binary number is loaded periodically in parallel into a 16-bit rate register 26 by a control signal T20F which in the presently described embodiment of the invention occurs every 20 milliseconds. A 16-bit binary adder 28 receives as one input thereto the output signals of the 16-bit rate register via a bus 30. The output signals of the adder 28 are clocked into a 16-bit accumulator 32 by a clock signal having a frequency of F.sub.o /30, which signal is derived from a (4/15) F.sub.o signal SYSCLK divided by eight, the F.sub.o /30 clock signal having a rate of 2.933 MHz. Output signals of the 16-bit accumulator 32 are coupled in parallel via a bus 34 to the 16-bit adder 28 as second inputs thereto. The data item strobed into the holding register 22 is in two's complement form. The 16-bit binary number in the rate register 26 is thus added to itself each 2.933 microseconds. A positive or a negative overflow of the 16-bit adder 28 results in the generation, respectively, of POV or NOV signals which are coupled to a latch circuit 36. The latch circuit 36 which is shown in detail in FIG. 2 regenerates the POV and NOV signals, respectively, as the EIGHT and TEN signals input to the four-bit adder/accumulator circuit 18. Upon the occurrence of a positive overflow from the adder 28, the EIGHT signal is disabled for one cycle of the CODCLK signal and the addend of the four-bit adder/accumulator circuit 18 is incremented to 8.sub.10 for one cycle; consequently the number of .div.9 cycles of the dual modulus divider circuit 10 is reduced with respect to the number of .div.8 cycles and the frequency of the CODCLK signal increases. Similarly, a negative overflow of the adder 28 disables the TEN signal and the addend of the four-bit adder/accumulator circuit 18 is incremented to 10.sub.10 for one cycle of the CODCLK signal resulting in a reduced frequency of the CODCLK signal. A data value of zero in the 16-bit rate register 26 results in the generation of the nominal frequency (10.23 MHz) of the CODCLK signal; positive and negative data values in the rate register 26 result, respectively, in higher and lower frequencies of the CODCLK signal. As frequency shifts occur, the circuit of the instant invention maintains phase continuity of the pulse train at the boundaries of changes in frequency. Long term drift of the code clock signal, a vital consideration in tracking a precision pseudo-random noise code such as the P code utilized in the GPS, is thus eliminated.

The range and resolution of the circuit of the present invention is shown as follows, where:

FiN=Clock to Dual Modulus Divider 10 (137 F.sub.o /16)

CODCLK=Code Clock Output; Clock to Four-Bit Adder/Accumulator 18

MOD89F=Carry from Four-bit Adder/Accumulator 18

f16=Clock to 16 Bit Accumulator 32 (F.sub.o /30)

R=Rate Value in 16 Bit Accumulator 32

NU=Upper Divide Modulus of Dual Modulus Divider (9)

NL=Lower Divide Modulus of Dual Modulus Divider (8) ##EQU1## Therefore, CODCLK=F.sub.o .+-.(0.5/4110) F.sub.o, and the range of the circuit=.+-.1.245 kHz about the nominal frequency of 10.23 MHz. The least significant bit of the rate register has a weight of 2.sup.-16. Therefore the resolution of the circuit of the presently described embodiment of the invention is 0.03798 Hz.

The circuit of the present invention is characterized by high resolution, low phase noise (in a digital pulse to digital pulse environment) and phase continuity at frequency-shift boundaries; a phase noise analysis follows. It is initially assumed that the .div.8 and .div.9 cycles are distributed over time so that the phase error of the code clock with respect to an ideal square wave does not exceed .+-..theta./2. ##EQU2## Assume the probability distribution of the phase error is uniform over the interval -.theta./2+.theta./2 ##EQU3## The average power output is: ##EQU4## Receiver performance penalty is therefore, 0.26 dB (with nominal CODCLK=F.sub.o output).

Each overflow from the 16-bit accumulator represents: ##EQU5## Peak-to-peak phase error is 7.3E-3 cycles=2.6.degree. ##EQU6## A performance penalty occurs only when the frequency of overflows is high compared to code-tracking bandwidth. Total performance penalty is 0.275 dB. Peak position error is: ##EQU7## This results in a pseudorange error only if the frequency of the overflows is low compared to the bandwidth of the code-tracking loop.

Referring now to FIGS. 1 and 2 in conjunction with FIG. 5, a dual modulus divider reset circuit 38 on the LSI CMOS chip generates a signal RST89F utilized to reset the ECL dual modulus divider circuit 10, the latter not being provided with a reset input. Because the code clock position must be known to within one period of the 137 F.sub.o /16 input clock, the reset circuit 38 is utilized to reset the dual modulus divider circuit 10. During a reset operation, the 137 F.sub.o /16 clock to the dual modulus divider circuit 10 is disabled and the dual modulus divider is clocked by the RST89F signal until a rising edge of the CODCLK signal resets bistable F2 of the reset circuit 38. The dual modulus divider circuit 10 remains in this state until the 137 F.sub.o /16 clock is restarted.

While the principles of the invention have now been made clear in the foregoing illustrative embodiment, there will be immediately obvious to those skilled in the art many modifications of structure, arrangement, proportions, the elements, material and components used in the practice of the invention, and otherwise, which are particularly adapted for specific environments and operating requirements without departing from those principles. The appended claims are, therefore, intended to cover and embrace any such modifications within the limits only of the true spirit and scope of the invention.